NXP Layerscape 2084A and 2044A Multicore Communications Processors Reference guide

LS2088A Security (SEC) Reference

Manual

Also supports LS2048A, LS2084A and LS2044A

Document Number: LS2088ASECRM

Rev. 0, 04/2018

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Contents

Section number Title Page

Chapter 1

Overview of SEC (security engine) functionality

Chapter 2

Feature summary

Chapter 3

SEC implementation

3.1 SEC submodules.........................................................................................................................................................91

3.2 Cryptographic engines implemented in SEC..............................................................................................................91

3.3 SEC Export-Controlled vs. non-Export-Controlled Versions.................................................................................... 92

Chapter 4

SEC modes of operation

4.1 Security Monitor (SecMon) security states.................................................................................................................95

4.1.1 The effect of security state on volatile keys...............................................................................................96

4.1.2 The effect of security state on non-volatile keys....................................................................................... 97

4.2 Keys available in different security modes.................................................................................................................97

4.2.1 Keys available in trusted mode.................................................................................................................. 97

4.2.2 Keys available in secure mode...................................................................................................................98

4.2.3 Keys available in non-secure mode........................................................................................................... 98

4.2.4 Keys available in fail mode........................................................................................................................99

Chapter 5

SEC hardware functional description

5.1 System Bus Interfaces.................................................................................................................................................102

5.1.1 AXI master (DMA) interface.....................................................................................................................102

5.1.1.1 DMA read-safe transactions...................................................................................................102

5.1.1.2 DMA interface write-safe transactions.................................................................................. 103

5.1.1.3 DMA write-efficient transactions.......................................................................................... 103

5.1.1.4 DMA bursts that may read past the end of data structures.................................................... 104

5.1.2 Register interface (IP bus)..........................................................................................................................105

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5.2 SEC service interface concepts...................................................................................................................................106

5.2.1 SEC descriptors..........................................................................................................................................106

5.2.2 Job termination status/error codes..............................................................................................................108

5.2.3 Frames and flows....................................................................................................................................... 115

5.2.4 Frame descriptors and frames.................................................................................................................... 116

5.2.5 Frame descriptor flow and flow context.................................................................................................... 116

5.2.6 Buffer allocation, release, and reuse.......................................................................................................... 117

5.2.7 User data access control and isolation....................................................................................................... 118

5.3 Service interfaces........................................................................................................................................................118

5.3.1 Job Ring interface...................................................................................................................................... 119

5.3.1.1 Configuring and managing the input/output rings, overview................................................ 120

5.3.1.2 Managing the input rings....................................................................................................... 122

5.3.1.3 Managing the output rings..................................................................................................... 123

5.3.1.4 Controlling access to Job Rings.............................................................................................124

5.3.1.5 Order of job completion.........................................................................................................124

5.3.1.6 Initializing Job Rings............................................................................................................. 125

5.3.1.7 Job Ring Registers................................................................................................................. 125

5.3.1.8 Asserting Job Ring interrupts.................................................................................................125

5.3.2 Queue Manager Interface (QI)...................................................................................................................126

5.3.2.1 Requesting and receiving frame descriptors from QMan...................................................... 127

5.3.2.2 Building job descriptors for QI jobs...................................................................................... 129

5.3.2.3 Controlling QI access to frame queues and data....................................................................129

5.3.2.4 Tracking the completion order of QI jobs..............................................................................130

5.3.2.5 Initializing the Queue Manager Interface.............................................................................. 130

5.3.2.6 Done/error notification for QI jobs........................................................................................ 131

5.3.3 Advanced IO Processor Interface (AI).......................................................................................................132

5.3.3.1 Receiving frame descriptors from AIOP............................................................................... 133

5.3.3.2 Building job descriptors for AI jobs...................................................................................... 134

5.3.3.3 Controlling AI access to data.................................................................................................135

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5.3.3.4 Tracking the order of completion of AI jobs......................................................................... 135

5.3.3.5 Initializing the AIOP interface...............................................................................................136

5.3.3.6 Done/error notification for AI jobs........................................................................................ 136

5.3.4 Register-based service interface.................................................................................................................137

5.4 Job scheduling.............................................................................................................................................................139

5.4.1 Job scheduling - default algorithm.............................................................................................................139

5.4.2 Job scheduling - adaptive resource reservation algorithm.........................................................................142

5.4.3 Job scheduling - DECO-specific jobs........................................................................................................ 145

5.5 Job execution hardware...............................................................................................................................................146

5.5.1 Descriptor controller (DECO) and cryptographic control block (CCB)....................................................146

5.5.1.1 Alignment blocks................................................................................................................... 147

5.5.2 Cryptographic hardware accelerators (CHAs) (overview)........................................................................ 148

Chapter 6

Frame queues, frame descriptors, and buffers

6.1 Frame queues.............................................................................................................................................................. 151

6.1.1 Dequeue response...................................................................................................................................... 152

6.2 Multi-partition resource access...................................................................................................................................153

6.2.1 Multi-partition resource access modes.......................................................................................................154

6.2.2 Flow context selection restrictions.............................................................................................................157

6.2.3 Inline job descriptor restrictions................................................................................................................ 158

6.2.4 Replacement job descriptor restrictions.....................................................................................................158

6.2.5 Non-local jump limitations........................................................................................................................ 159

6.2.6 Multi-partition resource access restriction summary.................................................................................159

6.3 Frame descriptors........................................................................................................................................................160

6.3.1 Flow Context..............................................................................................................................................160

6.3.2 Processing single frame jobs......................................................................................................................168

6.3.3 Processing frame list jobs.......................................................................................................................... 170

6.3.4 Frame descriptor error handling.................................................................................................................171

6.3.5 Job descriptor construction from frame descriptor.................................................................................... 172

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Chapter 7

Descriptors and descriptor commands

7.1 Job descriptors............................................................................................................................................................ 175

7.2 Trusted descriptors......................................................................................................................................................177

7.3 Shared descriptors.......................................................................................................................................................179

7.3.1 Executing shared descriptors in proper order............................................................................................ 180

7.3.2 Specifying different types of shared descriptor sharing.............................................................................181

7.3.2.1 Error sharing.......................................................................................................................... 183

7.3.3 Changing shared descriptors...................................................................................................................... 183

7.4 Using in-line descriptors.............................................................................................................................................184

7.5 Using replacement job descriptors..............................................................................................................................185

7.6 Scatter/gather tables (SGTs)....................................................................................................................................... 187

7.7 Using descriptor commands........................................................................................................................................190

7.7.1 Command execution order.........................................................................................................................190

7.7.1.1 Executing commands when SHR = 0.................................................................................... 192

7.7.1.2 Executing commands when SHR = 1.................................................................................... 193

7.7.1.3 Executing commands when REO = 0.................................................................................... 193

7.7.1.4 Executing commands when REO = 1.................................................................................... 194

7.7.1.5 Executing additional HEADER commands...........................................................................195

7.7.1.6 Jumping to another job descriptor..........................................................................................196

7.7.2 Command properties..................................................................................................................................197

7.7.2.1 Blocking commands...............................................................................................................197

7.7.2.2 Load/store checkpoint............................................................................................................197

7.7.2.3 Done checkpoint.................................................................................................................... 197

7.7.3 Command types..........................................................................................................................................198

7.7.4 SEQ vs non-SEQ commands..................................................................................................................... 199

7.7.4.1 Creating a sequence............................................................................................................... 200

7.7.4.2 Using sequences for fixed and variable length data...............................................................201

7.7.4.3 Transferring meta data........................................................................................................... 202

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7.7.4.4 Rewinding a sequence............................................................................................................203

7.7.5 Information FIFO entries........................................................................................................................... 204

7.7.6 Output FIFO Operation..............................................................................................................................204

7.7.7 Output Checksum logic..............................................................................................................................207

7.7.8 Cryptographic class....................................................................................................................................208

7.7.9 Address pointers.........................................................................................................................................209

7.8 HEADER command....................................................................................................................................................210

7.9 KEY commands..........................................................................................................................................................215

7.10 LOAD commands....................................................................................................................................................... 219

7.11 FIFO LOAD command...............................................................................................................................................231

7.11.1 Bit length data............................................................................................................................................ 234

7.11.2 FIFO LOAD input data type ..................................................................................................................... 235

7.12 ECPARAM command................................................................................................................................................ 237

7.13 STORE command.......................................................................................................................................................241

7.14 FIFO STORE command............................................................................................................................................. 249

7.15 MOVE, MOVEB, MOVEDW, and MOVE_LEN commands................................................................................... 255

7.16 ALGORITHM OPERATION command.................................................................................................................... 264

7.17 PROTOCOL OPERATION commands..................................................................................................................... 270

7.18 PKHA OPERATION command................................................................................................................................. 290

7.18.1 PKHA OPERATION: clear memory function...........................................................................................292

7.18.2 PKHA OPERATION: Arithmetic Functions.............................................................................................293

7.18.3 PKHA OPERATION: copy memory functions.........................................................................................299

7.18.4 PKHA OPERATION: Elliptic Curve Functions........................................................................................302

7.19 SIGNATURE command............................................................................................................................................. 305

7.20 JUMP (HALT) command........................................................................................................................................... 308

7.20.1 Jump type................................................................................................................................................... 308

7.20.1.1 Local conditional jump.......................................................................................................... 309

7.20.1.2 Local conditional increment/decrement jump........................................................................309

7.20.1.3 Non-local conditional jump................................................................................................... 310

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7.20.1.4 Conditional halt......................................................................................................................310

7.20.1.5 Conditional halt with user-specified status............................................................................ 311

7.20.1.6 Conditional subroutine call.................................................................................................... 312

7.20.1.7 Conditional subroutine return................................................................................................ 312

7.20.2 Test type.....................................................................................................................................................313

7.20.3 JSL and TEST CONDITION fields...........................................................................................................313

7.20.4 JUMP command format.............................................................................................................................315

7.21 MATH and MATHI Commands.................................................................................................................................318

7.22 SEQ IN PTR command...............................................................................................................................................325

7.23 SEQ OUT PTR command...........................................................................................................................................329

Chapter 8

Public Key Cryptography Operations

8.1 Conformance considerations.......................................................................................................................................333

8.2 Discrete-log key-pair generation.................................................................................................................................334

8.2.1 Inputs to the discrete-log key-pair generation function............................................................................. 335

8.2.2 Assumptions of the discrete-log key-pair generation function.................................................................. 335

8.2.3 Outputs from the discrete-log key-pair generation function......................................................................335

8.2.4 Operation of the discrete-log key-pair generation function.......................................................................335

8.2.5 Notes associated with the discrete-log key-pair generation function ........................................................336

8.3 Using the Diffie_Hellman function............................................................................................................................ 340

8.3.1 Diffie_Hellman requirements.................................................................................................................... 340

8.3.2 Inputs to the Diffie-Hellman function........................................................................................................340

8.3.3 Assumptions of the Diffie-Hellman function.............................................................................................341

8.3.4 Outputs from the Diffie-Hellman function................................................................................................ 341

8.3.5 Operation of the Diffie-Hellman function................................................................................................. 341

8.3.6 Notes associated with the Diffie-Hellman function...................................................................................341

8.4 Generating DSA and ECDSA signatures....................................................................................................................342

8.4.1 Inputs to the DSA and ECDSA signature generation function..................................................................343

8.4.2 Assumptions of the DSA and ECDSA signature generation function.......................................................343

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8.4.3 Outputs from the DSA and ECDSA signature generation function...........................................................343

8.4.4 Operation of the DSA and ECDSA signature generation function ...........................................................344

8.4.5 Notes associated with the DSA and ECDSA Signature Generation function............................................344

8.5 Verifying DSA and ECDSA signatures......................................................................................................................347

8.5.1 Inputs to the DSA and ECDSA signature verification function................................................................ 348

8.5.2 Assumptions of the DSA and ECDSA signature verification function..................................................... 348

8.5.3 Outputs from the DSA and ECDSA signature verification function.........................................................348

8.5.4 Operation of the DSA and ECDSA signature verification function ......................................................... 348

8.5.5 Notes associated with the DSA and ECDSA Signature Verification function .........................................349

8.6 RSA Finalize Key Generation (RFKG)...................................................................................................................... 352

8.7 Implementation of the RSA encrypt operation........................................................................................................... 353

8.8 Implementation of the RSA decrypt operation........................................................................................................... 355

Chapter 9

Protocol acceleration

9.1 IPsec ESP encapsulation and decapsulation overview............................................................................................... 363

9.1.1 IPsec ESP encapsulation and decapsulation mode support....................................................................... 365

9.1.2 IPsec ESP error codes................................................................................................................................ 365

9.1.3 Programming for IPsec ............................................................................................................................. 366

9.1.3.1 PDB format for IPsec ESP Transport (and Legacy Tunnel) encapsulation...........................367

9.1.3.2 Common PDB format descriptions for IPsec ESP Transport (and Legacy Tunnel)

decapsulation..........................................................................................................................370

9.1.3.3 Overriding ESP Transport (and legacy Tunnel) PDB content with the DECO Protocol

Override Register................................................................................................................... 373

9.1.3.4 PDB format for IPsec ESP Tunnel encapsulation .................................................................374

9.1.3.5 Common PDB format descriptions for IPsec ESP Tunnel decapsulation............................. 377

9.1.3.6 Overriding ESP Tunnel PDB content with the DECO Protocol Override Register.............. 380

9.1.3.7 IPsec ESP encapsulation CBC-specific PDB segment format descriptions.......................... 382

9.1.3.8 IPsec ESP encapsulation AES-CTR-specific PDB segment format descriptions..................383

9.1.3.9 IPsec ESP encapsulation AES-CCM-specific PDB segment format descriptions................ 383

9.1.3.10 IPsec ESP encapsulation AES-GCM-specific PDB segment format descriptions................ 384

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9.1.3.11 IPsec ESP decapsulation CBC-specific PDB segment format descriptions.......................... 384

9.1.3.12 IPsec ESP decapsulation AES-CTR-specific PDB segment format descriptions..................385

9.1.3.13 IPsec ESP decapsulation AES-CCM-specific PDB segment format descriptions................ 385

9.1.3.14 IPsec ESP decapsulation AES-GCM-specific PDB segment format descriptions................ 385

9.1.4 IPsec ESP Transport (and Legacy Tunnel) encapsulation overview......................................................... 386

9.1.4.1 Encapsulating the IP header in tunnel mode..........................................................................387

9.1.4.2 Encapsulating the IP header in transport mode......................................................................387

9.1.4.3 Process for IPsec ESP Transport (and Legacy Tunnel) encapsulation.................................. 388

9.1.5 IPsec ESP Cryptographic Encapsulation................................................................................................... 389

9.1.5.1 Process for IPsec encapsulation when using AES-CBC or DES-CBC..................................389

9.1.5.2 Process for IPsec encapsulation when using AES-CTR........................................................ 391

9.1.5.3 Process for IPsec encapsulation when using AES-CCM.......................................................392

9.1.5.4 Process for IPsec encapsulation when using AES-GCM.......................................................394

9.1.6 IPsec ESP Transport (and Legacy Tunnel) decapsulation procedure overview........................................ 395

9.1.6.1 IPsec ESP Transport Mode outer IP header decapsulation procedure...................................397

9.1.6.2 IPsec ESP Transport (and Legacy Tunnel) outer IP header decapsulation procedure

(tunnel mode)......................................................................................................................... 397

9.1.7 IPsec ESP Cryptographic Decapsulation................................................................................................... 398

9.1.7.1 IPsec decapsulation procedure when using AES-CBC or DES-CBC....................................398

9.1.7.2 Process for IPsec decapsulation when using AES-CTR........................................................ 400

9.1.7.3 Process for IPsec decapsulation when using AES-CCM.......................................................401

9.1.7.4 Process for IPsec decapsulation when using AES-GCM.......................................................402

9.1.7.5 Use of SPI and the sequence number in decapsulation..........................................................403

9.1.7.6 Optional use of ESN in ESP decapsulation........................................................................... 404

9.1.7.7 Anti-replay checking in IPsec ESP decapsulation................................................................. 404

9.1.7.7.1 When anti-replay checking is enabled.............................................................. 405

9.1.7.7.2 When anti-replay checking is disabled............................................................. 405

9.1.7.8 ICV checking during IPsec ESP decapsulation..................................................................... 406

9.1.8 IPsec ESP Tunnel encapsulation overview................................................................................................406

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9.1.8.1 Handling the Outer IP Header during ESP Tunnel encapsulation.........................................406

9.1.8.2 Outer IP Header handling with UDP-encapsulated-ESP....................................................... 408

9.1.8.3 ESP Tunnel Outer IP Header manipulation........................................................................... 408

9.1.8.4 ESP Tunnel handling of Next Header....................................................................................409

9.1.9 IPsec ESP tunnel decapsulation overview................................................................................................. 409

9.1.9.1 Input material preceding the outer IP header.........................................................................410

9.1.9.2 Handling the Outer IP Header during ESP Tunnel decapsulation.........................................410

9.1.9.3 Manipulation of the Inner IP Header during ESP Tunnel decapsulation...............................411

9.1.9.4 Decapsulation Output Frame Length..................................................................................... 411

9.2 SSL/TLS/DTLS record encapsulation and decapsulation overview.......................................................................... 412

9.2.1 Programming and processing details common to all versions of SSL, TLS, and DTLS...........................413

9.2.1.1 PDB use and format for SSL, TLS, and DTLS encapsulation and decapsulation.................413

9.2.1.1.1 PDB for SSL, TLS, and DTLS when a Block Cipher is used.......................... 414

9.2.1.1.2 PDB for SSL, TLS, and DTLS when AES-Counter mode is used...................415

9.2.1.1.3 PDB for TLS and DTLS when AES-GCM is used...........................................416

9.2.1.1.4 PDB for TLS and DTLS when AES-CCM is used...........................................417

9.2.1.1.5 Programming the Options byte with the PDB for SSL, TLS and DTLS..........417

9.2.1.2 Overriding the PDB for SSL, TLS, and DTLS Encapsulation.............................................. 419

9.2.1.3 Computing the pre-encrypted record length during decapsulation........................................420

9.2.1.4 SSL, TLS, DTLS Decapsulation Output frame options.........................................................422

9.2.1.5 SSL / TLS / DTLS error codes...............................................................................................423

9.2.2 Process for SSL 3.0 and TLS 1.0 record encapsulation.............................................................................424

9.2.2.1 Differences between SSL 3.0 and TLS 1.0 (record encapsulation)....................................... 425

9.2.2.2 Processing SSL 3.0 and TLS 1.0 record encapsulation with block ciphers...........................425

9.2.3 Process for SSL 3.0 and TLS 1.0 record decapsulation.............................................................................427

9.2.3.1 SSL 3.0 and TLS 1.0 Record Decapsulation for block ciphers............................................. 427

9.2.3.2 Differences between SSL 3.0 and TLS 1.0 (record decapsulation)....................................... 428

9.2.4 Process for TLS 1.1 and TLS 1.2 record encapsulation.............................................................................429

9.2.4.1 Differences between TLS 1.0, TLS 1.1, and TLS 1.2 Record Encapsulation....................... 429

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9.2.4.2 Support for IV generation in TLS 1.1 and TLS 1.2 record encapsulation.............................430

9.2.4.3 Processing TLS 1.1 and TLS 1.2 record encapsulation with block ciphers (AES or DES).. 432

9.2.4.4 Processing TLS 1.1 and TLS 1.2 record encapsulation with stream ciphers.........................433

9.2.4.5 Processing TLS 1.1 and TLS 1.2 record encapsulation with AEAD ciphers........................ 434

9.2.5 Process for TLS 1.1 and TLS 1.2 record decapsulation.............................................................................435

9.2.5.1 Decapsulation of TLS 1.1 and TLS 1.2 records when a stream cipher is used......................436

9.2.5.2 Decapsulation of TLS 1.1 and TLS 1.2 records when a block cipher is used....................... 438

9.2.5.3 Decapsulation of TLS 1.2 records when an AEAD is used...................................................439

9.2.6 Process for DTLS record encapsulation.....................................................................................................440

9.2.6.1 Differences between DTLS and TLS.....................................................................................441

9.2.6.2 Process of DTLS Record Encapsulation when using a Block Cipher................................... 441

9.2.6.3 Process of DTLS Record Encapsulation when using a Stream Cipher..................................443

9.2.6.4 DTLS 1.2 Record Encapsulation when using an AEAD Cipher........................................... 444

9.2.7 Process for DTLS record decapsulation.....................................................................................................445

9.2.7.1 Differences between DTLS and TLS.....................................................................................446

9.2.7.2 Process of DTLS Record Decapsulation when using a Block Cipher................................... 446

9.2.7.3 Process of DTLS Record Decapsulation when using a Stream Cipher................................. 448

9.2.7.4 DTLS 1.2 Record Decapsulation when using an AEAD Cipher........................................... 449

9.3 SRTP packet encapsulation and decapsulation...........................................................................................................451

9.3.1 Building the initial counter value (Counter IV).........................................................................................452

9.3.2 Building the AEAD Nonce........................................................................................................................ 452

9.3.3 Constructing the AESA context from the SRTP AEAD Nonce for AES-CCM mode..............................453

9.3.4 SRTP encapsulation................................................................................................................................... 454

9.3.4.1 Process for SRTP encapsulation............................................................................................ 455

9.3.4.2 Handling the optional MKI....................................................................................................456

9.3.4.3 SRTP encapsulation PDB format descriptions...................................................................... 456

9.3.4.4 SRTP encapsulation error conditions.....................................................................................457

9.3.5 SRTP decapsulation overview................................................................................................................... 457

9.3.5.1 Process for SRTP decapsulation............................................................................................ 458

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9.3.5.2 SRTP decapsulation PDB format descriptions...................................................................... 459

9.3.5.3 SRTP decapsulation error conditions.....................................................................................461

9.4 IEEE 802.1AE MACsec encapsulation and decapsulation overview.........................................................................461

9.4.1 Process for 802.1AE MACsec encapsulation............................................................................................ 462

9.4.1.1 Using the frame check sequence (FCS)................................................................................. 464

9.4.1.2 Additional notes for GMAC support..................................................................................... 465

9.4.2 MACsec encapsulation PDB format descriptions......................................................................................466

9.4.3 Process for 802.1AE MACSec decapsulation............................................................................................467

9.4.3.1 Automatically switching between two keys...........................................................................469

9.4.3.2 Additional notes for GMAC support (decapsulation)............................................................470

9.4.4 MACsec decapsulation PDB format descriptions......................................................................................470

9.5 IEEE 802.11 -2012 WPA2 MPDU encapsulation and decapsulation........................................................................ 471

9.5.1 Processing Common to WPA2 Encapsulation and Decapsulation............................................................ 472

9.5.1.1 Constructing the AAD for WPA2 encapsulation and decapsulation..................................... 472

9.5.1.2 Constructing the CCMP Nonce for WPA2 encapsulation and decapsulation....................... 473

9.5.1.3 Constructing the AESA context for WPA2 CCMP encapsulation and decapsulation.......... 473

9.5.2 Process for WPA2 encapsulation...............................................................................................................474

9.5.2.1 Constructing the CCMP header for WPA2 encapsulation.....................................................475

9.5.2.2 WPA2 Payload Encapsulation............................................................................................... 476

9.5.2.3 Computing the FCS for WPA2 encapsulation....................................................................... 476

9.5.2.4 WPA2 encapsulation PDB format descriptions.....................................................................476

9.5.2.5 WPA2 encapsulation error conditions................................................................................... 478

9.5.3 Process for WPA2 decapsulation...............................................................................................................478

9.5.3.1 WPA2 Decapsulation Anti-replay checking..........................................................................479

9.5.3.2 Using automatic key-switching..............................................................................................480

9.5.3.3 WPA2 decapsulation PDB format descriptions.....................................................................480

9.5.3.4 WPA2 decapsulation error conditions................................................................................... 481

9.6 IEEE 802.16 WiMAX encapsulation and decapsulation overview............................................................................482

9.6.1 Process for IEEE 802.16 WiMAX encapsulation......................................................................................483

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9.6.2 IEEE 802.16 WiMAX encapsulation PDB format descriptions................................................................485

9.6.3 WiMax encapsulation error conditions......................................................................................................486

9.6.4 Procedure for IEEE 802.16 WiMAX decapsulation..................................................................................486

9.6.4.1 Transforming the GMH (WiMAX decapsulation).................................................................488

9.6.4.2 Automatic key switching (WiMAX decapsulation)...............................................................489

9.6.5 IEEE 802.16 WiMAX decapsulation PDB format descriptions................................................................489

9.6.6 WiMAX decapsulation error conditions....................................................................................................490

9.7 Anti-Replay built-in checking.....................................................................................................................................490

9.8 Process for 3G double-CRC encapsulation and decapsulation...................................................................................493

9.8.1 3G double-CRC encapsulation process......................................................................................................494

9.8.1.1 Calculating the 7-bit CRC of the PDU header for encapsulation.......................................... 494

9.8.1.2 Calculating the 11-bit CRC of the PDU header for encapsulation........................................ 495

9.8.1.3 Calculating the 16-bit payload CRC for encapsulation......................................................... 496

9.8.2 3G double-CRC encapsulation PDB format descriptions..........................................................................496

9.8.3 3G double-CRC decapsulation process......................................................................................................496

9.8.3.1 Calculating the 7-bit CRC of the PDU header for decapsulation.......................................... 497

9.8.3.2 Calculating the 11-bit CRC of the PDU header for decapsulation........................................ 497

9.8.3.3 Calculating the 16-bit payload CRC for decapsulation......................................................... 498

9.8.4 3G double-CRC decapsulation PDB format descriptions..........................................................................498

9.9 3G RLC PDU Encapsulation and Decapsulation overview........................................................................................499

9.9.1 3G RLC PDU encapsulation overview...................................................................................................... 499

9.9.2 Process for 3G RLC PDU encapsulation................................................................................................... 500

9.9.3 3G RLC PDU encapsulation PDB format descriptions............................................................................. 501

9.9.4 3G RLC PDU decapsulation overview...................................................................................................... 502

9.9.5 Process for 3G RLC PDU decapsulation................................................................................................... 503

9.9.6 3G RLC PDU decapsulation PDB format descriptions............................................................................. 504

9.9.7 Overriding the PDB for 3G RLC PDU encapsulation and decapsulation................................................. 504

9.10 LTE PDCP PDU encapsulation and decapsulation overview.....................................................................................505

9.10.1 LTE PDCP PDU IV generation................................................................................................................. 506

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9.10.2 LTE PDCP PDU encapsulation process for confidentiality only.............................................................. 509

9.10.3 LTE PDCP PDU encapsulation for confidentiality and integrity..............................................................511

9.10.4 LTE PDCP PDU decapsulation process for confidentiality only.............................................................. 512

9.10.5 LTE PDCP PDU decapsulation for confidentiality and integrity..............................................................513

9.10.6 LTE PDCP shared descriptor PDB format descriptions............................................................................ 515

9.10.7 Overriding the PDB for LTE PDCP encapsulation and decapsulation......................................................515

Chapter 10

Key agreement functions

10.1 IKEv2 PRF overview..................................................................................................................................................517

10.1.1 Using IKE PRF to generate SKEYSEED.................................................................................................. 518

10.1.2 Using IKE PRF+ to generate keying material for the IKEv2 SA.............................................................. 518

10.1.3 Using IKE PRF+ to generate Child SA key material.................................................................................519

10.1.4 Restrictions on programming control blocks.............................................................................................519

10.1.5 IKE PRF PDB format descriptions............................................................................................................ 520

10.1.6 Implementation details for IKE PRF function........................................................................................... 523

10.1.7 Implementation Details for IKE PRF+ function........................................................................................524

10.2 SSL/TLS/DTLS pseudo-random functions (PRF)......................................................................................................525

10.2.1 SSL 3.0 PRF overview...............................................................................................................................525

10.2.1.1 SSL 3.0 PRF definitions.........................................................................................................526

10.2.2 Process for SSL 3.0 PRF............................................................................................................................527

10.2.3 SSL 3.0 PRF PDB format descriptions......................................................................................................527

10.2.4 TLS 1.0/TLS 1.1/DTLS PRF overview..................................................................................................... 530

10.2.4.1 TLS PRF RFC definitions......................................................................................................532

10.2.5 Process for TLS 1.0, TLS 1.1, DTLS PRF................................................................................................ 533

10.2.5.1 How TLS uses PRF material..................................................................................................533

10.2.5.2 Concatenating input material into one input string (TLS 1.0/1.1/DTLS)..............................534

10.2.6 TLS 1.0, TLS 1.1, DTLS PRF PDB format descriptions...........................................................................535

10.2.7 TLS 1.2 PRF overview...............................................................................................................................538

10.2.8 Process for TLS 1.2 PRF............................................................................................................................539

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10.2.8.1 Concantenating input material into one input string (TLS 1.2)............................................. 540

10.2.8.2 How TLS uses PRF material (TLS 1.2).................................................................................540

10.2.9 TLS 1.2 PRF PDB format descriptions......................................................................................................541

10.3 Implementation of the derived key protocol...............................................................................................................543

10.3.1 Using DKP with HMAC keys....................................................................................................................544

10.3.2 Implementation of the Blob Protocol.........................................................................................................545

Chapter 11

Cryptographic hardware accelerators (CHAs)

11.1 Public-key hardware accelerator (PKHA) functionality.............................................................................................548

11.1.1 Modular math.............................................................................................................................................549

11.1.2 About Montgomery values.........................................................................................................................549

11.1.3 Non-modular Math.....................................................................................................................................551

11.1.4 Elliptic-Curve Math................................................................................................................................... 551

11.1.4.1 ECC_MOD: Point math on a standard curve over a prime field (Fp)................................... 552

11.1.4.2 ECC_F2M: Point math on a standard curve over a binary field (F2m).................................553

11.1.5 PKHA Mode Register................................................................................................................................ 553

11.1.6 PKHA functions.........................................................................................................................................554

11.1.6.1 Copy memory, N-Size and Source-Size (COPY_NSZ and COPY_SSZ)............................. 555

11.1.6.2 Clear Memory (CLEAR_MEMORY) function..................................................................... 556

11.1.6.3 Arithmetic Functions..............................................................................................................557

11.1.6.3.1 Integer Modular Addition (MOD_ADD) function........................................... 557

11.1.6.3.2 Integer Modular Subtraction (MOD_SUB_1) function....................................558

11.1.6.3.3 Integer Modular Subtraction (MOD_SUB_2) function....................................558

11.1.6.3.4 Integer Modular Multiplication (MOD_MUL).................................................559

11.1.6.3.5 Integer Modular Multiplication with Montgomery Inputs (MOD_MUL_IM).559

11.1.6.3.6 Integer Modular Multiplication with Montgomery Inputs and Outputs

(MOD_MUL_IM_OM) Function..................................................................... 560

11.1.6.3.7 Integer Modular Exponentiation (MOD_EXP and MOD_EXP_TEQ)............561

11.1.6.3.8 Integer Modular Exponentiation, Montgomery Input (MOD_EXP_IM and

MOD_EXP_IM_TEQ) Function...................................................................... 562

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11.1.6.3.9 Integer Simultaneous Modular Exponentiation (MOD_SML_EXP)............... 562

11.1.6.3.10 Integer Modular Square (MOD_SQR and MOD_SQR_TEQ).........................563

11.1.6.3.11 Integer Modular Square, Montgomery inputs (MOD_SQR_IM and

MOD_SQR_IM_TEQ)..................................................................................... 564

11.1.6.3.12 Integer Modular Square, Montgomery inputs and outputs

(MOD_SQR_IM_OM and MOD_SQR_IM_OM_TEQ)................................. 564

11.1.6.3.13 Integer Modular Cube (MOD_CUBE and MOD_CUBE_TEQ)......................565

11.1.6.3.14 Integer Modular Cube, Montgomery input (MOD_CUBE_IM and

MOD_CUBE_IM_TEQ)...................................................................................566

11.1.6.3.15 Integer Modular Cube, Montgomery input and output

(MOD_CUBE_IM_OM and MOD_CUBE_IM_OM_TEQ)............................566

11.1.6.3.16 Integer Modulo Reduction (MOD_AMODN)..................................................567

11.1.6.3.17 Integer Modular Inversion (MOD_INV).......................................................... 568

11.1.6.3.18 Integer Montgomery Factor Computation (MOD_R2).....................................568

11.1.6.3.19 Integer Greatest Common Divisor (MOD_GCD).............................................569

11.1.6.3.20 Miller_Rabin Primality Test (PRIME_TEST)..................................................569

11.1.6.3.21 Right Shift A (RIGHT_SHIFT_A) function.....................................................570

11.1.6.3.22 Compare A B (COMPARE) function...............................................................570

11.1.6.3.23 Evaluate A (EVALUATE) function................................................................. 571

11.1.6.3.24 Binary Polynomial (F2m) Addition (F2M_ADD) function..............................571

11.1.6.3.25 Binary Polynomial (F2m) Modular Multiplication (F2M_MUL).................... 572

11.1.6.3.26 Binary Polynomial (F2m) Modular Multiplication with Montgomery Inputs

(F2M_MUL_IM) Function...............................................................................573

11.1.6.3.27 Binary Polynomial (F2m) Modular Multiplication with Montgomery Inputs

and Outputs (F2M_MUL_IM_OM) Function.................................................. 573

11.1.6.3.28 Binary Polynomial (F2m) Modular Exponentiation (F2M_EXP and

F2M_EXP_TEQ)..............................................................................................574

11.1.6.3.29 Binary Polynomial (F2m) Simultaneous Modular Exponentiation

(F2M_SML_EXP)............................................................................................ 575

11.1.6.3.30 Binary Polynomial (F2m) Modular Square (F2M_SQR and

F2M_SQR_TEQ)..............................................................................................576

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11.1.6.3.31 Binary Polynomial (F2m) Modular Square, Montgomery Input

(F2M_SQR_IM and F2M_SQR_IM_TEQ)..................................................... 576

11.1.6.3.32 Binary Polynomial (F2m) Modular Square, Montgomery Input and Output

(F2M_SQR_IM_OM and F2M_SQR_IM_OM_TEQ).....................................577

11.1.6.3.33 Binary Polynomial (F2m) Modular Cube (F2M_CUBE and

F2M_CUBE_TEQ)...........................................................................................578

11.1.6.3.34 Binary Polynomial (F2m) Modular Cube, Montgomery Input

(F2M_CUBE_IM and F2M_CUBE_IM_TEQ)................................................579

11.1.6.3.35 Binary Polynomial (F2m) Modular Cube, Montgomery Input and Output

(F2M_CUBE_IM_OM and F2M_CUBE_IM_OM_TEQ)...............................579

11.1.6.3.36 Binary Polynomial (F2m) Modulo Reduction (F2M_AMODN)..................... 580

11.1.6.3.37 Binary Polynomial (F2m) Modular Inversion (F2M_INV)..............................581

11.1.6.3.38 Binary Polynomial (F2m) R2 Mod N (F2M_R2) Function..............................581

11.1.6.3.39 Binary Polynomial (F2m) Greatest Common Divisor (F2M_GCD) Function.582

11.1.6.4 Elliptic Curve Functions........................................................................................................ 582

11.1.6.4.1 ECC Fp Point Add, Affine Coordinates (ECC_MOD_ADD) Function...........582

11.1.6.4.2 ECC Fp Point Add, Affine Coordinates, R2 Mod N Input

(ECC_MOD_ADD_R2) Function.................................................................... 583

11.1.6.4.3 ECC Fp Point Double, Affine Coordinates (ECC_MOD_DBL) Function.......584

11.1.6.4.4 ECC Fp Point Multiply, Affine Coordinates (ECC_MOD_MUL and

ECC_MOD_MUL_TEQ) Function.................................................................. 584

11.1.6.4.5 ECC Fp Point Multiply, R2 Mod N Input, Affine Coordinates

(ECC_MOD_MUL_R2 and ECC_MOD_MUL_R2_TEQ) Function..............586

11.1.6.4.6 ECC Fp Check Point (ECC_MOD_CHECK_POINT) Function..................... 587

11.1.6.4.7 ECC Fp Check Point, R2 Mod N Input, Affine Coordinates

(ECC_MOD_CHECK_POINT_R2) Function..................................................588

11.1.6.4.8 ECC F2m Point Add, Affine Coordinates (ECC_F2M_ADD) Function......... 589

11.1.6.4.9 ECC F2m Point Add, Affine Coordinates, R2 Mod N Input

(ECC_F2M_ADD_R2) Function......................................................................589

11.1.6.4.10 ECC F2m Point Double - Affine Coordinates (ECC_F2M_DBL) Function....590

11.1.6.4.11 ECC F2m Point Multiply, Affine Coordinates (ECC_F2M_MUL and

ECC_F2M_MUL_TEQ) Function....................................................................591

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11.1.6.4.12 ECC F2m Point Multiply, R2 Mod N Input, Affine Coordinates

(ECC_F2M_MUL_R2 and ECC_F2M_MUL_R2_TEQ) Function.................592

11.1.6.4.13 ECC F2m Check Point (ECC_F2M_CHECK_POINT) Function....................593

11.1.6.4.14 ECC F2m Check Point, R2 (ECC_F2M_CHECK_POINT_R2) Function.......594

11.1.6.4.15 ECM Modular Multiplication (ECM_MOD_MUL_X and

ECM_MOD_MUL_X_TEQ) Function............................................................ 595

11.1.6.4.16 ECM Fp Point Multiply, R2 Mod N Input, Affine Coordinates

(ECM_MOD_MUL_X_R2 and ECM_MOD_MUL_X_R2_TEQ) Function.. 596

11.1.6.4.17 ECT Modular Multiplication (ECT_MOD_MUL and

ECT_MOD_MUL_TEQ) Function.................................................................. 597

11.1.6.4.18 ECT Fp Point Multiply, R2 Mod N Input, Affine Coordinates

(ECT_MOD_MUL_R2 and ECT_MOD_MUL_R2_TEQ) Function.............. 599

11.1.6.4.19 ECT Fp Point Add, Affine Coordinates (ECT_MOD_ADD) Function........... 600

11.1.6.4.20 ECT Fp Point Add, Affine Coordinates, R2 Mod N Input

(ECT_MOD_ADD_R2) Function.................................................................... 600

11.1.6.4.21 ECT Fp Check Point (ECT_MOD_CHECK_POINT) Function......................601

11.1.6.4.22 ECT Fp Check Point, R2 (ECT_MOD_CHECK_POINT_R2) Function.........602

11.1.6.4.23 Copy memory, N-Size and Source-Size (COPY_NSZ and COPY_SSZ)........ 603

11.1.6.4.24 Right Shift A (R_SHIFT) function................................................................... 604

11.1.6.4.25 Compare A B (COMPARE) function...............................................................604

11.1.6.4.26 Evaluate A (EVALUATE) function................................................................. 605

11.1.6.5 Special values for common ECC domains.............................................................................606

11.2 Kasumi f8 and f9 hardware accelerator(KFHA) functionality................................................................................... 625

11.2.1 KFHA use of the Mode Register................................................................................................................625

11.2.2 KFHA use of the Context Register............................................................................................................ 626

11.2.3 KFHA use of the Key Register.................................................................................................................. 627

11.2.4 KFHA use of the Data Size Register......................................................................................................... 627

11.2.5 KFHA error conditions.............................................................................................................................. 627

11.3 Data encryption standard accelerator (DES) functionality......................................................................................... 628

11.3.1 DESA use of the Mode Register................................................................................................................628

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11.3.2 DESA use of the Key Register...................................................................................................................629

11.3.3 DESA use of the Key Size Register...........................................................................................................629

11.3.4 DESA use of the Data Size Register..........................................................................................................629

11.3.5 DESA Context Register............................................................................................................................. 630

11.3.6 Save and store operations in DESA context data.......................................................................................630

11.4 Cyclic-redundancy check accelerator (CRCA) functionality..................................................................................... 630

11.4.1 CRCA modes of operation.........................................................................................................................631

11.4.2 CRCA use of the Mode Register................................................................................................................631

11.4.3 CRCA Key Register...................................................................................................................................633

11.4.4 CRCA Key Size Register...........................................................................................................................633

11.4.5 CRCA Data Size Register..........................................................................................................................633

11.4.6 CRCA Context Register.............................................................................................................................633

11.4.7 Save and restore operations in CRCA context data................................................................................... 634

11.5 Random-number generator (RNG) functionality........................................................................................................634

11.5.1 RNG features summary..............................................................................................................................634

11.5.2 RNG functional description ...................................................................................................................... 635

11.5.2.1 RNG state handles..................................................................................................................635

11.5.2.2 RNG NIST certification.........................................................................................................635

11.5.3 RNG operations..........................................................................................................................................637

11.5.4 RNG use of the Key Registers................................................................................................................... 638

11.5.5 RNG use of the Context Register...............................................................................................................638

11.5.6 RNG use of the Data Size Register............................................................................................................639

11.6 SNOW 3G f8 accelerator functionality.......................................................................................................................639

11.6.1 Differences between SNOW 3G f8 and SNOW 3G f9..............................................................................639

11.6.2 SNOW 3G f8 use of the Mode Register.................................................................................................... 640

11.6.3 SNOW 3G f8 use of the Context Register................................................................................................. 641

11.6.4 SNOW 3G f8 use of the Data Size Register.............................................................................................. 641

11.6.5 SNOW 3G f8 use of the Key Register....................................................................................................... 642

11.6.6 SNOW 3G f8 use of the Key Size Register............................................................................................... 642

LS2088A Security (SEC) Reference Manual, Rev. 0, 04/2018

20 NXP Semiconductors

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