ZiLOG Z8523L User manual

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UM010904-0318

User Manual

SCC/ESCC

User Manual

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DO NOT USE IN LIFE SUPPORT

LIFE SUPPORT POLICY

ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE

SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF

THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

As used herein

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)

support or sustain life and whose failure to perform when properly used in accordance with instructions for

use provided in the labeling can be reasonably expected to result in a significant injury to the user. A

critical component is any component in a life support device or system whose failure to perform can be

reasonably expected to cause the failure of the life support device or system or to affect its safety or

effectiveness.

Document Disclaimer

applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,

INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY

OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.

ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY

INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR

TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this

document has been verified according to the general principles of electrical and mechanical engineering.

Z8, Z80 are registered trademarks of Zilog, Inc. All other product or service names are the property of their

respective owners.

Warning:

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Revision History

Each instance in Revision History reflects a change to this document from its previous

revision. For more details, refer to the corresponding pages and appropriate links in the

table below.

Date

Revision

Level Description Page No

March 2018 04 Added missing images 212, 213, 217,

218, 220, 222,

227, 230, 234,

236, 244

May 2015 03 Updated /SYNCA and /SYNCB

Updated /RTxCA, /RTxCB

Updated Data Encoding Method Figure

14

15

75

June 2009 02 Added Low Voltage ESCC information All

May 2009 01 Original Document All

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Table of Contents

General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SCC’s Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Descriptions 9

Pins Common to both Z85X30 and Z80X30. . . . . . . . . . . . . . . . . . . . . . . 13

Pin Descriptions, (Z85X30 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Pin Descriptions, (Z80X30 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Interfacing the SCC/ESCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Z80X30 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Z80X30 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Z80X30 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Z80X30 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . 19

Z80X30 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Z80C30 Register Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Z80230 Register Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Z80X30 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Z85X30 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Z85X30 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Z85X30 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Z85X30 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . 29

Z85X30 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Z85C30 Register Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Z85C30/Z85230/L Register Enhancements . . . . . . . . . . . . . . . . . . . . . . 32

Z85X30 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Interface Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

I/O Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Daisy-Chain Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

The Receiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Transmit Interrupts and Transmit Buffer Empty Bit . . . . . . . . . . . . . . . . . 49

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External/Status Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Block/DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Block Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Auto Echo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

SCC/ESCC Ancillary Support Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Data Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DPLL Digital Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

DPLL Operation in the NRZI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

DPLL Operation in the FM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

DPLL Operation in the Manchester Mode . . . . . . . . . . . . . . . . . . . . . . . . 82

Transmit Clock Counter (ESCC only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Data Communication Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Transmit Data Path Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Receive Data Path Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Asynchronous Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Asynchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Asynchronous Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Byte-Oriented Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Byte-Oriented Synchronous Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Byte-Oriented Synchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Transmitter/Receiver Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Bit-oriented Synchronous (SDLC/HDLC) Mode . . . . . . . . . . . . . . . . . . . . . 113

SDLC Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

SDLC Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

SDLC Frame Status FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

SDLC Loop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Write Register 0 (Command Register) . . . . . . . . . . . . . . . . . . . . . . . . . 139

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Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode

Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Write Register 2 (Interrupt Vector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Write Register 3 (Receive Parameters and Control) . . . . . . . . . . . . . . . 148

Write Register 4 (Transmit/Receive Miscellaneous Parameters 

and Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Write Register 5 (Transmit Parameters and Controls) . . . . . . . . . . . . . 152

Write Register 6 (Sync Characters or SDLC Address Field) 154

Write Register 7 (Sync Character or SDLC Flag) . . . . . . . . . . . . . . . . . 155

Write Register 7 Prime (ESCC only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Write Register 7 Prime (85C30 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Write Register 8 (Transmit Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Write Register 9 (Master Interrupt Control) . . . . . . . . . . . . . . . . . . . . . . 159

Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) . . 162

Write Register 11 (Clock Mode Control) . . . . . . . . . . . . . . . . . . . . . . . . 165

Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) 167

Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) 169

Write Register 14 (Miscellaneous Control Bits) . . . . . . . . . . . . . . . . . . . 169

Write Register 15 (External/Status Interrupt Control) . . . . . . . . . . . . . . 172

Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Read Register 0 (Transmit/Receive Buffer Status and External Status) 174

Read Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Read Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Read Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Read Register 4 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . . 182

Read Register 5 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . . 182

Read Register 6 (Not on NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Read Register 7 (Not on NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Read Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Read Register 9 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . . 184

Read Register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Read Register 11 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . 186

Read Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Read Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Read Register 14 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . 187

Read Register 15 187

Application Notes188

Interfacing Z80® CPUs to the Z8500 Peripheral Family . . . . . . . . . . . . . . . 188

AN0096: The Z180 Interfaced with the SCC at 10 MHz . . . . . . . . . . . . . . . 210

AN0097: The Zilog® Datacom Family with the 80186 CPU. . . . . . . . . . . . . 250

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SCC in Binary Synchronous Communications . . . . . . . . . . . . . . . . . . . . . . 275

Serial Communication Controller (SCC): SDLC Mode of Operation . . . . . . 288

Using SCC with Z8000 in SDLC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 300

AN0300: Boost Your System Performance Using the Zilog ESCC 

Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

AN006: Technical Considerations When Implementing Localtalk Link Access

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

AN0075: On-Chip Oscillator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Interfacing the ISCC to the 68000 and 8086 . . . . . . . . . . . . . . . . . . . . . . . . 353

Zilog SCC Z8030/Z8530 Questions and Answers . . . . . . . . . . . . . . . . . . . . 363

Zilog ESCC Controller Questions and Answers . . . . . . . . . . . . . . . . . . . . . 373

Questions and Answers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

Zilog SCC Z8030/Z8530 Questions and Answers . . . . . . . . . . . . . . . . . . . . 375

Zilog ESCC Controller Questions and Answers . . . . . . . . . . . . . . . . . . . . . 385

Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

SCC/ESCC

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UM010904-0318 General Description

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General Description

Introduction

Zilog’s SCC Serial Communication Controller is a dual channel, multiprotocol data communica-

tion peripheral designed for use with 8- and 16-bit microprocessors. The SCC functions as a serial-

to-parallel, parallel-to-serial converter/controller. The SCC can be software-configured to satisfy a

wide variety of serial communications applications. The device contains a variety of new, sophis-

ticated internal functions including on-chip baud rate generators, digital phase-lock loops, and

crystal oscillators, which dramatically reduce the need for external logic.

The SCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM

Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile

device supports virtually any serial data transfer application (telecommunication, LAN, etc.).

The device can generate and check CRC codes in any synchronous mode and can be programmed

to check data integrity in various modes. The SCC also has facilities for modem control in both

channels. In applications where these controls are not needed, the modem controls can be used for

general-purpose I/O.

With access to 14 Write registers and 7 Read registers per channel (the number of the registers var-

ies depending on the version), the user can configure the SCC to handle all synchronous formats

regardless of data size, number of stop bits, or parity requirements.

Within each operating mode, the SCC also allows for protocol variations by checking odd or even

parity bits, character insertion or deletion, CRC generation, checking break and abort generation

and detection, and many other protocol-dependent features.

The SCC/ESCC family consists of the following eight devices;

As a convention, use the following words to distinguish the devices throughout this document.

SCC: Description applies to all versions.

Z-Bus Universal-Bus

NMOS Z8030 Z8530

CMOS Z80C30 Z85C30

ESCC Z80230 Z85230/Z8523L

EMSCC Z85233

Low Voltage ESCC Z8523L

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NMOS: Description applies to NMOS version (Z8030/Z8530)

CMOS: Description applies to CMOS version (Z80C30/Z85C30)

ESCC: Description applies to ESCC (Z80230/Z85230/Z8523L)

EMSCC: Description applies to EMSCC (Z85233)

Z80X30: Description applies to Z-Bus version of the device (Z8030/Z80C30/Z80230)

Z85X3X: Description applies to Universal version of the device (Z8530/Z85C30/Z85230/

Z8523L/Z85233)

The Z-Bus version has a multiplexed bus interface and is directly compatible with the Z8000,

Z16C00, and 80x86 CPUs. The Universal version has a non-multiplexed bus interface and easily

interfaces with virtually any CPU, including the 8080, Z80

®

, 68X00.

SCC’s Capabilities

The NMOS version of the SCC is Zilog’s original device. The design is based on the Z80 SIO

architecture. If you are familiar with the Z80 SIO, the SCC can be treated as an SIO with support

circuitry such as DPLL, BRG, etc. Its features include:

•

Two independent full-duplex channels

•

Synchronous/Isosynchronous data rates:

– Up to 1/4 of the PCLK using external clock source

– Up to 5 Mbits/sec at 20 MHz PCLK (ESCC)

– Up to 4 Mbits/sec at 16 MHz PCLK (CMOS)

– Up to 2 Mbits/sec at 8 MHz PCLK (NMOS)

– Up to 1/8 of the PCLK (up to 1/16 on NMOS) using FM encoding with DPLL

– Up to 1/16 of the PCLK (up to 1/32 on NMOS) using NRZI encoding with DPLL

•

Asynchronous Capabilities

– 5, 6, 7 or 8 bits/character (capable of handling 4 bits/character or less.)

– 1, 1.5, or 2 stop bits

– Odd or even parity

– Times 1, 16, 32 or 64 clock modes

– Break generation and detection

– Parity, overrun and framing error detection

•

Byte oriented synchronous capabilities:

– Internal or external character synchronization

– One or two sync characters (6 or 8 bits/sync character) in separate registers

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– Automatic Cyclic Redundancy Check (CRC) generation/detection

•

SDLC/HDLC capabilities:

– Abort sequence generation and checking

– Automatic zero insertion and detection

– Automatic flag insertion between messages

– Address field recognition

– I-field residue handling

– CRC generation/detection

– SDLC loop mode with EOP recognition/loop entry and exit

•

Receiver FIFO

ESCC: 8 bytes deep

NMOS/CMOS: 3 bytes deep

•

Transmitter FIFO

ESCC: 4 bytes deep

NMOS/CMOS: 1 byte deep

•

NRZ, NRZI or FM encoding/decoding. Manchester code decoding (encoding with exter-

nal logic)

•

Baud Rate Generator in each channel

•

Digital Phase Locked Loop (DPLL) for clock recovery

•

Crystal oscillator

The CMOS version of the SCC is 100% plug in compatible to the NMOS versions of the device,

while providing the following additional features:

•

Status FIFO

•

Software interrupt acknowledge feature

•

Enhanced timing specifications

•

Faster system clock speed

•

Designed in Zilog’s Superintegration™ core format

•

When the DPLL clock source is external, it can be up to 2x the PCLK, where NMOS

allows up to PCLK (32.3 MHz max with 16/20 MHz version).

The Z85C30 CMOS SCC has added new features, while maintaining 100% hardware/software

compatibility. It has the following new features:

•

New programmable WR7' (write register 7 prime) to enable new features.

•

Improvements to support SDLC mode of synchronous communication:

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– Improved functionality to ease sending back-to back frames

– Automatic SDLC opening Flag transmission*

– Automatic Tx Underrun/EOM Latch reset in SDLC mode*

– Automatic /RTS deactivation*

– TxD pin forced “H” in SDLC NRZI mode after closing flag*

– Complete CRC reception*

– Improved response to Abort sequence in status FIFO

– Automatic Tx CRC generator preset/reset

– Extended read for write registers*

– Write data setup timing improvement

•

Improved AC timing:

– Three to 3.5 PCLK access recovery time.

– Programmable /DTR//REQ timing*

– Elimination of write data to falling edge of /WR setup time requirement

– Reduced /INT timing

•

Other features include:

– Extended read function to read back the written value to the write registers*

– Latching RR0 during read

– RR0, bit D7 and RR10, bit D6 now has reset default value

Some of the features listed above are available by default, and some of them (features with “*”)

are disabled on default.

ESCC (Enhanced SCC) is pin and software compatible to the CMOS version, with the following

additional enhancements.

•

Deeper transmit FIFO (4 bytes)

•

Deeper receive FIFO (8 bytes)

•

Programmable FIFO interrupt and DMA request level

•

Seven enhancements to improve SDLC link layer supports:

– Automatic transmission of the opening flag

– Automatic reset of Tx Underrun/EOM latch

– Deactivation of /RTS pin after closing flag

– Automatic CRC generator preset

– Complete CRC reception

– TxD pin automatically forced high with NRZI encoding when using mark idle

– Status FIFO handles better frames with an ABORT

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5

– Receive FIFO automatically unlocked for special receive interrupts when using

the SDLC status FIFO

•

Delayed bus latching for easier microprocessor interface

•

New programmable features added with Write Register 7' (WR seven prime)

•

Write registers 3, 4, 5 and 10 are now readable

•

Read register 0 latched during access

•

DPLL counter output available as jitter-free transmitter clock source

•

Enhanced /DTR, /RTS deactivation timing

Block Diagram

Figure on page 6 displays the block diagram of the SCC. Note that the depth of the FIFO differs

depending on the version. The 10X19 SDLC Frame Status FIFO is not available on the NMOS

version of the SCC. Detailed internal signal path will be discussed in Data Communication Modes

on page 88.

SCC/ESCC

User Manual

UM010904-0318 General Description

6

SCC Block Diagram

Transmit Lo

g

Channel

A

Receive and Transmit Clock Mul

Transmit FIFO

NMOS/CMOS: 1 b

ESCC: 4 Bytes

Transmit M

U

Data Encoding & C

R

Generation

Digital

Phase-Lock

e

Loop

Baud Rat

Generat

o

Crystal

Oscillat

o

Amplifi

e

Modem/Control L

o

Receive M

U

CRC Checke

Data Decode

&

Sync Charac

t

Detection

Rec. Status

*

FIFO

Rec. Data*

FIFO

SDLC Frame Status F

10 x 19

Receive Lo

g

TxD

A

/TRxC

A

/RTxC

A

/CTS

A

/DCD

A

/SYNC

A

/RTS

A

/DTRA//RE

Q

RxD

A

Intern

a

Contro

Logic

Channel

A

Register

Channel

B

Register

Interru

p

Control

Logic

CPU & DM

A

Bus Interfa

c

Databu

Contr

o

Channel

A

Channel

B

/IN

/INTA

C

IE

O

Interr

u

Contr

o

Exploded Vi

e

** See N

o

* NMOS/CMOS: 3 bytes each

ESCC: 8 bytes

** Not Available on NMOS

SCC/ESCC

User Manual

UM010904-0318 General Description

7

Pin Descriptions

The SCC pins are divided into seven functional groups: Address/Data, Bus Timing and Reset,

Device Control, Interrupt, Serial Data (both channels), Peripheral Control (both channels), and

Clocks (both channels). Figure on page 8 and Figure on page 9 display the pins in each functional

group for both Z80X30 and Z85X30. Notice the pin functions unique to each bus interface version

in the Address/Data group, Bus Timing and Reset group, and Control groups.

The Address/Data group consists of the bidirectional lines used to transfer data between the CPU

and the SCC (Addresses in the Z80X30 are latched by /AS). The direction of these lines depends

on whether the operation is a Read or Write.

The timing and control groups designate the type of transaction to occur and when it will occur.

The interrupt group provides inputs and outputs to conform to the Z-Bus

®

specifications for han-

dling and prioritizing interrupts. The remaining groups are divided into channel A and channel B

groups for serial data (transmit or receive), peripheral control (such as DMA or modem), and the

input and output lines for the receive and transmit clocks.

SCC/ESCC

User Manual

UM010904-0318 General Description

8

The signal functionality and pin assignments (Figure on page 10 through Figure on page 13) stay

constant within the same bus interface group (i.e., Z80X30, Z85X30), except for some timing and/

or DC specification differences. For details, refer the individual product specifications.

Z85X30 Pin Functions

D7

D6

D5

D4

D3

D2

D1

D0

/RD

/WR

A//B

/CE

D//C

/INT

/INTACK

IEI

IEO

TxDA

RxDA

/TRxCA

/RTxCA

/SYNCA

/W//REQ

A

/DTR//REQA

/RTS

A

/CTS

A

/DCDA

TxDB

RxDB

/TRxCB

/RTxCB

/SYNCB

Serial

Data

Channel

Clocks

Channel

Controls

for Modem,

DMA and

Other

/W//REQB

/DTR//REQ

B

/RTS

B

/CTS

B

/DCDB

Interrup

t

Data Bus

Serial

Data

Channel

Clocks

Control

Bus Timing

and Reset

Channel

Controls

for Modem,

DMA and

Other

Z85X30

SCC/ESCC

User Manual

UM010904-0318 General Description

9

Pin Descriptions

Z80x30 Pin Functions

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

/AS

/DS

R//W

CS1

/CS0

/INT

/INTACK

IEI

IEO

TxDA

RxDA

/TRxCA

/RTxCA

/SYNCA

/W//REQA

/DTR//REQA

/RTSA

/CTSA

/DCDA

TxDB

RxDB

/TRxCB

/RTxCB

/SYNCB

Serial

Data

Channel

Clocks

Channel

Controls

for Modem,

DMA and

Other

/W//REQB

/DTR//REQB

/RTSB

/CTSB

/DCDB

Interrupt

Address

Data Bus

Serial

Data

Channel

Clocks

Control

Bus Timing

and Reset

Channel

Controls

for Modem,

DMA and

Other

Z80X30

Channel A

Channel B

SCC/ESCC

User Manual

UM010904-0318 General Description

10

Z85X30 DIP Pin Assignments

1

2

9

3

4

5

6

7

8

4

0

39

3

8

3

7

3

6

35

3

4

3

32

D0

D2

D//C

D4

D6

/RD

/WR

A//B

/CE

D1

31

3

0

29

2

8

2

7

14

10

11

12

13

GND

/W//REQB

/SYNCB

/RTxCB

RxDB

D3

D5

D7

/INT

IEO

IEI

/INTACK

VCC

/W//REQA

/SYNCA

/RTxCA

RxDA

/TRxCA

TxDA

/DTR//REQA

/RTSA

/CTSA

/DCDA

PCL

K

15

16

17

18

19

20

/TRxCB

TxDB

/DTR//REQB

RTSB

/CTSB

/DCDB

2

6

25

2

4

2

3

22

21

Z85X30

SCC/ESCC

User Manual

UM010904-0318 General Description

11

Z85X30 PLCC Pin Assignments

SCC/ESCC

User Manual

UM010904-0318 General Description

12

Z80X30 DIP Pin Assignments

1

2

9

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

AD0

AD2

CS1

AD4

AD6

/DS

/AS

R//W

/CS0

AD1

31

30

29

28

27

14

10

11

12

13

GND

/W//REQB

/SYNCB

/RTxCB

RxDB

AD3

AD5

AD7

/INT

IEO

IEI

/INTACK

VCC

/W//REQA

/SYNCA

/RTxCA

RxDA

/TRxCA

TxDA

/DTR//REQA

/RTSA

/CTSA

/DCDA

PCL

K

15

16

17

18

19

20

/TRxCB

TxDB

/DTR//REQB

RTSB

/CTSB

/DCDB

26

25

24

23

22

21

Z80X30

SCC/ESCC

User Manual

UM010904-0318 General Description

13

Z80X30 PLCC Pin Assignments

Pins Common to both Z85X30 and Z80X30

/CTSA, /CTSB. Clear To Send (inputs, active Low). These pins function as transmitter enables if

they are programmed for Auto Enable (WR3, D5=1). A Low on the inputs enables the respective

transmitters. If not programmed as Auto Enable, they may be used as general-purpose inputs. Both

inputs are Schmitt-trigger buffered to accommodate slow rise-time inputs. The SCC detects pulses

on these inputs and can interrupt the CPU on both logic level transitions.

/DCDA, /DCDB. Data Carrier Detect (inputs, active Low). These pins function as receiver

enables if they are programmed for Auto Enable (WR3, D5=1); otherwise, they are used as gen-

eral-purpose input pins. Both pins are Schmitt-trigger buffered to accommodate slow rise time sig-

nals. The SCC detects pulses on these pins and can interrupt the CPU on both logic level

transitions.

/RTSA, /RTSB. Request To Send (outputs, active Low). The /RTS pins can be used as general-

purpose outputs or with the Auto Enable feature. When used with Auto Enable ON (WR3, D5=1)

in asynchronous mode, the /RTS pin goes High after the transmitter is empty. When Auto Enable

1

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