KEN WOO
D
T
S-440SPS-430SP-4a
0
SPECIFICATIONS
2
HF TRANSCEIVE
R
CONTENT
S
CIRCUIT DESCRIPTION
4
SEMICONDUCTORS
27
PARTS LIST
3
5
PC BOARD SCHEMATIC DIAGRA
M
SWITCH UNIT
6
9
FILTER UNIT
70, 7
1
PLL UNIT
72, 7
3
RF UNIT
74, 7
5
CONTROL UNIT
76, 7
7
DISPLAY UNIT
76, 7
7
FINAL UNIT
78
IF UNIT
78, 7
9
AT UNIT
80
DISASSEMBLY
81
PACKING
8 8
ADJUSTMENT
8
9
LEVEL DIAGRAM
10
1
BLOCK DIAGRAM
10
3
OPTIO
N
PS-50
104
PS-430
109
VS-1
1 1
1
SP-430
11
4
MB-430
11
4
AT-440
11
4
YK-88S /S N
11
4
YK-88C/CN
11
4
SCHEMATIC DIAGRAM
113
TS-440
S
(GENERAL
)
Transmitter frequency range
:
Receive frequency range
:
Mode
:
Antenna impedance
:
Power requirement
:
Power consumption
:
RX no signal input
:
TX
:
Frequency configuration
:
RX unit
:
TX unit
: (A1,A3J,A3,FSK
)
(F3
)
Semiconductors
:
SPECIFICATION
S
160m BAND
1
.8 —
2
.0MH
z
80m BAND
3
.5 —
4
.0MH
z
40m BAND
7
.0 —
7
.3MH
z
30m BAND
10
.1
—
10
.15MH
z
20m BAND
14
.0
--
14
.35MH
z
17m BAND
18
.068 — 18
.168MH
z
15m BAND
21
.0 — 21.45MH
z
12m BAND
24
.89 — 24
.99MH
z
10m BAND
28
.0 — 29
.7MHz
100kHz — 30MH
z
Al (CW), A3J(SSB), A3(AM), F1 (FSK), F3(FM
)
50 Ohm (TX
: 20— 150 Ohm with AT
)
12
.0--
16
.0V D
C
Approx
. 1
.9
A
Approx
. 20
A
1st IF 45
.05MHz, 2nd IF 8.83MHz, 3rd IF 455kH
z
1st IF 455kHz, 2nd IF 8
.83MHz, 3rd IF 45
.05MH
z
1st IF 36
.22MHz, 2nd IF 45
.05MH
z
CW, SSB, AM, FSK, FM
: Triple conversion superheterodyn
e
FM
: Double conversion superheterodyne
TS-440S
TS-440S (with AT
)
Tr's
1 57
1 7
4
FET's
22
2 2
IC's
49
5 8
Diod's
257
27
7
(
TS-440S TS-440S
with AT
)
W(mm)
270 (279)
270 (279
)
H(mm)
96 (108)
96 (108
)
D(mm)
313 (335)
313 (335
)
Weight(kg)
6
.3
7
.
3
Dimensions
:
(
The numbers in the parenthesis include protections
.
(TRANSMITTER
)
Ratead final power input
:
Carrier supression
:
Unwanted sidebande supression
:
Harmonic content
:
Transmit frequency character
:
Maximum frequency diviation (FM)
:
Microphone impedance
:
More than 40d
B
More than 50d
B
Less than
-40d
B
400--2600Hz (—6dB
)
±5k H
z
50052 - 50k
g
2
TS-440
S
SPECIFICATION
S
(RECEIVER
)
Sensitivity
:
Freq
.
Mode
100 -- 150kHz
150
500kHz
0
.5 --
1
.6MHz
1
.6 -- 30MH
z
SSB,CW,FS
K
(SIN10dB)
Less tha
n
2
.5µV
(8dBA1
Less tha
n
1µV (OdB
A
)
Less tha
n
4µV (12dBA)
Less tha
n
0
.25µV (— 12dB
A
)
AM (SIN 10dB)
Less tha
n
25µV
(28dBp)
Less tha
n
13µV (22dB
A
)
Less tha
n
40/,cV
(32dBA)
Less tha
n
2
.5µV
(8dBA
)
FM (12dB SINAD)
Less tha
n
0
.7µV (—3 dBµ
)
Squelch
sensitivity
: (Threshold
)
Mode
•
•
150 -- 500kHz
0
.5 —
1
.6MHz
1
.6 - - 30MH
z
SSB,CW,AM,FSK
Less tha
n
20AV (26dBA1
Less tha
n
10
A
V (20dBp)
Less tha
n
20µV
(26dBA)
Less tha
n
2µV (6dBA
)
FM
Less tha
n
0 32
A
V (— 10d B
A
)
Image ratio
:
IF rejection
:
Selectivity
:
IF SHIFT variable range
:
RIT/XIT variable range
:
Audio output power
:
Audio output impedanc
e
(FREQUENCY STABILITY
)
Frequency accuracy
: (RIT/XIT OFF
)
Frequency stability
:
(RIT/XIT OFF
: at receive
)
Reference oscillator frequency
:
50dB or more (1 00kHz -- 1 6MHz
)
70dB or more (1
.6 — 30MHz
)
50dB or more (FM 3rd image ratio
)
50dB or more (100kHz --- 1 6MHz
)
70dB or more (1
.6MHz -- 30MHz
)
Fre
d
Mode
— 6dB — 60d
B
SB,CW,FSK
More than 2kHz Less than 4
.4kH
z
AM
More than 4kHz
Less than 18kHz (— 50dB
)
FM
More than 1 2kHz Less than 25kHz (— 50dB)
±0
.9kHz or mor
e
± 1 kHz or mor
e
1
.5W or more (with 8S2 load, 10% distortion
)
4 — 1652 (Speaker and headphone
)
More than
±10
x 1
0
-
6
More than
±10
x 10
-6
(— 10°C to 50°C
)
36MH
z
Note
:
Circuit and ratings subject to change without notice due to developments in technology
.
3
TS-440S
CIRCUIT DESCRIPTIO
N
1
. Overview
•
The TS-440 is a triple conversion type transceiver, incor-
porating a general coverage receiver, which uses 45
.0
5
MHz as the first IF, 8
.83 MHz as the second IF, and 45
5
kHz as the third IF
.
•
The TS-440 is compact, but allows for installation of a
n
optional internal automatic antenna tuner operating in th
e
amateur band from 3
.5 MHz to 28 MHz and enables
a
wide range of antennas to be used
.
•
The TS-440 also contains a microprocessor-controlled dig-
ital PLL circuit which controls frequency in 10 Hz step
s
using a single crystal oscillator to implement high accura
-
cy and stable frequency control
.
•
The TS-440 has the following major features
:
(1)
Selectable VFOs
; VFO-A and VFO-
B
(2)
Direct frequency input using a numeric keypa
d
(3)
100-channel memory containing frequency band
,
and mode information (channel 90 to 99 for split fre
-
quency memory
)
(4)
Memory scan in 10 channel groups and two type
s
of program sca
n
(5)
RTTY (AFSK) mode availabl
e
(6)
Squelch circuit operational in all mode
s
(7)
Dual filters available to improve selectivity and SI
N
ratio (optional filter required
)
(8)
IF shift, audio notch, IF filter switching, and RF AT
T
functions for convenient interference reductio
n
(9)
Large heat sink and cooling fan (100 W) enabling u
p
to one-hour continious transmit operatio
n
(101 Full and semi break-in circuits for C
W
(1 1) External-computer controllable (optional interface re
-
quired
)
(12) Many easy-to-read meter functions such as th
e
received signal strength (s-meter), transmitter power
,
SWR, and ALC level
.
2
. Frequency Element
s
The TS-440 utilizes a triple conversion transmitter an
d
receiver
.
V
30K
f IN
RX MIX
1
30MHz ,
RX
TX
45
.05MHz RX MIX2
8
.83MHz
RX MIX3
455KHz
DE
T
DISCR I
RX OUTPU
T
TX MIX3
TX MIX
I
8
.83MH
z
TX MIX
2
SSB,CWT, AM,
FM, FSK
(FM MOD
)
:45
.O8^-75
.05MH
z
-CW R
:45
.0792-- 75
.0492 MHz
SS B
C
W
FS
K
'
AMR,FM
R
AMT,FMT
: 455KH
z
USB,
CW
:
456
.5
KH
z
-LSB,FSK
453
.5KH
z
FSK
AFS INPU
T
B
.M
.
SS
B
AM
MIC INPU
T
F
M
Fig
. 1
Frequency configuratio
n
The overall frequency configuration of the TS-440 is show
n
in Figure 1
. The incoming received signal (f,
N
l
is applied t
o
the ANT terminal
. This signal is mixed with the local oscilla-
tor signal (fvco) in RX MIX 1 to obtain the first IF frequen-
cy
. This signal is then mixed with the HET Oscillator signa
l
(fHET) in RX MIX 2, to obtain the 2nd IF frequency
. Th
e
resulting signal is then mixed with the second local oscilla
-
tor frequency (f
L
o) to obtain the 3rd IF frequency
. The sig-
nal is then combined with the CAR signal for detection
. f
i
N
is expressed mathematically as follows
:
fiN = fvco
fHEr – fLo
fcAlt
1
4
TS-440
S
CIRCUIT DESCRIPTIO
N
ANT
Fig
. 2 PLL frequency configuratio
n
30
K
30MHz
1st MIX
MIX
3rd MI
X
2nd
D
AF OU
T
DE
T
/
\
I
5 KHZ
I
6
.22MHZ
P
D
120KHZI
1= 1800 1=450
1
J=72441=1811
1
FM
MOD
I
/
1
I
HI
IPLL 5
1
I I F
M
MIX 5
4
.55MH
AMR,FM
R
AMT, FMT
: 455 KH
z
USB, CW
: 456
.
5
LSB,
FSK
: 453
.
5
CA
R
1/1
0
IX 4
9
.9—10 4MH
1/2
0
1/
5
IPLL
31
I/1
0
MKR —
(=13720_
.20719)
1 1
RIT, XI
T
Y
I/L
11/180
0
L=19800
`_
MN614
7
20799
4
P
.D
99=104MH
z
(98_6 =103
.6MHZ
)
—
5KHZ
—
I
M=323
9
299 4
STEP 5
)Cw
R
1
/P
o
r
I
/P-
I
F
P
I/1
---
-
7006 J
58
.25-
u
53
.25MHz
BP
F
r
1
I
p,D
I/
M
}
20KH
Z
1/450
AM,FM
: 91 MH
z
USB,CW
: 91
.3 MH
z
LSB,FSK
: 90
.7MH
z
IPLL4I
I
AM,FM
: K=1820
0
USB,
CW
K=1826
0
LSB,FSK
K=1814
0
IPLL
11
D
I/N,I/A--L
1
8
SOOKHZ
INT=13-
.73
T _ MN614
7
NT=PN-A
L—
—
I
91 MH
z
/'
—
1
I
.98^-2
.08MH
z
64
.78
=
59
.88MHz
P
.D
5KH
z
I/K
1/180
0
—
As shown in figure 2, all received frequencies excluding th
e
local oscillator frequency fLo are generated in the PLL circuit
.
The frequencies generated in these loops are expressed a
s
follows
:
-
fsT
D
VC04
:
f
K04
4
800 •
. fvco4 = 7200 fSTD
. . .
3
.fsTD
L
VCO3
: fvLos =
4
800
fvcos = 7200 fSTD
. . . .
4
fvcoz + fvco3 + fvco4
1
'fsT
D
50
20
4
M
45 0
M
fsTD
fvco
_ s
fvco4
5
fvcoz = 1800
50
2
0
VC01
:
N
1
8
:
.
fvcos = 72 fSTD + fLo +
f
STD
f
1
002
. .
6
Based on these formulas, the frequencies fvcor fHET,
and
fCA
R
are expressed as follows
:
/
N
M
L
fvco
= fvcor =
(
72
1800 + 3600000
K
+ 1440000 + 1) fsTD + fLo
7
J
f
HET = fVCO5 = 41
fSTD
8
Formula 1 may now be rewritten as follows
:
N _
M
L
J
fIN 1
72
180000 + 3600000
41 +
1
)
.
fsT
D
1
0
Note that f
L
o
is
not included in formula 10
. That is,
a
received frequency is determined by the reference frequen-
cy fs
TD
and frequency division data
Ito
N
. Further analysi
s
of formula
10 shows the following
:
i)
Basically, frequency division data I to N contain no er-
ror because they are controlled by the microproces-
sor according to the operating frequency
.
ii)
The accuracy of the operating frequency is equal t
o
that of the reference frequency, because all frequen-
cies other than fs
TD
in formula 10 are determine
d
by the microprocessor
.
iii)
The operating frequency does not change even if k o
r
fLo changes
.
When f
IN
= 14 MHz (USB mode) in formula 10 , f
IN
an
d
f
STD have the following relationship
:
VCO5
:
fvcos
4 fsTD
fvcos =
J
I
4
1
fSTD
2
VCO2
:
fvcos — f
L
o — fSTD + fvcoz
1
f
10
4
sTD
fvco4
K
fcAR
200
1440000
fSTD
9
5
TS-440S
CIRCUIT DESCRIPTIO
N
I=1800, J=7244, K=19800, L=3239, M=4
1
fin = 0
.388 fsTD
1 1
When fIN = 30 MHz (USB mode) in formula 10 , f
IN
an
d
fSTD have the following relationship
:
I = 1800, J = 7244, K = 19800, L = 3239, M = 7
3
.'
. fIN = 0
.833
f
STD
1
2
Since the precision of the reference crystal oscillator use
d
in the TS-440 is 10 ppm (—10 to 50°C) and the receive
r
system has the characteristics shown in items i) and ii), th
e
total accuracy is stable at any point from 30 kHz to 30 MHz
.
The maximum amount of frequency shift is only +/— 30
0
Hz (see formula 12 )
. The characteristic shown in ite
m
iii) enables variable band functions such as IF shift to be im
-
plemented, using the microprocessor. The microprocesso
r
also is used to set carrier points by adjusting fcAR, and to se
t
and adjust the amount of IF shift
.
So far received frequencies in the SSB mode have been dis
-
cussed
. For receive modes other than SSB, and in transmi
t
mode, operating frequency is determined by the referenc
e
frequency and frequency division data
.
In CW receive mode,
fvco
is shifted down 800 Hz and use
d
as
fvco3
.
In AM or FM receive mode, fCAR generation i
s
stopped
. In FM receive mode, f
HET
is modulated by addin
g
audio signals to VCO5 from the microphone
. FSK (RTTY) i
s
transmitted in LSB mode and uses AFSK by adding audio sig
-
nals externally
.
The type of frequency displayed differs, depending on th
e
mode, as shown in Table 1
.
Mode
Displayed frequenc
y
USB, LSB, FS
K
C
W
AM, FM
Carrier point frequenc
y
Transmission carrier frequenc
y
IF filter center frequency
Table 1 Displayed frequencie
s
3
.
Receiver Circuit Descriptio
n
IC
2
C335
7
f
I F AMP
.
DE
T
Noise
S
O
CF
3
CFW455
Fig
. 3 Receiver circuit configuratio
n
CF I
Q7,
8
3SK73GRx2
IC
7
µPC2002V
S P
SSB
C
.F
AF P
A
CF
2
C
.
F
6
TS-440
S
CIRCUIT DESCRIPTIO
N
t
Signals from the ANT pin are fed into the RAT pin of the R
F
unit via the transmit/receive switching relay
. The signals the
n
go to the 10 BPFs through the approx
. 20 dB attenuator cir
-
cuit, the first stage of the first IF trap circuit, and the lo
w
pass filters (which pass only 500 kHz or less)
. The signal the
n
goes through the second stage of the first IF trap circuit, an
d
is mixed with the VCO signal and converted into the first I
F
signal of 45
.05 MHz in the first mixer, consisting of Q3 an
d
Q4 (2SK125-5)
. The VCO circuit consists of Q21 to Q2
4
(2SC2668Y) and oscillates in four bands from 45
.05 MH
z
to 75
.05 MHz
. Oscillator frequencies are controlled by D
C
signals from the PLL unit
.
The first IF signal of 45
.05 MHz is passed through the MC
F
(F1), which is used in both receive and transmit, and is am
-
plified by the first IF amplifier Q5 (3SK74L)
. In the secon
d
mixer, consisting of Q6 and Q7 (2SK1 25), the first IF signa
l
is mixed with the heterodyne oscillator signal (36
.22 MHz
)
from the PLL circuit, amplified by Q12 (2SC2668Y) to ob-
tain the second IF signal (8
.83 MHz)
. The second IF signa
l
of 8
.83 MHz goes through the gate of the noise blanker
. I
n
modes other than FM , the signal then goes through the MC
F
(F2) and is fed into the IF unit through buffer amplifiers Q
8
and Q9 (2SC2668Y)
.
1) Selectivity circui
t
Figure 4 is a selectivity circuit diagram
. In auto mode, th
e
appropriate bandwidth filter is automatically selected accord
-
ing to mode
. When an optional filter is used, two filters ar
e
available
. Tables 2 and 3 shows the various combinations
When the optional 8
.83 MHz filter is connected, the secon
d
IF signal is then fed from the IF unit into the optional filter
.
In the third mixer, consisting of Q1 and Q2 (3SK73GR), th
e
second IF signal is mixed with 8
.375 MHz signal generate
d
by IF unit's heterodyne oscillator circuit, consisting of Q5
3
and Q54 (2SC2458Y), and converted into the third IF signa
l
(455 kHz)
. The third IF signal is then amplified by Q
5
(3SK73GR)
. A diode switch is used to route the signal t
o
either the FM or SSB circuits
.
In SSB mode, the third IF signal goes through the SSB cer-
amic filter (XF3)
. In AM mode, the third IF signal goes throug
h
the AM ceramic filter (XF4)
. In either mode, the third IF sig-
nal is then amplified by Q7 and Q8 (3SK73GR) and detected
.
In FM mode, the third IF signal goes through the FM cerami
c
filter (XF5)
. The signal is then sent to the FM IF, IC2 (M
C
3357) for amplification and detection
. IC2 also contains a
n
FM noise squelch circuit
.
The detected SSB/AM signal is passed through the notch cir
-
cuit, consisting of hybrid IC IC1 (BX6124) and squelch gat
e
Q12 (2SC2459BL)
. The signal then goes through the A
F
volume control and is amplified to the appropriate level b
y
AF amplifier IC7 (UPC2002V)
.
of bandwidth available when optional filters are used
. In F
M
mode, the selectivity switch does not operate and a singl
e
dedicated FM filter is used
. Optional filters operate only i
n
receive and are separate from the filters used in transmit
.
AUTO SELECTIVITY CONTROL
I
—
X59—1070—00
1
D6
01
I
558
21
,
i
l
a
< ss
R
455 3t_
.
14
/a
D
I
+
R
+
z
'
.
,$W
I
AI
AL
T
D5
02
L a
J
r
p1
<
I
cw
R
R4~~
fro
m
04
IC 1
0
D4
RY
R
D
2
~•
14
i
D3
0 3
Bew
sj
r
l
a
—
i
L_
.
j
J
<A M
R
45A
6
L
RX
B
45A
I
DI I
la
Bow
I
o
D
9
M 2
I4
N
-
88
5
455
0
D
5
45S
(
-
a
D8
6
SELEC-
TIVIT
Y
BBC
AUTO
n
AU
T
454
GNDI
F/14
—
J
Fig
.
4
Selectivity control circuit
MANUAL SELECTIVITY CONTROL
7
TS-440S
CIRCUIT DESCRIPTIO
N
Filter selectiv
e
AUTO MODE
WITHOUT OPTION
OPTION INSTALLE
D
MODE
8
.83MHz
455kHz
8
.83MHz
455kH
z
SSB
Through CFI
XF1
CF
1
CW
Through
CF1
XF2
CF
1
AM
Through
CF2
Through
CF
2
FSK
Through
CFI
XF2
CF
I
FM
Through
—
Through
—
XF1:
YK-88S or YK-88S
N
XF2:
YK-88C or YK-88C
N
Table
2
Item
Ratin
g
Center frequency fo
45
.05 MH
z
Center frequency deviation
fo±
1 kHz at 3 d
B
Pass bandwidth
±9
.6
kHz or more at 3 d
B
Attenuation bandwidth
±28
kHz or less at 10 d
B
Ripple
0
.7 dB or les
s
Insertion loss
2
.0 dB or les
s
Guaranteed attenuation
30 dB or more with
±1
MH
z
(Except spurious
)
Final impedance
2 kS1±10 %IL characteristi
c
Table 4 MCF (L71-0259-05) (RF UNIT
Fl
)
Item
Ratin
g
Center frequency fo
8830
kHz±0
.5
kH
z
Pass bandwidth
±3
kHz or more at 3 d
B
Attenuation bandwidth
±12
kHz or less at 18 d
B
Guaranteed attenuation
30 dB or more within
fo±
1
MH
z
Ripple
0
.5 dB or les
s
Insertion loss
1
.0 dB or les
s
Final impedance
2
.5 kfll3 pF
Table 6 MCF (L72-0260-05) (RF unit F2
)
Item
Ratin
g
Center frequency fo
455
kHz±0
.2
kHz at 6 d
B
6 dB bandwidth (total)
± 1
.1
-1
.3
kH
z
60 dB bandwidth
4
.5 kHz or les
s
Guaranteed attenuation
60 dB or mor
e
(at 0
.1
-1
MI-Iz
)
Spurious (600—700 kHz)
40 dB or mor
e
Ripple with bandwidth
2 dB or less at 60 d
B
Insertion loss
2 dB or les
s
Temperature
— 10°C—
+50°
C
Input and output impedance
2
a
l
Table 8 Ceramic filter (L72-0356-05) (IF UNIT CF1)
MANUAL MODE
WITHOUT OPTION
OPTION INSTALLE
D
SELECT
8
.83MHz
455kHz
8
.83MHz
455kH
z
N
NO
RX
XF2
CF
1
XF1
CF
1
M
1
M2
Through
CFI
Through
CF
1
W
Through
CF2
Through
CF2
XF1:
YK-88S or YK-88S
N
XF2:
YK-88C or YK-88C
N
Table
3
Item
Ratin
g
Center frequency fo
455 kH
z
6 dB bandwidth
±2
kHz or mor
e
40 dB bandwidth
7
.5 kHz or les
s
Insertion loss
6 dB or les
s
Guaranteed attenuatio
n
(within 455kHz ±
100kHz)
35 dB or mor
e
Input and output impedance
2
.0
a
l
Table 5 Ceramic filter (L72-0355-05) (IF UNIT CF2
)
Item
Ratin
g
Center frequency fo
455
kHz±1
'kH
z
6 dB bandwidth
±6
kHz or mor
e
50 dB bandwidth
±12
.5
kHz or les
s
Rippl
e
(within 455 kHz±4 kHz)
3 dB or les
s
Insertion loss
6 dB or les
s
Guaranteed attenuatio
n
(within 455 kHz± 100kHz)
35 dB or mor
e
Input and output impedance
2
.0 kS
l
Table 7 Ceramic filter (L72-0315-05) (IF unit CF3
)
Item
Ratin
g
Center frequency fo
8 830 MH
z
Attenuation bandwidth
±50
kHz or more at 3 d
B
Guaranteed attenuation
35 dB or more at 9 285 MH
z
45 dB or more at 9
.74 MH
z
Insertion loss
6 dB or les
s
Ripple
1
.0 dB or les
s
Input and output impedance
330 S
l
Max
voltage (DC)
50 V (Min
l
Table 9 Ceramic filter (L72-0351-05) (IF unit CF4
)
8
TS-440
S
CIRCUIT DESCRIPTIO
N
2)
AF notch circuit
R OH
M
BX7I91— 851
8
123
10
BX719
I
R7 IOK
R9 22
K
OUT!
-
S
C
5
1
0
+
0 iI t
i
U
W
U
D27
D2
6
Fig
. 5 NOTCH circui
t
The hybrid ICI in the IF unit is an audio notch circuit
.
Figure 5 shows its equivalent circuit
. This circuit forms state-
variable band pass filter, also known as a bi-quad filter
. Th
e
notch frequency can be changed using the notch control vari
-
able resistor
. Since the circuit consists of the hybrid IC, sta
-
ble attenuation characteristics can be obtained electrically an
d
thermally
. The range of variable notch frequencies is 400 H
z
to 2600 Hz
.
The notch frequency is determined by the following tw
o
formulas
.
1)
f
N
,,R6/27r (R1 +Notch VR)•R8•R10•C1
.
C65
1
2)
R6
.
1R12+R13)=R10•R11
2
If a variable resistor is used for resistor NOTCH VR, the notc
h
frequency can be controlled according to formula 1)
.
The notch frequency range is from 400 to 2600 Hz, and at-
tenuation is from 25 to 50 dB
.
9
TS-440S
CIRCUIT DESCRIPTIO
N
3
.
Transmitter Circuit Descriptio
n
IC
4
MIC
pPCI
I58HZ
SS
B
D
<M1C AMP
GAI
N
PRO
C
FSK
IN
45
.05^
-
75
.05MH
z
Q4
6
3SK73
Q10,1
I
3SK122 x2
Q13,1
4
3SKI22x
2
F
I
MC
F
Q4
4
2SC2459
IC
5
AN612
CFI
IC
6
AN612
CF
4
IST
MIX
9
.83MH
z
DB
M
ssB
Q1
6
2SC253
8
LP
F
Q
I
2SC2075
02,3
Q4,
5
2SC2509x2 2SC2879x 2
LPF/
-
0
A
.T
R
X
Fig
. 6 Transmitter circuit
configuratio
n
In SSB, CW, AM, or FSK mode, the transmitter system use
s
triple conversion
. In FM mode, the transmitter system use
s
double conversion using PLL modulation
.
Audio signals from the microphone are applied to the MI
C
pin (connector (21)) of the IF unit and are separated into SS
B
modulation and VOX signals
. The SSB signal is amplified ap-
prox
. 8 dB by IC4 (µ
.PC 1 1 58HZ)
. AFSK audio signals fro
m
the AFSK IN pin (back panel) are also applied to IC4
.
IC4 functions as a SPEECH processor
. Output from IC4 i
s
distributed to the MIC GAIN control (front panel) and FM cir-
cuit (RF unit)
. In SSB mode, the signal applied to the MI
C
GAIN control is sent back to the IF unit (connector (23) MV2)
,
amplified by Q44 (2SC2459), and supplied to the balance
d
modulator IC5 (AN612)
. In FM or CW mode, Q44 does no
t
operate because a cut-off voltage is supplied to its emitte
r
via diodes D82 and D46 . The signal converted to 455 kH
z
10
TS-440
$
CIRCUIT DESCRIPTIO
N
DSB by IC4 goes through the SSB transmit switching diode
s
D17 and D18, filter switching diodes D14 and D12, and SS
B
ceramic filter CF1, to obtain the SSB signal
. The SSB signa
l
then goes through the transmit switching diode D36 and i
s
fed into the transmit first mixer, IC6, where the SSB signa
l
is mixed with the output from the 8
.375 MHz oscillator i
n
the IF unit, and converted to 8
.83 MHz
. In CW or FM mode
,
the carrier signal from the PLL unit does not go through IC
5
BM or the 455 kHz filter
. These carrier signals are applie
d
to IC6 via switching diodes D53 and D54
. The output signa
l
from IC6 goes through the MCF to remove spurious compo
-
nents, and is amplified by the IF amplifier Q46 (3SK73) an
d
sent to the RF unit
. Q46 provides ALC control and C
W
keying
.
In the transmitter second mixer, consisting of Q1 1 and Q12
,
(3SK122), the 8
.83 MHz transmit IF signal input to the R
F
unit is mixed with HET oscillator signal (36
.22 MHz) fro
m
the PLL unit and converted to 45
.05 MHz signals
. The 45
.0
5
MHz signal goes through D23 and the MCF to remove an
y
spurious components
. The 45
.05 MHz signal then goe
s
through D27 and is supplied to the transmit third mixer con
-
sisting of Q13 and Q14 (3SK1 22)
. In the third mixer the sig
-
nal is mixed with VCO signal (Q21 to Q24) amplified by Q1
2
(2SC2668) and converted to the required transmit frequen
-
cy (1
.8 to 29
.7 MHz)
. The signal from the third mixer goe
s
through the low pass filters C156, C158, C159, and L89
,
and is amplified by the wide band amplifier Q15 (2SC2570)
.
The signal then goes through the wide band transformer Ti
9
and low pass filters C164, C165, and L90, and is further am
-
plified by wide band amplifier Q16 (2SC2538)
. The signa
l
from the Q16 goes through the output transformer T20 an
d
is used as the drive output
.
In FM mode, the PLL VCO is directly modulated
. The audi
o
signal from IF unit IC4 (UPC1 1 58HZ) is fed into the RF uni
t
via the FM1 pin
. In the RF unit, the audio signal is amplifie
d
by Q36 (2SC2459) and Q37 (2SC2603), and goes throug
h
the limiter circuit consisting of Q38 (UPC4558C) and lo
w
pass filter circuit, and is sent to the PLL unit via the FM
D
pin
. In the PLL unit, the 36
.22 MHz VCO is modulated
. Q3
9
(2SC2603) is a switching circuit to prevent the modulate
d
signals from being emitted from the PLL unit in a mode othe
r
than FM
.
For
"S"
model radios the output from the RF unit i
s
amplified to a 100 W power level by Q1 (2SC2075), Q
2
and Q3 (2SC2509), and Q4 and Q5 (2SC2879) in th
e
final unit
. The 100 W output goes through the LPFs whic
h
differ by bands, and is sent as output to the antenna via th
e
AT unit and transmit/receive switching relay
. SWR an
d
ALC detection is performed at the output of the LPFs
.
1) Antenna tune
r
The antenna tuner operates when the AUTO/THRU switc
h
is in the AUTO position and the AT TUNE switch is ON
. Th
e
antenna tuner is driven in the CW mode and power is reduce
d
to 50 W by the microcomputer regardless of the mode select
-
ed before the AT TUNE switch was turned ON
. The rang
e
of operating frequencies is determined by a microcompute
r
program, and is from 3
.5 MHz to 30 MHz
.
• AT unit operatio
n
Power transmitted by the final unit passes through the cur
-
rent and voltage detecting transformers L1 and L2 usin
g
toroidal cores
. Current and voltage components detecte
d
by the transformers are supplied to pins 9 and 13 of IC
2
for wave shaping and their phases are compared by IC
3
HD10131
. The output from pin 3 of IC3 depends upo
n
the phase of the voltage and current waveforms applie
d
to IC3
. The signal from IC3 pin 3 is sent to pins 10 an
d
15 of buffer IC IC3 HD10125
. Output from pins 12 an
d
13 of IC3 goes through level shift Zener diodes D5 an
d
D6 to control the input circuit of motor drive IC IC
5
BA6109U2
. The output signal is used to drive motor M
1
to adjust the variable capacitor VC1 so that the phas
e
difference between voltage and current components i
s
reduced
.
The current and voltage components output from the cur
-
rent and voltage detecting transformers is also supplie
d
to the voltage comparator IC1 NJM2903D
. The compa-
rator output is used by motor drive IC IC6 BA6109U2 t
o
drive motor M2 to adjust variable capacitor VC2 so tha
t
the amplitude difference is reduced
. That is, the phase con
-
trol variable capacitor VC1 is controlled so that the cur
-
rent is in phase with the voltage and the voltage contro
l
variable capacitor VC2 is controlled so that the amoun
t
of amplitude difference between the current and voltag
e
is reduced (SWR1, an SWR of 1 to 1, is obtained whe
n
the current and voltage are in phase and the amount o
f
amplitude difference is 0)
. VC1 and VC2 are designed t
o
operate independently of each other, but since phas
e
difference affects the amount of amplitude difference an
d
vice versa, VC 1 and VC2 will normally rotate together
.
Forward and reflected waves detected by the filter unit ar
e
converted to SWR control signals in the SWR arithmetic cir-
cuit in the control unit and are sent to the ISW pin of th
e
AT unit
. Since the SWR control signals are current wave
-
forms, the signals are converted from Ito V waveforms b
y
IC8 (b/4) in the AT unit and to obtain the corresponding vol
-
tage mode SWR signals are generated
. The SWR signals ar
e
then fed into the SWR comparator IC8 (C/4)
. The referenc
e
voltage pin 9 of the IC8 (C/4) is supplied with a voltage cor
-
responding to an SWR of 1
.25 to 1 via a potentiometer
.
Therefore, when the actual SWR value exceeds 1
.25, pin
8
of SWR comparator IC8 (C/4) is H, so the motor drive vol-
tage control transistor Q5 turns on and the collector of Q
4
is supplied with voltage from pin 14S
. The voltage is als
o
used to turn the tuning LED on. The inverted input pin of IC
8
(d/4) is supplied with triangular waves generated by IC7, an
d
its non-inverted input pin is supplied with the above SWR vol
-
tage signals
. As a result, as SWR lowers, IC8 (d/4) outputs
11
TS-440S
CIRCUIT DESCRIPTIO
N
waves changing from continuous waves to relatively low dut
y
pulses
. Q1 is driven by this voltage waveform to control Q2
,
which is connected to the collector of Q4 in series and mo-
tor drive voltage is generated
.
If the motor turns too fast, the SWR value will be smalle
r
than the motor stop value because of the inertia of the mo-
tor
. As a result, the motor will continue to operate even if
the motor stop signal is sent and the SWR value will con-
tinue to be greater than the motor stop value, causing th
e
motor stop signal to turn off. That is, the motor will not sto
p
and it will be difficult to obtain a match
. If the motor spee
d
is too slow, it will take a long time to satisfy a matching con
-
dition
. The TS-440 therefore controls the motor speed ac
-
cording to changes in SWR
.
TUNE STO
P
ADJ
IC8
c/4
Q
5
Triangular
wov
e
generator
Fig
. 7 Antenna
tuner circui
t
The antenna coupler is a T type. Six relays RL100 to RL10
5
are used to change taps within the range 3.5 MHz to 30 MHz
.
2) Cooling fan circui
t
The final unit contains the temperature-sensitive thermisto
r
TH1 thermally coupled with final transistor Q4
. When tem-
perature on the surface of Q4 reaches approx
. 50°C, the fa
n
start comparator Q9B operates (H level), causing Q8 to tur
n
on to operate the fan
. During operation of the fan, tempera
-
ture protection comparator Q9A is at a L level, so the tem-
perature protection circuit does not operate
.
When temperature on the surface of Q4 goes down to 45°C
,
the cooling fan turns off
.
•
Final temperature protection
circui
t
When the temperature of the final transistor Q4 rises u
p
to approx
. 80°C, the temperature protection comparato
r
Q9A turns on (H level), Q1 in the filter unit also turns on
,
and a minus DC voltage is supplied to the ALC line, reduc
-
ing the transmitter output to zero
. (The TS-440 does no
t
return to a receive state
.) When the temperature of th
e
final transistor Q4 falls to approx
. 70°C, the protectio
n
circuits turns off allowing the transmitter to operate again
.
•
SWR protection circui
t
When antenna VSWR is bad, or the reflected wave is to
o
large, because the auto antenna is tuning for example, L4
2
and L43 detect the state and its output is rectified
. Th
e
rectified signal is then amplified by Q2 to control the AL
C
voltage so that drive power is reduced. As a result, loa
d
on the final unit is reduced
.
•
SWR automatic arithmetic circui
t
The TS-440 uses the automatic arithmetic circuit in th
e
AT-250
. The forward wave voltage
VSF
and reflecte
d
wave voltage
VSR
from the filter unit are fed into the ana
-
log arithmetic circuit of the switch unit, and used to se
t
the voltage level of IC8 pin 2 (5 V
+VsR/VSF)
.
Output vol-
tage from the pin 2 is shifted by IC5 to move the needl
e
in the SWR meter
.
IC5 contains a level shift/meter amplifier and an auto tune
r
V-I convertor
. IC7 contains a square wave generator an
d
a voltage comparator
. IC8 contains an integration circuit
.
Q3 and Q4 are used to switch forward and reflected wav
e
input signals alternately
.
Comparato
r
output
Q9
B
/45°
/50°
0° Bo°
Temperature °
C
FAN
OFF FAN
ON
Thermal
Therma
l
protection OFF protection O
N
Fig
. 8 temperature protection operatio
n
V
12
TS-440
S
CIRCUIT DESCRIPTIO
N
Vs
F
is compared with voltage from IC8 pin 6 (5
.5 V)
.
When SWR increases,
VSF
lowers and the voltage leve
l
of IC8 pin 8 rises
. At IC7 pin 3, a triangular wave is moni
-
tored
. The triangular wave is compared with the wav
e
from IC8 pin 8 and output
. The triangular wave is con-
verted to a square wave by IC10 and sent to switch Q
3
and Q4
. This voltage is used as the SWR control voltage
.
Output voltage from IC8 pin 2 consists of the voltage com
-
pared with VsR/Vs
F
and + 5 DC voltage
. It is distribute
d
to IC4 the level shift/meter amplifier to move the needl
e
in the SWR meter and IC5 the V-I convertor to control th
e
AT440
.
VR14 is used to adjust the SWR meter ZERO point
.
VR 13 is for SWR meter adjustmen
t
3) FULL/SEMI BREAK-IN and VOX circuits
RL TXB RX
B
MICROPROCESSOR
STAND-B
Y
CIRCUIT
CONTROL
POWER SUPPL
Y
CONTRO
L
CIRCUIT
KEYIN
G
CIRCUI
T
VO
X
CIRCUIT
Fig
. 9-1 FULL/SEMI BREAK-IN block diagra
m
When the standby switch, the key, or the VOX switchin
g
transistor are activated, a ground is applied to the input pi
n
of the control circuit, which causes a standby signal to b
e
fed to the microprocessor to determine if a valid transmit con
-
dition has been met
. When that condition has been met, th
e
KEYIN
G
STAND-B
Y
VOX
standby circuit in the IF unit will be turned on
.
A keying signal is generated by the control circuit, wheneve
r
the key is depressed, to control the keying circuits in the I
F
unit
. This keying signal is also used as the transmit/receiv
e
signal during break-in operations
.
o KEYING (FULL
)
o CONTROL( FULL
)
o KEYING(SEMI
)
0
CONTROL(SEMI
)
Fig
. 9-2 FULL/SEMI BREAK-IN timing chart
13
TS-440S
CIRCUIT DESCRIPTIO
N
FULL
BREAK-I
N
H
A
L
B
L
1
KEYING I
N
C
L
H
D
E
F
G
KEYING OU
T
L
H
L
L
L
H
H
L
CONTROL OU
T
SEMI BREAK-IN, VO
X
A
L
H
L
KEYIN
G
VOX
I
N
CONTROL OU
T
F
L
H
J
KEYING OU
T
VO
X
Fig
. 9-3 FULL/SEMI BREAK-IN
timing char
t
The above timing charts show the timing for standby an
d
keying signals
.
When an input from the CW key is supplied to point A a
s
shown in the above figure during full break-in operation
,
the one-shot multi-vibrator and gate circuits generate con
-
trol (full) and delayed keying (full) signals
. After the fun-
damental timing signal, RL (12V) for reception an
d
transmission rises, the keying wave also rises, and whe
n
the key is off, RL falls according to the preset tim
e
constant
.
Semi-break-in operation is synchronized to VOX
. When
a
signal is supplied to point A, the VOX delay time multi
-
vibrator determines the VOX time constant
. The input sig-
nal is converted to a keying (semi) signal by the gat
e
circuit
.
These keying semi/full and control semi/full signals ar
e
converted to appropriate break-in VOX mode signals us
-
ing the slide switch
. The control signal is checked by th
e
microcomputer to see whether transmission is to be per
-
formed
. The control signal is then used to switch CRL i
n
the IF assembly unit and generate RL (12 V)
. TXB (trans-
mit
B+)
(8
.8 V) is generated, synchronized to RL
. Th
e
receive control signal RXB (receive
B+)
(8
.8 V) turn
s
on/off, synchronized to the inverted TXB signal, that is, RL
.
RL
12
V
TXB
8
.8
v
RXB
8
.e
v
Fig
. 10 STANDBY keying timing char
t
14
TS-440
S
CIRCUIT DESCRIPTIO
N
4) Speech
processo
r
IC4 in the IF unit functions as the first stage microphone am
-
plifier or audio speech processor
. When the processor switc
h
is off, IC4 functions as a 20 dB microphone amplifier
. Whe
n
the processor switch is on, IC4 functions as an up to 40 d
B
PROCESSOR OF
F
ON
Fig
. 1
1
MIC
gain amplifier with ALC. When the processor switch is on
,
8 VDC is supplied to the base of the gain adjustment switch
-
ing transistor, Q41, driving the feedback amplifier
.
GAIN 2Od
B
MAX GAIN 4Od
8
4
.
PLL Circuit
s
Theory
of
PLL
circuit
operation
s
The TS-440 PLL circuit uses a reference frequency of 36 MH
z
and consists of five PLL loops covering the range of frequen
-
cies from 30 kHz to 30 MHz in 10 Hz steps
. The PLL circui
t
has an IF shift function which is implemented by insertin
g
carrier frequencies between PLL loops
. The PLL loops includ
e
a carrier circuit PLL loop and an HET circuit PLL loop whic
h
generates a constant frequency of 36
.22 MHz
. Frequenc
y
division for these PLL loops is controlled by the microproces
-
sor
. In all PLL loops phase comparison is made using the refer
-
ence frequency fSTO (frequency control using a single crysta
l
oscillator)
.
Figure 12 is the PLL circuit block diagram
.
The reference frequency (fsro) is generated by a 36 MH
z
crystal oscillator and Q21 (2SC2787)
. Reference frequenc
y
signals are fed into the main loop's IC1 1 (SN16913P) via
a
buffer consisting Q22 and Q23 (2SC2668)
. The signal is als
o
fed into IC13 (SN74S112) via a buffer consisting of Q2
4
(2SC2668)
. In IC13, the signals are frequency divided t
o
generate a 9 MHz signal
. The 9 MHz signal is used as th
e
reference frequency signals for the PLL loops
.
•
PLL
5
PLL5 consists of IC 18 (MN6147) and its associated loo
p
components
. VCO5,Q36 (2SK192A), is locked at a fre-
quency of 36
.22 MHz
. The 9 MHz reference frequenc
y
signal is supplied to pin 3 of IC 18, where the signal is divid
-
ed by 1800 (450 in FM mode) to generate
a
5 kHz (2
0
kHz in FM mode) signal used for comparison
. VCO5's out
-
put signal is supplied to IC 18 pin 16 via Q37 (2SC2668)
,
where the signals are frequency divided by 7244 (181
1
in FM mode)
. The phase of the signal is then compare
d
with that of the 5 kHz (20 kHz in FM mode) signal by th
e
phase comparator and the VCO5 oscillation frequency i
s
locked
. Frequency division data is supplied by digital uni
t
(DAO to DA3 and CK4)
.
As described above, the dividing ratio used varies depend
-
ing on which mode the TS-440 is in, FM mode or SSB
.
This is because the apparent time constant is increase
d
without changing the active LPF constant so that the PL
L
signals can be modulated easily and reducing distortio
n
during FM transmission
. In modes other than FM, th
e
amount of frequency shift due to mechanical vibration
s
is reduced because the apparent time constant is reduced
.
The output from PLL5 goes through buffer Q38 (2SC2668
)
and LPFs, and is used as the HET signal in the RF unit
.
15
TS-440S
CIRCUIT DESCRIPTIO
N
VCO I A 45
.08
.
. 52
.55 MH
z
8 52
.55
..
. 59
.55 MH
z
C 59
.55
.
. 67
.05MH
z
D 67
.05
.,
. 75
.05MHz
Q3
6
I
fLO
J
---
-
024
2502459
.
2
034,3
5
IC
1
3
Di
v
4
9MH
z
BUF
F
2502668
SN7RS,12
N
6
r ST
D
ST
D
OSC
Q2
1
250278
7
Q2
2
BUF
F
2SC266
8
BPF
O
FM MO
D
0
9
UFF
I
I
36
.22MHZ
037
03
8
118111 FM
)
3
I C
SN 74LS9
0
IC
2
4
.55MH
z
LPF
7244 9MH
z
15KHZ1
20KHZ
: FM
I
6 14
7
IC18
250245
8
AMR,FMR
: O
N
/456
.5KHZ USB,C
W
1453
.5KHZ LSB,FSK
1
`\
AMR,FM
R
®
to
-
Q
6
AMT , FM
T
455KHZ
Q
7
25C266B
(OCT
I
4508-
.]5G5MH
=
. .
LO
256192
4
Q25
1
8 375MH
z
SN16913
8
0
.175-30
.675M
H
023
BUF
F
SNI6913F 250266
8
IC1I
IC8
6
.53-
.6
.63MHZ
10
7
2502668
VC
O
25C266B
55
A
5
vco
Co
D
ICI4
SN15913
3
5
.82
5
P
5 32 5
8
.5539
.05 MH
z
2502668
2S 0266822
020
0
AM,F
M
91MHZ /91
.3MHZ
. USB
4
O
w
2SC2668 90
.7MHZ
: LSH
.FS
K
A
.LPF
o
3l
,
32
,
33
2502459 x
3
}
500KH
z
P
.
_
PHA
. C
.
1017
9MH
x
3-]3
1
i
PLL
II
6
.5-
.36
.5MH
Q2
6
2SC2668
IC1
2
2SC245
8
BUFF
L
DIV
SN74SII2N
IC1
6
1/30,1/2
SN74SION
IC1
5
4
030
029
Q27,2
8
\
2SC2668
HET
CA
R
SFT
CA
R
05
2SC2668
2502458
250195
9
2SC266
8
15K Hz
(
P
D
111
019
5
SN16913
P
2SC2668
459
L
SN16913P 2502458
PL L
4
01,
2
25031132
2
IC1
0
54460
L
58
.25-53
.25MHz
Q1
8
016,17
I
PLL
3
2502668 2SC266
8
I20KHZI
IC9
015
01
3
2502668
®
9MHz K 1820
0
I/ 18260
: USB , C
w
\18140 LS8,FS
K
IF SHIFT I-40--40
1
CAR
I-16-
. 15
)
B
.A
P
A
LPF
h-1
P
.
D
I
'PHA
. C
.
2503113 x 2
S 1 R
MN6147 2802668
99
.
-IO
4
Q12
250266
6
IC
5
64
.78-59
.88MHz 1
.98-2
.08M4z
IC
6
/
5
01
4
BUF
F
LPF
DI
V
I/1
0
B P F
MN6147
C I
SN74LS90N M54460L
2SC266
8
M 9MHz
010,11
(5K
H
3239
.
. 2994 (STEP 51
A
. LPF
P D
_ IC
4
HA C
MN 614
7
2503113
. 2
L 9MHz
RITZ-120- ,120
1
19800- 2079
9
Fig
. 12
PLL circuit block diagra
m
•
PLL
4
PLL4 consists of IC1 (MN6147) and its associated loo
p
circuit
. VC04, Q3 (2SC2668), is locked at a frequenc
y
of aproximately 91 MHz, which differs depending on th
e
operational mode
. The 9 MHz reference frequency is ap-
plied to pin 3 of ICI, where the signal is divided by 180
0
to generated the 5 kHz signal for frequency comparison
.
The output of VC04 is supplied to IC1 pin 16 via buffe
r
amplifier Q4 (2SC2668)
. In ICI, the output is divided b
y
an appropriate division ratio (18200 or so) which differ
s
depending on the mode
. The phase of the signal is com-
pared with that of the 5 kHz reference signal by the phas
e
comparator and the VC04 oscillation frequency is locked
.
Frequency division data is sent from the digital unit (DA
O
to DA3 and CK3)
.
The output from PLL4 goes through buffer amplifier Q
5
(2SC2668) and is divided by 20 in IC2 (M54459L(
. Th
e
signal is further divided by ten in the carrier circuit of IC
3
(SN74LS90N) and then fed into the IF unit as the carrie
r
signal via the LPF, and buffer Q7 (2SC2458) and Q
8
(2SC 1959)
. In AM or FM receive mode, switching circui
t
Q6 (2SC2458) operates when an SFT signal is sent, an
d
as a result, IC3, Q7, and Q8 are stopped to cut carrie
r
signals
.
The PLL4 output signal also goes through the LPF an
d
buffer amplifier Q9 (2SC2458) and is fed into the mixe
r
in the main loop, where the signal is used to form the dig
-
ital VFO signal
. As a result, the operating frequency doe
s
not change even if the carrier frequency is changed, whic
h
enables USB and LSB mode switching IF shift and fine car
-
rier point adjustment
. In SSB, CW, or FSK reception mode
,
the may be shifted +/– 1 kHz or more and the carrie
r
point can be adjusted in the range from – 400 Hz to + 35
0
Hz
.
•
PLL
3
PLL3 consists of IC4 (MN6147) and its associated loo
p
components
. VCO3, Q12 (2SC2668), is locked in th
e
range of 99 MHz to 103.995 MHz
. The 9 MHz referenc
e
frequency signal is supplied to pin 3 of IC4, where the sig
-
nal is divided by 1800 to generate the 5 kHz signal fo
r
frequency comparison
. The output of VCO3 goes throug
h
buffer amplifier Q13 (2SC2668) and is applied to IC4 pi
n
16
. In IC4, the output is divided by L and the phase o
f
the signal is compared with that of the 5 kHz referenc
e
signal by the frequency comparator, and VCO3 oscillatio
n
frequency is locked (in 5 kHz steps)
. The division ratio
,
L, is supplied by the microprocessor, in the digital unit
,
(DAO to DA3 and CK2)
. L is in 1000 steps (19800 t
o
20799) corresponding to 0
.00 kHz to 9
.99 kHz
. In C
W
receive, in order to obtain 800 Hz beat signals in the oper
-
ation frequency display, the L is shifted
-80
(19720 t
o
20719) and when RIT/XIT operates, the Lis changed s
o
that fvco is shifted +1– 1
.2 kHz or more
. In AM or F
M
mode, the L is shifted by 10 steps to change
fvco
by 10
0
Hz steps
.
Output from PLL 3 goes through buffer amplifier Q1
4
(2SC2668) and it is divided by ten in IC5 (M54460L) an
d
then by five in IC6 (SN74LS90N)
. The signal is then fe
d
16
TS-440
S
(
CIRCUIT DESCRIPTIO
N
into pin 2 of MIX5 IC7 (SN1 691 3P) via the LPF
. In MIX5
,
the signal is mixed with the signal generated by PLL4 an
d
goes through the BPF to generate a signal in the range o
f
6
.53 MHz to 6
.6301 MHz (in 100 Hz steps)
. The gener-
ated signal is supplied to pin 5
.
•
PLL
2
PLL2 consists of IC9 (MN6147) and its loop circuitry
.
VCO2, Q18 (2SC2668(, is locked in the range of 58
.2
5
MHz to 53
.2501 MHz
. The 9 MHz reference frequenc
y
signal is supplied to pin 3 of IC9, where the signal is divide
d
by 450 to generate a 20 kHz signal for frequency com-
parison
. VCO2's output goes through buffer amplifier Q1
9
(2SC2668(, and is fed into MIX4 pin 2 and mixed wit
h
the 6
.35 MHz to 6
.63 MHz signals applied to pin 5
. Th
e
mixed signal then goes through the BPF to obtain 64
.7
8
MHz to 59
.88 MHz signal (in 100 kHz steps)
. Th
e
64
.78 MHz to 59.88 MHz signal is fed into IC9_ pin 16 vi
a
buffer amplifier Q15 (2SC2668)
. In IC9, the signal is divide
d
by M, and the phase of signal is compared with that of th
e
20 kHz reference signal by the phase comparator, and thu
s
MIX4 output is locked (in 100 kHz step)
. The division ratio
M
is supplied from the digital unit (DA0 to DA3 and CK1), and i
s
in 50 steps from 3239 to 2994 corresponding t
o
0
.00 MHz to 0
.49 MHz
.
The output from PLL2 goes through buffer amplifier Q2
0
(2SC2668) and is divided by ten in IC 10 (M54460L)
. Vi
a
the LPF, the signal is fed into pin 2 of MIX3 IC1
1
(SN 16913P)
. The frequency of the signals depends on th
e
values of L and M, and is in the range of 5
.825 MHz t
o
5
.32501 MHz (10 Hz step)
.
VR1 in MIX4 circuit is used to suppress spurious output
s
from the mixer
. It is necessary to prevent PLL2 from be
-
coming unlocked
.
Signals generated by PLL2 and the 9 MHz reference fre-
quency are mixed in MIX3
. The mixed signal goes throug
h
the BPF, and is further mixed with
fLo
in MIX2 IC1
2
(SN16913P) on the IF unit
. The output from MIX2 goe
s
through the BPF to obtain 38
.55 MHz to 39.04999 MHz
.
The signals are then mixed with the output from the fina
l
VCO oscillator in MIX1
.
•
PLL
1
The last PLL loop, PLL1, consists of IC1 7 (MB87006) an
d
its loop components
. In IC 17, frequency division for refer
-
ence and comarison frequencies is set by serial data (SO
,
SCK, and LEI
. When an external prescaler is used, IC1
7
has a modulus control function for configuring the puls
e
swallow counter
.
The VCO oscillator output from the RF unit goes throug
h
Q26 (2SC2668) in the PLL unit and is fed into MIX 1
. Th
e
mixed signals go through the BPF, and they are then am
-
plified by buffer amplifiers Q27 thru Q30 (2SC2668)
,
shaped by IC 15 (SN74S 10N 1 /3), and fed into IC 1
6
(WN74S 1 12N) 1/3, or 1 /2 prescaler
. Basically, IC 16 is
a
two-level FF circuit and functions as a 1 /4 divider. But
,
when IC17 of the PLL unit sends control signals, to IC 1 6
,
IC 16 functions as a 1 /3 or 1 /2 frequency divider in con
-
junction with IC 1 5 (2/3)
. That is, the IC 1 5, IC 16, and IC1
7
form a pulse swallow frequency divider
.
The 9 MHz reference frequency signal is supplied to pi
n
1 of IC17, where the signals are divided by 18 to gener-
ate a 500 kHz signal for frequency comparison
. Signal
s
fed into IC17 pin 8 via MIX1 and the buffer amplifier ar
e
divided by N, and the phase is compared with that of th
e
500 kHz reference signals by the phase comparator
. Th
e
signal then goes through the active LPFs Q31 to Q3
3
(2SC2459) and is fed into the RF unit as VCO voltage sig
-
nals to control the variable capacitor of the final VCO
. Th
e
frequency divider N covers the full range of operating fre
-
quencies from 30 kHz to 30 MHz (500 kHz step), and i
t
has 61 steps of frequency division data supplied by th
e
microprocessor in the digital unit
.
The last VCO signal in PLL1 therefore depends on th
e
values of L, M, and N, and it is in the range from 45
.0
8
MHz to 75
.05 MHz (10 Hz step)
. N is expressed a
s
follows
:
N=PNo -
A
(No>A
)
P
:
Prescaler module valu
e
No
: Programmable counter valu
e
A
: Swallow counter valu
e
PLL IC contains No and A
.
The last VCO unit is contained in the RF unit and consist
s
of four VCOs, each handling one portion of frequencie
s
from 30 kHz to 30 MHz
. The appropriate VCO is selecte
d
by the microprocessor according to band information fro
m
the digital unit
.
•
Unloc
k
If a PLL loop enters a unlock state, the output on the U
L
pin becomes L
. This L signal is sent to the digital unit t
o
stop the microprocessor
.
•
500
kHz marker signa
l
The 500 kHz reference signal for frequency compariso
n
is supplied from IC17 pin 13, and it is used as the marke
r
reference signal
.
5
. Digital control circui
t
The TS-440 digital control circuit uses an 8-bit CPU (7800
)
which does not contain ROM, and has a 16K ROM (27128
)
and a 2K RAM 18418) outside the CPU
. A common bus use
d
for data exchange between the CPU and RAM, and betwee
n
the CPU and ROM and is also connected in parallel to th
e
two 8255's for extended I/O and an 8251 for interface t
o
a personal computer (option)
. To transfer
data
to
or
from a
n
appropriate IC, the CPU uses the WR or RD signal
,
and the chip select signal from the 74LS138
.
The display is dynamically controlled by software, and con-
sists of 13 digits and nine segments
. The 13 digit and seve
n
segment signal is driven by the high voltage resistive buffe
r
(6300), and the other two segment signals are driven by
a
transistor
. The 7800 transfers data serially
. The clock signa
l
is frequency divided by two in the 4013 and sent to the 6300
.
Using the 4011 and 4030, the encoder generates count
17
TS-440S
CIRCUIT DESCRIPTIO
N
pulses and U/D signals from two clock signals which are 90
°
out of phase with each other, and sends the pulses and sig-
nals to the 7800
. A clock pulse interrupts the 7800 and
a
U/D signal causes the 7800 to perform a count up or dow
n
operation for each step
. If fast rotation occurs, the 780
0
processes several steps of PLL data at one time
.
Voltages from the RIT and IF shift VRs are converted fro
m
analog to digital by the A/D convertor IC (4052) and fed int
o
the 7800
. The voltages are used to drive the display and ar
e
reflected in the PLL data
.
The digital control circuit contains two 8255's for extende
d
I/O
. The 8255 in control unit A is an outputonly element an
d
the 8255 in control unit B is an inputonly element for ke
y
scan and static data
. The output 8255 emits VS-1 signals,
PLL data for the 6147, clock signals, and 1 MHz LED data
.
The input 8255 receives key scan data such as panel switc
h
data and DIP switch data for CAR compensation
. It als
o
receives static data which cannot be entered as a portion ke
y
scan data
.
The 7800 outputs four bits of band and mode informatio
n
(11 bands in the frequency range from 30 kHz to 30 MHz)
.
Each time the 8251, used as the interface to a personal com
-
puter, receives one byte of data, the 7800 is interrupted an
d
reads the data from the 8251
. The 7800 analyzes any com-
mand in the data
. In response to the command, the 780
0
controls setting or writes data to the 8251 as required
. Th
e
8251 serially sends one byte of data including a start bit, syn
-
chronizing to a 4800 Hz clock signal
.
RIT IF-SNIF
T
En<mer
count pufs
e
Enc
.
.
u/C s
.9no
l
n ock s,gno
l
A/O converter data
Made lnfnrmaY
Y
O,
:A LEO)
e
/0 control
,E
,
_SB,US0,CW,AM,FM,FSH1
)CIOAk,por',select
t
Tx
e'•al
0,1
Seeial o
t
,O
)
Outdo
.
;clock dot)-
,
Band ,nformofion
(PLC
.195)58,FIP
. 630
0
Enable 2
;
Power down IPO
I
(PLL
:145158,Fi P
.6300
1
Peounwa
l
1825`IAI,l8)
e
825)
)
PIP
C
L
_ J
Rs-232
C
85-I
converter C
S
(Address s rt)
Ton
e
AF Mole (MY)
conirallTON
)
LE
D
PP
Mule 1590)
(M SCR, IMU
,
PLL do
Lock
)
.
.
.too,
dota
l
OPTION
Vs
-
Ines,
I
Lack S
W
AT S
W
MIC UP/DOWN S
W
PTT S
W
vs-I
dos,
.
Key sca
n
0 ke
y
V, SCAN, CLEA
R
.
.,N
. EN
T
tT
,
Et,
T,T-FSE
TA/
B
SPRIT, A=
9
VOICE U
DOW
N
\CAN SW
i
pra NOn
/
'
Fig
. 13 Control
circuit block diagra
m
18
TS-440
S
CIRCUIT DESCRIPTIO
N
1
. Encode
r
The TS-440S uses an optical encorder
. Two different cloc
k
signals from the encoder are
90°,
out of phase with eac
h
other
. This phase difference is not adjustable but depend
s
on the precision of the module
. The two clock signals are
converted into clock pulses (250 pulses/rotation x 4) and U/
D
signals indicating the direction of rotation by the 4011 an
d
4030 and fed into the 7800
. Figure 1 5 is a timing chart fo
r
clock pulse and the U/D signal transmitted to the 7800
.
,uPD7800G
Fig
. 14 Encoder circui
t
4I
I
B
6
8
8
8
4
8
3
81
1
C
4
A
4
CI
O
A1
0
C
2
012
84 BI
I
BIO 8
3
BIO 81
1
B4 - B
3
COUNT PULS
E
BIG
I
—
U/D SIGNA
L
Fig
. 15 Encoder waveform timing chart
19
TS-440S
CIRCUIT DESCRIPTIO
N
2
. Digital displa
y
FIP digit and segment signals are driven by the 6300 bu
t
decimal point and red character signals are driven by a tran
-
sistor
. 8 V is used to increase the brightness of red charac
-
ters
. The 7800 sends display data serially at 1 MHz, but th
e
clock signals are divided by two (500 kHz) in the 4080 an
d
fed into the 6300
. Figure 16 shows how the frequency divi
-
sion is accomplished
. The 7800 sends data from its SO pi
n
Switch uni
t
+5v
(pin 28) and a clock signal from its SCK pin (pin 26) at ap-
prox
. 1 ms intervals
. After the 7800 has sent 8 bits of dat
a
five times, the 7800 sends a negative enable pulse from por
t
B5 (pin 46)
. When a decimal digit goes on, the 7800 set
s
port C4 to L and when a red character goes on the 780
0
sets port C3 to H
.
-------------------
-
+g
~
L
1~)
N_
O Q,
O
I()
e
M N
-
0 0 O 9 0 0 0 O U O
O
O
0
02 03 04 05 06
On 08
09 010 011 012 01
3
1
0
0
0
0 0 0 0 0 0
0 0
0
1
00
01 01 9
O
n0
1
014 01
5
o
c
20 bit Display buffer resisto
r
IC3 TC40I3BP A/2
i
f'
p P
D
7800G
46
O
28
5
C
K
D
0
CL P
R
10
8
9
13
S
I
c
LH
contro
l
circuit
20bit Serial shift resisto
r
1 1 1-
---
fl
-
>
J
IC
I
pPD6300C
s
o
s
IC
3
TC40I3BP B/
2
D
26
SCK
3
2
CL PR
Fig
. 16 Digital circui
t
3. Key scan inpu
t
The key scan input block sends key scan signals (negativ
e
pulses) from its 8255 (IC53) port C in the order of CO to C
7
(C6 and C7 are output only once when the POWER switc
h
is turned on)
. When a matrix crossing point switch is on, its
corresponding bit in the 8255 port A is L to enable the switc
h
to be identified
. Figure 13 shows the matrix
. Key scan S
6
and S7 are provided for the extended function using diodes
.
Key
scan
matrix
S
1 2
3
4
5
6
1 1
LSB
2
USB
3
CW
4
AM
5
F
M
2 6
7 8 9
0
FS
K
3
V/M
MV
SCAN
M
.IN
CLEAR
EN
T
4
RIT
ZIT
T-FSET
1MHz
DOW
N
K
5
A/B
SPRIT
A=B
25L
1
U
.
P
6
VOICE
.
T SET ON
CLOCK 1
100L
3
50L
2
100U
8
7
T
.SET OFF
200L
4
25U
6
200U
9
8
TIMER
SET
CLOCK 2
400L
5
501
7
400U
10
Table 10
. Key scan matri
x
20
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