Specialized Functions
VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 5
Bifurcation Usage (for Sabertooth x16 PCIe)
The EPMe-51 (not available on the EPU-5120) provides a PCIe/104 Type 1 Stack-Down
connector on its I/O Board. This connector makes use of the Coffee Lake H CPU PEG
port to implement the x16 PCIe interface that allows for use of a PCIe/104 GPU or other
higher bandwidth peripheral cards in a stack-down application. This section explains
usage details of this interface since the bifurcation hardware straps can be modified by
the CPU Board FPGA, but also note there are BIOS Settings available that should be
used to configure these processor strap settings rather than using direct writes to the
FPGA. Please refer to the Sabertooth BIOS Reference Manual for details on how to
access the Bifurcation settings.
The Bifurcation and Lane Reversal settings for the x16 PCIe interface are described in
the CPUSTRAPS Register for the CPU Board FPGA below, but here is a supplemental
summary of how this works:
By default, x16 Bifurcation with PCIe Lane Reversal disabled is assigned via the
CPU straps. Any x16 PCIe/104 peripheral will work with Type 1 hosts only and
must be stack-down compatible for use with Sabertooth. The peripheral should
be available to the system from the first power up unless specific drivers are
required. The default setting will also work with any lane width requirement for
the PCIe/104 peripheral (x16, x8, x4, x2, x1), but it will consume the entire x16
lanes for the implementation and simply power down the lanes which are not
needed for the link.
If there is a desire to use 2 x8 PCIe links or 2 x4 PCIe links bifurcation instead (allowing
for use of two stacked x8 and/or x4 PCIe/104 peripherals), there are a few more
considerations involved:
The first power up will only allow the system access to the peripheral allocated as
“PCI Slot 1” which with PCIe Lane Reversal disabled would be the second board
below the Sabertooth added to the stack because PCIe/104 stack-down rules
allocate the eight higher order PCIe lanes first and then shift the eight lower order
“unused lanes” to the next board in the stack. In order to see the first board
below the Sabertooth added to the stack with this bifurcation setting (which gets
allocated as “PCI Slot 2”) you would have to perform a reboot (reset) of the
system (making sure the main power input does not get cycled to the Sabertooth
or the PCIe/104 stack).
Enabling PCIe Lane Reversal will change the order of the PCI Slot allocations
(so PCI Slot 1 is the first board down and PCI Slot 2 is the second), but this
enable also reverses the numbering assignment of the lanes to the link so the
PCIe/104 peripherals used would have to support PCIe Lane Reversal as well.