VersaLogic Eagle (VL-EPU-5120) Reference guide

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual i

Programmer

Reference

Manual

REV. August, 2023

Sabertooth

(VL-EPMe-51)

Eagle

(VL-EPU-5120)

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual ii

WWW.VERSALOGIC.COM

10230 SW Spokane Court

Tualatin, OR 97062-7341

(503) 747-2261

Notice:

Although every effort has been made to ensure this document is error-free, VersaLogic

makes no representations or warranties with respect to this product and specifically

disclaims any implied warranties of merchantability or fitness for any particular purpose.

VersaLogic reserves the right to revise this product and associated documentation at

any time without obligation to notify anyone of such changes.

Other names and brands may be claimed as the property of others.

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual iii

Product Release Notes

Revision 1.0 – Initial Release

Support Page

The product pages below contains additional information and resources such as:

 Operating system information and links to software drivers

 Data sheets and manufacturers’ links for chips used in this product

 BIOS and PLD information and upgrades

EPMe-51 (Sabertooth)

https://www.versalogic.com/product/Sabertooth/

EPU-5120 (Eagle)

https://www.versalogic.com/product/Eagle/

Customer Support

If you are unable to solve a problem after reading this manual or visiting the product

page, contact VersaLogic Technical Support at (503) 747-2261. VersaLogic support

engineers are also available via e-mail at [email protected].

Repair Service

If your product requires service, you must obtain a Returned Material Authorization

(RMA) number by calling (503) 747-2261.

NOTE: Please mark the RMA number clearly on the outside of the box before returning

Please provide the following information:

 Your name, the name of your company, your phone number, and e-mail address

 The name of a technician or engineer that can be contacted if any questions

arise

 The quantity of items being returned

 The model and serial number (barcode) of each item

 A detailed description of the problem

 Steps you have taken to resolve or recreate the problem

 The return shipping address

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual iv

AS9100

All AS9100 products dispositioned for scrap shall be conspicuously

and permanently marked, or positively controlled, until physically

rendered unusable.

Material designated for scrap may be recycled in a manner that

complies with applicable environmental regulations.

NOTE: VersaLogic recommends that all materials be disposed of in environmentally responsible

manner i.e., recycling in compliance with applicable laws and regulations.

Warranty Repair

All parts and labor charges are covered, including return shipping

charges for UPS Ground delivery to United States addresses.

Non-Warranty Repair

All approved non-warranty repairs are subject to diagnosis and

labor charges, parts charges, and return shipping fees. Please

specify the shipping method you prefer and supply a purchase

order number for invoicing the repair.

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 1

Contents

Introduction ..................................................................................................................... 1

Description ............................................................................................................ 1

Related Documents ............................................................................................... 1

System Resources .......................................................................................................... 2

FPGA I/O Space .................................................................................................... 2

Interrupts ............................................................................................................... 2

Specialized Functions .................................................................................................... 4

Switch Settings ...................................................................................................... 4

Secure Erase ......................................................................................................... 4

Data At Rest .......................................................................................................... 4

Bifurcation Usage (for Sabertooth x16 PCIe) ........................................................ 5

BIOS Auto-Failover ............................................................................................... 6

FPGA Registers ............................................................................................................... 7

CPU and I/O FPGA Register Access Key ............................................................. 7

CPU and I/O Reset Status Key ............................................................................. 7

CPU Board FPGA Register Map ........................................................................... 8

I/O Board FPGA Register Map .............................................................................. 9

Register Access Key ........................................................................................... 10

Reset Status Key ................................................................................................. 10

CPU Board FPGA Register Descriptions ............................................................ 11

PCR – Product Code & LED .................................................................... 11

PSR – Product Status .............................................................................. 11

SCR – BIOS and Jumper (Switch) Control/Status Register .................... 12

SPIMISC – SPI Control Register ............................................................. 13

CPUSTRAPS – CPU Strap Control/Status Register ............................... 14

MISCSR1 – Misc Control Reg #1 ............................................................ 15

MISCSR2 – Misc Control Reg #2 ............................................................ 16

MISCSR3 – Misc Control Reg #3 ............................................................ 17

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 2

WDT_CTL – Watchdog Control Register ................................................. 18

WDT_VAL – Watchdog Value Register ................................................... 19

FANCON – Fan Control Register ............................................................ 20

FANPWMDC – Fan PWM Duty Cycle Control Register .......................... 21

FANTACHLS, FANTACHMS – FANTACH Status Registers ................... 21

TEMPICR – Temperature Interrupt Control Register ............................... 22

TEMPISTAT – Temperature Interrupt Status Register ............................ 23

FANPWMDIV0, FANPWMDIV1 – Fan PWM Frequency

Control Registers ..................................................................................... 24

Product Information Registers ................................................................. 25

BIOS and Jumper Status Register ........................................................... 26

Timer Registers ....................................................................................... 26

Miscellaneous FPGA Registers ............................................................... 30

Programming Information for Hardware Interfaces ................................................... 44

Watchdog Timer .................................................................................................. 44

Programmable LED ............................................................................................. 44

Processor WAKE# Capabilities ........................................................................... 45

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 1

Introduction

Description

This document provides information for users requiring register-level descriptions for

developing applications with the Sabertooth (VL-EPMe-51) and Eagle (VL-EPU-5120)

Products.

Related Documents

The following documents available are on the VL-EPMe-51 and VL-EPU-5120 Product

Pages:

 VL-EPMe-51/VL-EPU-5120 Hardware Reference Manual – provides information on

the board’s hardware features including connectors and all interfaces.

 VL-EPMe-51/VL-EPU-5120 BIOS Reference Manual – provides information on the

settings accessible through BIOS Setup.

1

EPMe-51 and VL-EPU-5120 Programmer Reference Manual 2

System Resources

FPGA I/O Space

There are two physical FPGA devices in the Sabertooth and Eagle product design. One

resides on the CPU Board, and the other resides on the I/O Board. Both FPGAs are

mapped into I/O space on the LPC bus. The address range is mapped into a continuous

120 byte I/O window which is broken down between the two FPGA devices in Table 1

below.

 FPGA access: LPC I/O space

 FPGA access size: All 8-bit (byte) accesses (16-bit like registers are aligned on 16-

bit word boundaries to make word access possible in software but the LPC bus still

splits the accesses into two 8-bit accesses)

 FPGA address range: 0x1C80 through 0x1CF7 (a 120-byte window)

Table 1: FPGA I/O Map

Address Range

Device

Size

0xC80 – 0xCBF

CPU Board FPGA registers

64 bytes

0xCC0 – 0xCF7

I/O Board FPGA registers

56 bytes (Note 1)

NOTE: 0xCF8 – 0xCFF (the remainder of the 64 byte I/O space for the I/O FPGA register set) is

reserved for PCI Configuration Registers accesses and will be ignored by the FPGA

Interrupts

The LPC SERIRQ is used for interrupt interface to the Sabertooth and Eagle PCH.

Each of the following devices can have an IRQ interrupt assigned to it and each with an

interrupt enable control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:

CPU Board FPGA Interrupts Available:

 Watchdog timer (one interrupt status bit)

 Temperature Monitor Alert (one interrupt status bit)

 SODIMM Event (one interrupt status bit)

2

System Resources

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 3

I/O Board FPGA Interrupts Available:

 8254 timers (with three interrupt status bits)

 8x GPIOs (with one interrupt status bit per GPIO)

 COM 1 UART (with 16550 interrupt status bits)

 COM 2 UART (with 16550 interrupt status bits)

Common interrupts can be assigned to multiple devices if software can deal with it (this

is common on UARTs being handled by a common ISR).

Interrupt status bits for everything except the UARTs will “stick” and are cleared by a

“write-one” to a status register bit. The 16550 UART interrupts behave as defined for the

16550 registers and are a pass-through to the LPC SERIRQ.

All interrupts in the SERIRQ are high-true so when the slot becomes active, the slot will

be low when there is no interrupt and high when there is an interrupt. Per the FPGA

register descriptions that follow, the CPU Board FPGA and the I/O Board FPGA each

have an independent enable bit that must be set in order for that FPGA’s interrupts to

flow through to the LPC Bus SERIRQ.

EPMe-51 and VL-EPU-5120 Programmer Reference Manual 4

Specialized Functions

Switch Settings

Please reference the Sabertooth and Eagle Hardware Reference Manual for detailed

switch setting information (linked above in Related Documents). Note - there are

mentions of several switch settings in the CPU Board FPGA Register Descriptions.

Secure Erase

The EPMe-51supports Secure Erase, which permanently erases all of the data found on

a drive and does not allow that data to be retrieved. Secure Erase is a function built into

the NVMe drive. The Secure Erase command can be sent from an OS or from the BIOS

menu: Intel Advanced  PCH-FW Configuration  AMT Configuration.

In Linux, common tools used to identify if a drive can be securely erased and erase the

drive are blkid, nvme and hdparm.

Data At Rest

The EPMe-51 NVMe supports secure Data At Rest using Self-Encrypting Drive (SED)

functions, which leaves the data in an encrypted state while the system is powered off.

The data is unencrypted only when power is applied and a password is provided. TCG

Opal compliance allows the encryption and password processing functions to be

contained within the NVMe device.

To enable the NVMe password, see the Opal Security Status section in the BIOS

Security tab. The user will be prompted for this password every time the system powers

on. To remove the password, set a new empty (zero length) password.

WARNING: After a valid password is entered, the drive will remain unencrypted while system

power is applied, which includes warm reboots and S3 sleep states.

3

Specialized Functions

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 5

Bifurcation Usage (for Sabertooth x16 PCIe)

The EPMe-51 (not available on the EPU-5120) provides a PCIe/104 Type 1 Stack-Down

connector on its I/O Board. This connector makes use of the Coffee Lake H CPU PEG

port to implement the x16 PCIe interface that allows for use of a PCIe/104 GPU or other

higher bandwidth peripheral cards in a stack-down application. This section explains

usage details of this interface since the bifurcation hardware straps can be modified by

the CPU Board FPGA, but also note there are BIOS Settings available that should be

used to configure these processor strap settings rather than using direct writes to the

FPGA. Please refer to the Sabertooth BIOS Reference Manual for details on how to

access the Bifurcation settings.

The Bifurcation and Lane Reversal settings for the x16 PCIe interface are described in

the CPUSTRAPS Register for the CPU Board FPGA below, but here is a supplemental

summary of how this works:

 By default, x16 Bifurcation with PCIe Lane Reversal disabled is assigned via the

CPU straps. Any x16 PCIe/104 peripheral will work with Type 1 hosts only and

must be stack-down compatible for use with Sabertooth. The peripheral should

be available to the system from the first power up unless specific drivers are

required. The default setting will also work with any lane width requirement for

the PCIe/104 peripheral (x16, x8, x4, x2, x1), but it will consume the entire x16

lanes for the implementation and simply power down the lanes which are not

needed for the link.

If there is a desire to use 2 x8 PCIe links or 2 x4 PCIe links bifurcation instead (allowing

for use of two stacked x8 and/or x4 PCIe/104 peripherals), there are a few more

considerations involved:

 The first power up will only allow the system access to the peripheral allocated as

“PCI Slot 1” which with PCIe Lane Reversal disabled would be the second board

below the Sabertooth added to the stack because PCIe/104 stack-down rules

allocate the eight higher order PCIe lanes first and then shift the eight lower order

“unused lanes” to the next board in the stack. In order to see the first board

below the Sabertooth added to the stack with this bifurcation setting (which gets

allocated as “PCI Slot 2”) you would have to perform a reboot (reset) of the

system (making sure the main power input does not get cycled to the Sabertooth

or the PCIe/104 stack).

 Enabling PCIe Lane Reversal will change the order of the PCI Slot allocations

(so PCI Slot 1 is the first board down and PCI Slot 2 is the second), but this

enable also reverses the numbering assignment of the lanes to the link so the

PCIe/104 peripherals used would have to support PCIe Lane Reversal as well.

Specialized Functions

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 6

 Note that if the desire is to use a single x8 (or less) PCIe linked peripheral so that

the second x8 PCIe link can remain accessible in the future, then you will need to

Enable PCIe Lane Reversal as well in order for the EPMe-51 bifurcation to see

the peripheral in PCI Slot 1. This is because if there is nothing in PCI Slot 1 then

PCI Slot 2 is not accessible.

There is a bifurcation setting implemented to use 1 x8 and 2 x4 PCIe links available with

the Coffee Lake H processor PEG port, but it has not been fully validated since there are

not any PCIe/104 peripheral cards that support that scenario of use (the specification

only supports 2 x8 or 2 x4 bifurcation).

BIOS Auto-Failover

This feature is currently non-functional.

Currently as designed, if the Primary BIOS fails to successfully complete its boot cycle

within approximately 3 minutes, the controls will switch to the Secondary BIOS device

but the board cannot actually reboot and approximately 3 minutes later the CPU board

Yellow LED will start flashing an error condition indicating a boot failure.

EPMe-51 and VL-EPU-5120 Programmer Reference Manual 7

FPGA Registers

This chapter describes the registers in each of the FPGAs.

 Tables 2 and 3 (beginning on the following page) lists the FPGA registers for the

CPU Board (Table 2) and the I/O Board (Table 3)

 Table 4 (refer to page 11) through Table 47 provide bit-level information on the

individual FPGA registers

CPU and I/O FPGA Register Access Key

CPU and I/O FPGA Register Access Key (tables 2-3)

R/W

Read/Write

RO

Read-only (status or reserved)

R/WC

Read-status/Write-1-to-Clear

RSVD

Reserved. Only write 0 to this bit; ignore all read values.

CPU and I/O Reset Status Key

CPU and I/O FPGA Reset Status Key (tables 2-3)

POR

Power-on reset (only resets one time when input power comes on)

Platform

Resets prior to the processor entering the S0 power state (that is, at power-on and in sleep

states)

POR/Platform

Some of the bits in the register are controlled by Power-on reset, and some are controlled

by Platform reset (see individual bit descriptions).

ResetSX

If AUX_PSEN is a '0' in MISCSR1 (default setting), then this is the same as the Platform

reset.

If AUX_PSEN is a programmed to a '1', then it is the same as the Power-On Reset (POR).

n/a

Reset doesn't apply to status or reserved registers

4

FPGA Registers

EPMe-51 and VL-EPU-5120 Programmer Reference Manual 8

CPU Board FPGA Register Map

Table 2: CPU Board FPGA Register Map

Description

I/O

Address

Offset

Reset

D7

D6

D5

D4

D3

D2

D1

D0

PCR

CC0

0

Platform

PLED

PRODUCT_CODE

PSR

CC1

1

n/a

REV_LEVEL

EXTEMP

CUSTOM

BETA

SCR

CC2

2

Platform

0

LED_DEBUG

WORKVER

0

TICR

CC3

3

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

0

IMASK_TC5

IMASK_TC4

IMASK_TC3

TISR

CC4

4

Platform

INTRTEST

TMRTEST

TMRIN4

TMRIN3

0

ISTAT_TC5

ISTAT_TC4

ISTAT_TC3

TCR

CC5

5

Platform

TIM5GATE

TIM4GATE

TIM3GATE

TM45MODE

TM4CLKSEL

TM3CLKSEL

TMROCTST

0

Reserved

CC6-CCD

6-D

n/a

0

SPIMISC

CCE

E

Platform

0

SERIRQEN

0

Reserved

CCF

F

n/a

0

MISCSR1

CD0

10

POR

0

AUX_PSEN

MISCSR2

CD1

11

POR

0

PC104E_OC

PC104E_STK2

PC104E_STK1

PC104E_STK0

MISCSR3

CD2

12

POR

USB2_OC23

USB2_OC01

USB3_OC1

USB3_OC0

USB2_EN23

USB2_EN01

USB3_EN1

USB3_EN0

MISCSR4

CD3

13

POR

PWROK_S0

PWROK_SBY

PC104EPWR1

PC104EPWR0

ENPC104E

NO3VPWR

NO12VPWR

RSTPC104E

Reserved

CD4-CDB

14-1B

n/a

0

8254 Timers

Address 0

CDC

1C

Platform

msb

<============>

lsb

8254 Timers

Address 1

CDD

1D

Platform

msb

<============>

lsb

8254 Timers

Address 2

CDE

1E

Platform

msb

<============>

lsb

8254 Timers

Address 3

CDF

1F

Platform

msb

<============>

lsb

Reserved

CE0

20

n/a

0

AUXDIR

CE1

21

resetSX

DIR_GPIO8

DIR_GPIO7

DIR_GPIO6

DIR_GPIO5

DIR_GPIO4

DIR_GPIO3

DIR_GPIO2

DIR_GPIO1

AUXPOL

CE2

22

resetSX

POL_GPIO8

POL_GPIO7

POL_GPIO6

POL_GPIO5

POL_GPIO4

POL_GPIO3

POL_GPIO2

POL_GPIO1

AUXOUT

CE3

23

resetSX

OUT_GPIO8

OUT_GPIO7

OUT_GPIO6

OUT_GPIO5

OUT_GPIO4

OUT_GPIO3

OUT_GPIO2

OUT_GPIO1

AUXIN

CE4

24

n/a

IN_GPIO8

IN_GPIO7

IN_GPIO6

IN_GPIO5

IN_GPIO4

IN_GPIO3

IN_GPIO2

IN_GPIO1

AUXIMASK

CE5

25

Platform

IMASK_GPIO8

IMASK_GPIO7

IMASK_GPIO6

IMASK_GPIO5

IMASK_GPIO4

IMASK_GPIO3

IMASK_GPIO2

IMASK_GPIO1

AUXISTAT

CE6

26

Platform

ISTAT_GPIO8

ISTAT_GPIO7

ISTAT_GPIO6

ISTAT_GPIO5

ISTAT_GPIO4

ISTAT_GPIO3

ISTAT_GPIO2

ISTAT_GPIO1

AUXMODE1

CE7

27

resetSX

MODE_GPIO8

MODE_GPIO7

MODE_GPIO6

MODE_GPIO5

MODE_GPIO4

MODE_GPIO3

MODE_GPIO2

MODE_GPIO1

Reserved

CE8

28

n/a

0

Reserved

CE9

29

n/a

0

XCVRMODE

CEA

2A

Platform

0

COM2_MODE

COM1_MODE

AUXMODE2

CEB

2B

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

0

Reserved

CEC-CF1

2C-31

Platform

0

UART1CR

CF2

32

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

UART1_BASE3

UART1_BASE2

UART1_BASE1

UART1_BASE0

UART2CR

CF3

33

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

UART2_BASE3

UART2_BASE2

UART2_BASE1

UART2_BASE0

Reserved

CF4

34

n/a

0

Reserved

CF5

35

n/a

0

UARTMODE1

CF6

36

Platform

0

UART2_485ADC

UART1_485ADC

0

UART2_EN

UART1_EN

UARTMODE2

CF7

37

Platform

0

FAST_MODE

FPGA Registers

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 9

I/O Board FPGA Register Map

Table 3: I/O Board FPGA Register Map

Description

I/O

Address

Offset

Reset

D7

D6

D5

D4

D3

D2

D1

D0

PCR

C80

0

Platform

PLED

PRODUCT_CODE

PSR

C81

1

n/a

REV_LEVEL

EXTEMP

CUSTOM

BETA

SCR

C82

2

POR /

Platform

BIOS_JMP

BIOS_OR

BIOS_SEL

LED_DEBUG

WORKVER

SW_STATUS2

SW_STATUS1

0

Reserved

C83-C8D

3-D

n/a

0

SPIMISC

C8E

E

Platform

0

SERIRQEN

0

CPUSTRAPS

C8F

F

POR

0

PEG_BIFUR1

PEG_BIFUR0

PEG_REV

EDP_EN

DCI_EN

SEC_DIS

MISCSR1

C90

10

POR

0

FLT_CATERR

FLT_CFP

FLT_VCCSA

FLT_VCCGT

FLT_VCC

MISCSR2

C91

11

POR /

Platform

0

SPI_CNTL_OR

REDUN_BOOT_

EN

SPI_CNTL

BOOT_WDT_EX

P

BOOT_WDT_EN

BOOT_OK

PWR_CYCLE

MISCSR3

C92

12

Platform

0

PBRESET

IOPRESENT

NOPORT80

Reserved

C93-C99

13-19

n/a

0

Description

I/O

Address

Offset

Reset

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

C9A-CA7

1A-27

n/a

0

WDT_CTL

CA8

28

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

WDT_MODE

RESET_EN

WDT_EN

WDT_STAT

WDT_VAL

CA9

29

Platform

msb

<============>

lsb

Reserved

CAA

2A

n/a

0

Reserved

CAB

2B

n/a

0

FANCON

CAC

2C

Platform

0

PWM_PCH

PWM_EN

FAN_INVERT

FAN_OFF

FANPWMDC

CAD

2D

Platform

msb

<============>

lsb

FANTACHLS

CAE

2E

Platform

msb

<============>

lsb

FANTACHMS

CAF

2F

Platform

msb

<============>

lsb

TEMPICR

CB0

30

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

0

IMASK_THERM

IMASK_DDR4

TEMPISTAT

CB1

31

Platform

0

ISTAT_THERM

ISTAT_DDR4

Reserved

CB2-CB8

32-38

n/a

0

Description

I/O

Address

Offset

Reset

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

CB9

39

n/a

0

FANPWMDIV0

CBA

3A

Platform

PWMFRAC7

PWMFRAC6

PWMFRAC5

PWMFRAC4

PWMFRAC3

PWMFRAC2

PWMFRAC1

PWMFRAC0

FANPWMDIV1

CBB

3B

Platform

0

PWMINT3

PWMINT2

PWMINT1

PWMINT0

Reserved

CBC-CBF

3C-3F

n/a

0

FPGA Registers

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 10

Register Access Key

Register Access Key (tables 4-27)

R/W

Read/Write, Platform Reset

R/W

Read/Write, Power-on reset

RO

Read-Only

R/WC

Read-Status/Write-1-to-Clear

WO

Write-Only

ROC

Read-Only and clear-to-0 after reading

Reset Status Key

Reset Status Key (tables 4-27)

POR

Power-on reset (only resets one time when input power comes on)

Platform

Resets prior to the processor entering the S0 power state (i.e., at power-on and in sleep

states)

POR/Platform

Some of these bits are reset by Power-on, some are Platform reset (see Field Key for

color code)

resetSX

If AUX_PSEN is a ‘0’ in MISCSR1 (default setting) then this is the same as the Platform

reset. If AUX_PSEN is a programmed to a '1' then it is the same as the power-on reset

POR.

n/a

Reset doesn't apply to status or reserved registers

RSMRST

Resume Reset (i.e., the main power-on reset for the Processor … which also includes

POR)

FPGA Registers

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 11

CPU Board FPGA Register Descriptions

The CPU Board FPGA Registers accessible via the LPC bus are described in

this section.

PCR – PRODUCT CODE & LED

This is the usual VersaLogic register for the product code and PLED.

RESET: Platform Reset

Table 4 PCR – Product Code & LED

Bits

Identifier

Access

Default

Description

7

PLED

R/W

0

Drives the Yellow LED on the CPU board since the I/O

FPGA drives the actual “PLED” on the CBR-4005.

0 – LED is OFF (LED is off if FPGA is programmed)

1 – LED is ON (LED is on if the FPGA is not

programmed)

Note: Board fault conditions can also drive this Yellow

LED.

6-0

PRODUCT_CODE[6:0]

RO

“0100100”

Product Code for the Sabertooth and Eagle CPU Board

(0x24)

PSR – PRODUCT STATUS

This is the usual VersaLogic register for the board revision and Extended Temperature,

Custom and Beta bits status.

Table 5 PSR – Product Status

Bits

Identifier

Access

Default

Description

7:3

REV_LEVEL[4:0]

RO

N/A

Revision level of the PLD (incremented every FPGA release)

2

EXTEMP

RO

N/A

Extended or Standard Temp Status:

0 – Standard Temp

1 – Extended Temp (always set, no external strap for this

product)

1

CUSTOM

RO

N/A

Custom or Standard Product Status (set in FPGA):

0 – Standard Product

1 – Custom Product or PLD/FPGA

0

BETA

RO

N/A

Beta or Production Status (set in FPGA):

1 – Beta (basically any release prior to Production or during

development)

0 - Production

FPGA Registers

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 12 12

SCR – BIOS AND JUMPER (SWITCH) CONTROL/STATUS REGISTER

This is a “traditional” register in many VL products. On COM products the BIOS selection

was done on the Carrier boards. That function is on the CPU board on this two board

product.

RESET: POR or Platform Reset (see individual bit description default)

The table below summarizes the modes related to BIOS_OR and BIOS_SEL and the

BIOS Configuration Switch SW1 #2. Note that the FPGA must be programmed in order

to power the board on so the configuration switch only goes to the FPGA. (On other

products the switch and FPGA output controls were “wire-AND’d”.)

Table 6 BIOS Selection

BIOS Configuration

Switch Position

(status in BIOS_JMP

Bit 7)

BIOS_OR

(Bit 6)

BIOS_SEL

(Bit 5)

BIOS

Actually

Selected

Comments

“OFF” (‘1’)

‘0’

‘X’

(don’t care)

Primary

Configuration Switch selects the BIOS

(BIOS_SEL ignored)

“ON” (‘0’)

‘0’

‘X’

(don’t care)

Secondary

Configuration Switch selects the BIOS

(BIOS_SEL ignored)

‘X’ (don’t care)

‘1’

Primary

BIOS_SEL selects BIOS

(BIOS_JMP switch ignored)

‘X’ (don’t care)

‘1’

‘0’

Secondary

BIOS_SEL selects BIOS

(BIOS_JMP switch ignored)

Table 7 SCR – BIOS and Jumper (Switch) Control/Status

Bits

Identifier

Access

Default

Description

7

BIOS_JMP

RO

N/A

Status of the external BIOS selection swtich (SW1 #2 discussed in

Section Error! Reference source not found.):

1 – Primary BIOS selected

0 – Secondary BIOS selected

FYI – these are the “traditional” settings which seem backwards but

that’s OK.

6

BIOS_OR

R/W

0

(POR)

BIOS Switch (jumper) Override. Do not set this to ‘1’ if using BIOS

Auto-Failover (see MISCSR2 register). Do not change this setting

until all SPI flash activity is stopped.

0 – BIOS Select will follow the BIOS_JMP switch setting (or BIOS

Auto-Failover if enabled)

1 – BIOS Select will follow the BIOS_SEL register

Note: See Table above for control signal usage. This bit is cleared

with a POR.

FPGA Registers

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 13 13

Bits

Identifier

Access

Default

Description

5

BIOS_SEL

R/W

1

(POR)

BIOS Select (see BIOS_OR):

1 – Primary BIOS selected

0 – Secondary BIOS selected

Note: This bit should be set to the desired BIOS before BIOS_OR

is set to a ‘1’. See Table above for control signal usage. This bit is

set with a POR.

4

LED_DEBUG

R/W

0

Debug LED (controls the Yellow LED):

0 – LED is off and follows its primary function

1 – LED is On

FYI – this is used in some other products to drive a Blue LED.

3

WORKVER

RO

N/A

Status used to indicate that the FPGA is Not Official Released and

is still in a working state. This bit should only be set on the FPGA

developers boards.

0 – FPGA is Released

1 – FPGA is in a Working State (Not Released)

2

SW_STATUS2

RO

N/A

Status of the debug switch Position 2 (SW2 #2 discussed in

Switch Settings):

0 – Switch is Off (Normal Operation)

1 – Switch is On (Disables REDUN_BOOT_EN bit in MISCSR2)

This is RESERVED on older products.

1

SW_STATUS1

RO

N/A

Status of the debug switch Position 1 (SW2 #1 discussed in

Switch Settings):

0 – Switch is Off (Normal Operation)

1 – Switch is On (Debug only – will shut down regulators on-board)

This was often called GPI_JMP on older products.

0

RESERVED

RO

0

Reserved – Writes are ignored. Reads always return 0

SPIMISC – SPI CONTROL REGISTER

This register is only used to set there SERIRQ Enable required for software interrupts

via the LPC bus. The register is left the same as before to be compatible with existing

software.

RESET: Platform Reset

Table 8 SPI – SPI Debug Control Register

Bits

Identifier

Access

Default

Description

7-3

RESERVED

RO

0’s

Reserved – Do not write (may be used for debug). Reads always

return 0

FPGA Registers

VL-EPMe-51 and VL-EPU-5120 Programmer Reference Manual 14 14

Bits

Identifier

Access

Default

Description

2

SERIRQEN

R/W

0

When an IRQ is assigned a slot in the SERIRQ it will drive the slot

with the interrupt state. But, this bit must be set to a ‘1’ to do that.

0 – Slots assigned to SERIRQ are not driven (available for other

devices).

1 – Slots assigned to SERIRQ are driven with their current interrupt

state (which is low since interrupts are high-true)

Note: The reason for this is that default interrupt settings in this FPGA

can conflict with other interrupts if VersaAPI is not being used (e.g.,

console redirect using IRQ3).

1-0

RESERVED

RO

0’s

Reserved – Do not write (may be used for debug). Reads always

return 0

CPUSTRAPS – CPU STRAP CONTROL/STATUS REGISTER

This register is used to set CPU Board straps (i.e. override hardware straps) for the

Processor and PCH. When a change from the default is required, they should be set in

this register and then a Processor/PCH power cycle should be run (the power cycle can

be forced using the PWR_CYCLE bit in MISCSR2). A power cycle is necessary since

straps are either sampled on the resume reset (RSMRST#) de-assertion or on the PCH

power ok (PCH_PWROK) assertion.

All of these drive “open-source” drivers which means if the register value is set to a ‘1’

then the strap is driven High (to a ‘1’ level). But, if the register is set to a ‘0’ then the

output is high-impedance and the default resistor strap is used. Because this register

defaults to 0’s that means the hardware-strap values are setting the mode. This design

sets them all to a “0” level by default as shown, but to default to other values the default

settings in the FPGA can be changed so a power sequence isn’t required to change the

strap values.

RESET: This register is only reset by the main power-on reset (POR) since it must

maintain its state in Sleep modes (e.g. S3). It is not impacted by a processor/PCH

power cycle.

Table 9 CPUSTRAPS – CPU Straps Control/Status Register

Bits

Identifier

Access

Default

Description

7-6

RESERVED

RO

0’s

Reserved – Writes are ignored. Reads always return 0

5-4

PEG_BIFUR[1:0]

R/W

00

Processor Strap: For PCI Express* Bifurcation.

00 = 1 x16 PCIe  hardware strap setting

01 = 2 x8 PCIe (this setting also supports 2 x4 bifurcation)

1X = 1 x8 and 2 x4 PCIe (this bifurcation has not been fully

validated)

See “Bifurcation Usage” in this document for more information.

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