Silicon Labs RS9113 Family Module User guide

Silicon Labs
Brand
Silicon Labs
Model
RS9113 Family Module
Type
User guide
Page 1
RS9113 Module Family
Module Integration Guide
Version 2.10
December 2017
Page 2
RS9113 Module Family
Module Integration Guide
Version 2.10
About this Document
The RS9113 module is a Wi-Fi, Bluetooth and ZigBee combo module. It is a dual-band 802.11n single-
stream module with built-in MAC/BBP, RF and PA, and front-end components. It supports Bluetooth 2.1
EDR and 4.0. It interfaces to a host processor through SDIO, SPI, UART or USB interfaces. This document
provides information that may be used while integrating the module into a hardware system.
This document includes RS9113 reference schematics for integrating with host processors over multiple
interfaces and the corresponding circuitry, along with the BoM.
Page 3
RS9113 Module Family
Module Integration Guide
Version 2.10
Table of Contents
1 Introduction ......................................................................................................... 5
1.1 Host Interface Selection ............................................................................................5
1.2 Power Supply ...........................................................................................................5
1.3 Quick Links ...............................................................................................................5
2 RS9113 Module with Integrated Antenna .............................................................. 7
2.1 Block Diagram ..........................................................................................................7
2.2 Reference Schematics and BoM ................................................................................7
2.2.1 Reference Schematics ............................................................................................................. 7
2.2.2 Bill of Materials ..................................................................................................................... 10
2.3 Recommended PCB Landing Pattern ....................................................................... 13
2.4 Circuit and Layout Guidelines .................................................................................. 13
2.5 u.FL Connector for External Antenna ....................................................................... 17
3 RS9113 Module without Integrated Antenna ...................................................... 19
3.1 Block Diagram ........................................................................................................ 19
3.2 Reference Schematics and BoM .............................................................................. 19
3.2.1 Reference Schematics ........................................................................................................... 19
3.2.2 Bill of Materials ..................................................................................................................... 22
3.3 Recommended PCB Landing Pattern ....................................................................... 26
3.4 Circuit Layout and Guidelines .................................................................................. 26
3.5 Antenna Layout Guidelines ..................................................................................... 29
Table of Figures
Figure 1: RS9113 Module with Integrated Antenna .................................................................................. 7
Figure 2: Reference Schematics for RS9113 Module with Integrated Antenna – Page 1 ........................... 8
Figure 3: Reference Schematics for RS9113 Module with Integrated Antenna – Page 2 ........................... 9
Figure 4: Recommended PCB Landing Pattern for RS9113 Module with Integrated Antenna ................. 13
Figure 5: PCB Antenna Guidelines .......................................................................................................... 14
Figure 6: Spacing between USB_DP and USB_DN ................................................................................... 16
Figure 7: Spacing for Low-speed and High-speed signals around USB_DP/USB_DN ............................... 16
Figure 8: USB Signals and the Ground Plane ........................................................................................... 17
Figure 9: u.FL Connector (Part No: Hirose U.FL-R-SMT (01)) ................................................................... 17
Figure 10: External Antenna ................................................................................................................... 18
Figure 11: RS9113 Module without Integrated Antenna ........................................................................ 19
Figure 12: Reference Schematics for RS9113 Module without Integrated Antenna – Page 1 .................. 20
Figure 13: Reference Schematics for RS9113 Module without Integrated Antenna – Page 2 .................. 21
Figure 14: Recommended PCB Landing Pattern for RS9113 Module without Integrated Antenna ......... 26
Figure 15: Spacing between USB_DP and USB_DN ................................................................................. 28
Figure 16: Spacing for Low-speed and High-speed signals around USB_DP/USB_DN ............................. 28
Figure 17: USB Signals and the Ground Plane ......................................................................................... 29
Figure 18: Chip Antenna Layout Recommendations ............................................................................... 30
Table of Tables
Table 1: Host Interface Selection .............................................................................................................. 5
Table 2: Bill of Materials for RS9113 Module with Integrated Antenna .................................................. 12
Page 4
RS9113 Module Family
Module Integration Guide
Version 2.10
Page 5
RS9113 Module Family
Module Integration Guide
Version 2.10
1 Introduction
The RS9113 n-Link®, WiSeConnect® module families are based on Silicon Labs' RS9113 ultra-
low-power, single spatial stream, dual-band 802.11n + BT4.0 + ZigBee Convergence SoC.
The RS9113 module integrates a multi-threaded MAC processor with integrated analog
peripherals and support for digital peripherals, baseband digital signal processor, analog
front-end, crystal oscillator, calibration OTP memory, dual-band RF transceiver, dual-band
high-power amplifiers, baluns, diplexers, diversity switch and Quad-SPI Flash thus providing
a fully-integrated solution for embedded wireless applications.
From a hardware perspective, the modules come in two variants – with an integrated
antenna and without an integrated antenna. The subsequent sections explain the
requirements for integrating these modules with a Host processor using different
interfaces.
1.1 Host Interface Selection
The table below shows the requirement of pull-down resistors on HOST_SEL_0,
HOST_SEL_1 and BOOTMODE_0 signals to select the interface to the Host processor.
NOTE: The interfaces supported by n-Link® modules’ software are USB and SDIO. The
interfaces supported by WiSeConnect® modules’ software are SPI, UART, USB and USB-CDC.
Interface
HOST_SEL_1
HOST_SEL_0
BOOTMODE_0
SDIO
Leave unconnected
Leave unconnected
Leave unconnected
SPI
Leave unconnected
Connect 4.7kOhms pull-
down resistor
Leave unconnected
USB
Connect 4.7kOhms pull-
down resistor
Leave unconnected
Connect 4.7kOhms pull-
down resistor
USB-CDC
Connect 4.7kOhms pull-
down resistor
Leave unconnected
Leave unconnected
UART
Connect 4.7kOhms pull-
down resistor
Connect 4.7kOhms pull-
down resistor
Leave unconnected
Table 1: Host Interface Selection
1.2 Power Supply
It is recommended to have a tightly regulated power supply which is 3.3V +/- 10% and can
handle a continuous current of 500mA. As a general practice it is always suggested to have
a 30% buffer on the current rating of the power supply.
1.3 Quick Links
Click on one of the links below to proceed to the corresponding section.
1) Module with Integrated Antenna
a. Reference Schematics
b. Bill of Materials
c. Recommended PCB Landing Pattern
d. Circuit and Layout Guidelines
2) Module without Integrated Antenna
Page 6
RS9113 Module Family
Module Integration Guide
Version 2.10
a. Reference Schematics
b. Bill of Materials
c. Recommended PCB Landing Pattern
d. Circuit and Layout Guidelines
Page 7
RS9113 Module Family
Module Integration Guide
Version 2.10
2 RS9113 Module with Integrated Antenna
In the following sections, we present reference schematics, BoM, Recommended PCB
Landing Pattern, Circuit and Layout Guidelines for the RS9113 Module with integrated PCB
antenna. The schematics are shown for SDIO, SPI, UART, USB and USB-CDC host interface
options.
2.1 Block Diagram
Figure 1: RS9113 Module with Integrated Antenna
2.2 Reference Schematics and BoM
2.2.1 Reference Schematics
Page 8
RS9113 Module Family
Module Integration Guide
Version 2.10
Figure 2:Reference Schematics for RS9113 Module with Integrated Antenna – Page 1
R13
100K
D3
TP2
TP1
DBG_UART_TX
NOTE: TP2 is
required for
debug purposes
only.
NOTE: TP1 is
required for
debug purposes
only.
VINMOD_22
U4
Max8902B
OUT
8
BYP
7
FB
6
GS
4
GND
2
EP
9
POK
5
EN
3
IN
1
VINMOD_22
R9
10K
HOST_BB_EN
R14
10K
Title
Size Document Number Rev
Date: Sheet of
RS9113 based Module with Integrated Antenna
1 2Monday, June 15, 2015
Rev1.0
C6
0.01uF
R10
120K
R12
56K
FB1
BEAD C1
2.2uF
C2
0.1uF
C8
4.7pF
ANA33
OPTION 1: Connect to VINMOD (all versions of the Module)
VINMOD ANA33
OPTION 2: Generate 1.9V from VINMOD and connect to ANA33 (from
Version 3.0 onwards)
GPIO_21
GPIO_2
U1A
RS9113 Module with
VIN_MOD
33
SDIO_VDD_18_33
19
GPIO_2
26
GPIO_7
23
GPIO_8
29
GPIO_13
49
GPIO_14
8
GPIO_15
24
GPIO_16
25
GPIO_17
28
GPIO_18
30
GPIO_19
32
GPIO_21
31
ANA33
34
VBATT
52
WURX
1
HOST_BB_EN
39
ULP_GPIO_0
2
JP0
47
JNC
46
JP2
45
JP1
48
BOOTLOAD_EN
27
AUX_DAC_OUT
38
RESET_N
51
ULP_ANAGPI
50
AUX_ADC_IN0
44
XTAL_32KHZ_P
3
XTAL_32KHZ_N
4
GND
75
GND
76
GND
77
GND
78
GND
79
GND
53
GND
54
GND
55
GND
56
GND
57
GND
58
GND
59
GND
60
GND
61
GND
62
GND
63
GND
64
GND
65
GND
66
GND
67
GND
68
GND
69
GND
70
GND
71
GND
72
GND
73
GND
74
U2
HOST MCU
C7
10uF
NOTE: Please refer to the
Datasheet for details on how to
connect the GPIOs for different
funtions
GPIO_15 ULP_GPIO_0
GPIO Options
GPIO_2
R1
100K
VINMOD
R2
100K
NOTES:
1) These connections of GPIOs are needed only for Low Power modes. All or some of them may be left
unconnected based on the Low Power mode usage.
2) Choose between R1 and R2 based on whether GPIO_2 is active-low or active-high in Low Power
mode.
3) Please refer to the Datasheet for more details.
GPIO_21
R3
100K
NOTE:
From Module Version 3.0 onwards, ANA33 may be connected to VINMOD (3.3V) through a supply filter or
to a lower supply source down to 1.9V. An example circuit to generate ANA33 is given below. Connecting
ANA33 to the lower voltage results in lesser power consumption, with no difference in performance of
the module.
FOR MODULE VERSIONS 2.0 AND EARLIER, PLEASE CONNECT VINMOD (3.3V) TO ANA33.
ANA33 Options
U3
XC9236F08DER-G
LX
1
VOUT
3
VSS
5
VSS
2
VIN
6
CE
4
VINMOD
C3
10uF
GPIO_15
R4 4.7K
HOST_BB_EN
L1
4.7uH
R7
300K
VIN_33
R8
187K
RESET_N
OPTION-1
C10
0.1uF
RESET_N
C11
8.2nF
R11 1M
R16
100K
U5
MAX6415
VCC
5
SRT
4
RESETn
1
GND
2
RESET IN
3
R15 402K
C9
0.1uF
OPTION-2
SW1
1 2
RESET Circuitry
VIN_33
VIN_33
RESET_N
R5 4.7K
C4
150pF
R6 4.7K
C5
10uF
Integrated Antenna
VINMOD
ANA33
HOST_BB_EN
ULP_GPIO_0
MCU pin
driving
RESET_N
Host MCU may directly drive the RESET_N pin of
the module as shown below.
OPTION-3
Note: Ensure a reset assertion time of 20ms.
HOST MCU
RESET_N
Page 9
RS9113 Module Family
Module Integration Guide
Version 2.10
Figure 3: Reference Schematics for RS9113 Module with Integrated Antenna – Page 2
C13
10uF
USB_VBUS
R23 1M
VINMOD
NOTE: R18** value should be
adjusted based on driver output
impedance and PCB Trace
Impedance,,(33E is Nominal)
U7
TPS63001
L1
4
L2
2
VIN
5
VINA
8
PS/SYNC
7
GND
9
PGND
3
FB
10
VOUT
1
EN
6
EP
11
C14
4.7nF 250V
USB_VBUS
SDIO_D0
SDIO_CLK
SDIO_CMD
SDIO_D3
SDIO_D2
SDIO_D1
L2
2.2uH
NOTE: R19** value should be
adjusted based on driver output
impedance and PCB Trace
Impedance,,(33E is Nominal)
SPI_MOSI
SPI_INTR
SPI_MISO
SPI_CLK
SPI_CS
SPI Mode
VIN_33
R20 4.7K
USB 5V to 3.3V Conversion
(only for USB & USB-CDC)
D1
0603ESDA
Power Supply Filter Section
D2
0603ESDA
C18
10uF
VIN_33
U1B
RS9113 Module with Integrated Antenna
VOUTLDOP1
37
VOUTLDOP3
40
USB_VBUS
9
USB_DP
11
USB_DN
10
USB_ID
12
USB_VDDS
22
USB_VDDD
42
USB_VDDP
21
USB_VDDA
43
GPIO_9
6
GPIO_10
5
GPIO_11
7
GPIO_12
41
SDIO_DATA0
13
SDIO_DATA1
14
SDIO_DATA2
16
SDIO_DATA3
15
SDIO_CMD
17
SDIO_CLK
18
HOST_SEL_0
36
HOST_SEL_1
35
BOOT_MODE_0
20
NOTE:
VIN_33 is the 3.3V supply from in
the System PCB. It may be derived
using a DC-DC as shown on the
left. If a DC-DC is used, C19 has to
be placed close to the DC-DC.
U1B
RS9113 Module with Integrated Antenna
VOUTLDOP1
37
VOUTLDOP3
40
USB_VBUS
9
USB_DP
11
USB_DN
10
USB_ID
12
USB_VDDS
22
USB_VDDD
42
USB_VDDP
21
USB_VDDA
43
GPIO_9
6
GPIO_10
5
GPIO_11
7
GPIO_12
41
SDIO_DATA0
13
SDIO_DATA1
14
SDIO_DATA2
16
SDIO_DATA3
15
SDIO_CMD
17
SDIO_CLK
18
HOST_SEL_0
36
HOST_SEL_1
35
BOOT_MODE_0
20
U1B
RS9113 Module with Integrated Antenna
VOUTLDOP1
37
VOUTLDOP3
40
USB_VBUS
9
USB_DP
11
USB_DN
10
USB_ID
12
USB_VDDS
22
USB_VDDD
42
USB_VDDP
21
USB_VDDA
43
GPIO_9
6
GPIO_10
5
GPIO_11
7
GPIO_12
41
SDIO_DATA0
13
SDIO_DATA1
14
SDIO_DATA2
16
SDIO_DATA3
15
SDIO_CMD
17
SDIO_CLK
18
HOST_SEL_0
36
HOST_SEL_1
35
BOOT_MODE_0
20
C19
10uF
U1B
RS9113 Module with Integrated Antenna
VOUTLDOP1
37
VOUTLDOP3
40
USB_VBUS
9
USB_DP
11
USB_DN
10
USB_ID
12
USB_VDDS
22
USB_VDDD
42
USB_VDDP
21
USB_VDDA
43
GPIO_9
6
GPIO_10
5
GPIO_11
7
GPIO_12
41
SDIO_DATA0
13
SDIO_DATA1
14
SDIO_DATA2
16
SDIO_DATA3
15
SDIO_CMD
17
SDIO_CLK
18
HOST_SEL_0
36
HOST_SEL_1
35
BOOT_MODE_0
20
U6
FDC6329L
R1,C1
6
VIN
4
VON/OFF
5
VOUT
2
VOUT
3
R2
1
U1B
RS9113 Module with Integrated Antenna
VOUTLDOP1
37
VOUTLDOP3
40
USB_VBUS
9
USB_DP
11
USB_DN
10
USB_ID
12
USB_VDDS
22
USB_VDDD
42
USB_VDDP
21
USB_VDDA
43
GPIO_9
6
GPIO_10
5
GPIO_11
7
GPIO_12
41
SDIO_DATA0
13
SDIO_DATA1
14
SDIO_DATA2
16
SDIO_DATA3
15
SDIO_CMD
17
SDIO_CLK
18
HOST_SEL_0
36
HOST_SEL_1
35
BOOT_MODE_0
20
HOST_BB_EN
R27
20K
C15 1nF
R28
2K
UART_RX
UART_TX
UART_RTS
UART_CTS
UART Mode
VOUTLDOP1
VINMOD
USB_DN
USB_DP
USB_VBUS
VOUTLDOP3
VOUTLDOP1
USB_ANA3V3
VOUTLDOP3
USB_ID
C16
10uF
FB2
BEAD
C17
10uF
USB Mode
NOTE: Pull up resistors should
be present on SDIO CMD & SDIO
Data lines according to the
section 6.6.5 of SD physical
layer specification, version 2.00
Title
Size Document Number Rev
Date: Sheet of
RS9113 based Module with Integrated Antenna
2 2Monday, June 15, 2015
VINMOD
USB_DN
USB_DP
USB_VBUS
VOUTLDOP1
USB_ANA3V3
VOUTLDOP3
VOUTLDOP1
VOUTLDOP3
USB-CDC Mode
R18 33E
FB3
BEAD
C20
2.2uF
C21
0.1uF
R19 33E
USB_ANA3V3
Rev1.0
R17
51K
NOTE:
The section for USB_ANA3V3
is required only in the case of
USB and USB-CDC.
USB Connector
(for USB and USB-CDC Modes)
R21 4.7K
J1
USBminiB
VBUS
1
D-
2
D+
3
ID
4
GND
5
SDIO Mode
R22 4.7K
R24 4.7K
R26 4.7K
R25 4.7K
NOTE:
The FDC6329L Load Switch shown here is
required for the Low Power modes of the
module.
C12
0.1uF
USB_ID
USB_DP
USB_DN
USB_ID
Page 10
RS9113 Module Family
Module Integration Guide
Version 2.10
2.2.2 Bill of Materials
S.No.
Quantity
Value
Description
Reference Schematics Section
JEDEC
Manufacturer
Part Number
1.
3
4.7K
CHIP RES 4K7 5% 200PPM 0402 1/10W
Core
0402
Panasonic
ERJ-2GEJ472X
2.
1
RS9113
RS9113 Module with Integrated Antenna
Core
Silicon Labs, Inc.
RS9113-XXX-X1X
3.
3
100K
CHIP RES 100K 5% 200PPM 0402 1/10W
GPIO Options
0402
Panasonic
ERJ-2GEJ104X
4.
1
2.2uF
CER CHIP C 2.2U 20% X5R 0402 4V
ANA33 Option – 1
0402
Murata
GRM155R60G225ME15D
5.
1
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
ANA33 Option – 1
0402
Murata
GRM155R61A104KA01D
6.
1
BEAD
FILTER CHIP 120 OHM 1.5A 0402
ANA33 Option – 1
0402
Murata
BLM15EG121SN1D
7.
3
10uF
CER CHIP C 10U 20% X5R 0805 10V
ANA33 Option – 2
0805
Murata
GRM21BR61A106KE19L
8.
1
150pF
CAP CER 150PF 25V 10% X7R
ANA33 Option – 2
0201
Murata
GRM033R71E151KA01D
9.
1
0.01uF
CAP CER 10000PF 10V 10% X5R
ANA33 Option – 2
0201
Murata
GRM033R61A103KA01D
10.
1
4.7pF
CAP CER 4.7PF 50V NP0
ANA33 Option – 2
0201
Murata
GRM0335C1H4R7CA01D
11.
1
4.7uH
Power Inductor
ANA33 Option – 2
SMD
FDK
MIPF2520D4R7
12.
1
300K
RES SMD 300K OHM 5% 1/20W
ANA33 Option – 2
0201
Panasonic
ERJ-1GEJ304C
13.
1
187K
RES SMD 187K OHM 1% 1/20W
ANA33 Option – 2
0201
Panasonic
ERJ-1GEF1873C
14.
1
10K
CHIP RES 10K 5% 200PPM 0402 1/10W
ANA33 Option – 2
0402
Panasonic
ERJ-2GEJ103X
15.
1
120K
RES SMD 120K OHM 5% 1/20W
ANA33 Option – 2
0201
Panasonic
ERJ-1GEJ124C
16.
1
56K
RES SMD 56K OHM 5% 1/20W
ANA33 Option – 2
0201
Panasonic
ERJ-1GEJ563C
17.
1
DC-DC
DC-DC convertor
ANA33 Option – 2
UPSC-6
Torex
XC9236F08DER-G
18.
1
LDO
LDO
ANA33 Option – 2
TDFN-8
Maxim
MAX8902B
19.
1
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
Reset – Option 1
0402
Murata
GRM155R61A104KA01D
20.
1
100K
CHIP RES 100K 5% 200PPM 0402 1/10W
Reset – Option 1
0402
Panasonic
ERJ-2GEJ104X
21.
1
-
DIODE SML SIG 100V 0.2A
Reset – Option 1
SOT-23
Fairchild
Semiconductor
MMBD1202
Page 11
RS9113 Module Family
Module Integration Guide
Version 2.10
S.No.
Quantity
Value
Description
Reference Schematics Section
JEDEC
Manufacturer
Part Number
22.
1
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
Reset – Option 2
0402
Murata
GRM155R61A104KA01D
23.
1
8.2nF
CAP CER 8200PF 10V 10% X5R
Reset – Option 2
0201
AVX
0201ZD822KAT2A
24.
1
1M
CHIP RES 1M 5% 200PPM 0402 1/10W
Reset – Option 2
0402
Panasonic
ERJ-2GEJ105X
25.
1
402K
RES SMD 402K OHM 1% 1/10W 0402
Reset – Option 2
0402
Panasonic
ERJ-2RKF4023X
26.
1
100K
CHIP RES 100K 5% 200PPM 0402 1/10W
Reset – Option 2
0402
Panasonic
ERJ-2GEJ104X
27.
1
SW
SWITCH TACTILE SPST-NO 0.02A 15V
Reset – Option 2
SMD
ALPS
SKRAAKE010
28.
1
Reset IC
IC MPU/Reset circuit
Reset – Option 2
SOT23-5
Maxim
MAX6415UK-T
29.
1
10K
CHIP RES 10K 5% 200PPM 0402 1/10W
Reset – Option 3
0402
Panasonic
ERJ-2GEJ103X
30.
1
33E
CHIP RES 33R 5% 200PPM 0402 1/10W
SDIO Mode
0402
Panasonic
ERJ-2GEJ330X
31.
1
33E
CHIP RES 33R 5% 200PPM 0402 1/10W
SPI Mode
0402
Panasonic
ERJ-2GEJ330X
32.
1
4.7K
CHIP RES 4K7 5% 200PPM 0402 1/10W
SPI Mode
0402
Panasonic
ERJ-2GEJ472X
33.
1
51K
CHIP RES 51K 5% 200PPM 0402 1/10W
UART Mode
0402
Panasonic
ERJ-2GEJ513X
34.
2
4.7K
CHIP RES 4K7 5% 200PPM 0402 1/10W
UART Mode
0402
Panasonic
ERJ-2GEJ472X
35.
2
4.7K
CHIP RES 4K7 5% 200PPM 0402 1/10W
USB Mode
0402
Panasonic
ERJ-2GEJ472X
36.
1
4.7K
CHIP RES 4K7 5% 200PPM 0402 1/10W
USB-CDC Mode
0402
Panasonic
ERJ-2GEJ472X
37.
1
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
USB Connector
0402
Murata
GRM155R61A104KA01D
38.
1
10uF
CER CHIP C 10U 20% X5R 0805 10V
USB Connector
0805
Murata
GRM21BR61A106KE19L
39.
1
4.7nF
250V
CAP CER 4700PF 100V 10% X7R 0805
USB Connector
0805
Murata
GRM219R72A472KA01D
40.
2
0603ESDA
ESD Suppressor
USB Connector
0603
CooperBussmann
0603ESDA-MLP
41.
1
USB –
micro AB
CONN RCPT STD MICRO USB TYPE AB
USB Connector
SMD
FCI
10104111-0001LF
42.
1
1M
CHIP RES 1M 5% 200PPM 0402 1/10W
USB Connector
0402
Panasonic
ERJ-2GEJ105X
Page 12
RS9113 Module Family
Module Integration Guide
Version 2.10
S.No.
Quantity
Value
Description
Reference Schematics Section
JEDEC
Manufacturer
Part Number
43.
1
10uF
CER CHIP C 10U 20% X5R 0805 10V
USB 5V to 3.3V Conversion
0805
Murata
GRM21BR61A106KE19L
44.
1
2.2uH
Power Inductor
USB 5V to 3.3V Conversion
1212
Murata
LQH3NPN2R2NG0L
45.
1
DC-DC
DC-DC Convertor
USB 5V to 3.3V Conversion
TI
TPS63001
46.
1
1nF
CAP CER 1nF 6.3V X5R 0201
Power Supply Filter Section
0201
Murata
GRM033R60J102KA01D
47.
3
10uF
CER CHIP C 10U 20% X5R 0805 10V
Power Supply Filter Section
0805
Murata
GRM21BR61A106KE19L
48.
1
2.2uF
CER CHIP C 2.2U 20% X5R 0402 4V
Power Supply Filter Section
0402
Murata
GRM155R60G225ME15D
49.
1
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
Power Supply Filter Section
0402
Murata
GRM155R61A104KA01D
50.
2
BEAD
FILTER CHIP 120 OHM 1.5A 0402
Power Supply Filter Section
0402
Murata
BLM15EG121SN1D
51.
1
20K
RES 20K OHM 1/20W 5% 0201 SMD
Power Supply Filter Section
0201
Panasonic
ERJ-1GEJ203C
52.
1
2K
RES 2K OHM 1/20W 5% 0201 SMD
Power Supply Filter Section
0201
Panasonic
ERJ-1GEJ202C
53.
1
Load
Switch
IC LOAD SWITCH INT 8VIN
Power Supply Filter Section
SSOT-6
Fairchild
FDC6329L
Table 2: Bill of Materials for RS9113 Module with Integrated Antenna
Page 13
RS9113 Module Family
Module Integration Guide
Version 2.10
2.3 Recommended PCB Landing Pattern
The figure below illustrates the recommended landing pattern for the module.
Figure 4: Recommended PCB Landing Pattern for RS9113 Module with Integrated Antenna
2.4 Circuit and Layout Guidelines
The following guidelines outline the integration of the RS9113 module without antenna.
Page 14
RS9113 Module Family
Module Integration Guide
Version 2.10
1) The module has 27 Ground pads, with two different sizes as mentioned below. Note
that all ground pads are present around the center of the module on the bottom side.
a. Provide one ground copper pad of size 3.60mm x 3.60mm and 26 ground
copper pads of size 1.4mm x 1.4 mm on the top side of the PCB. Make sure to
open the solder mask in this area so that the Cu is exposed.
b. Provide one ground copper pad of size 3.60mm x 3.60mm or higher on the
bottom side of the PCBand keep open the solder mask in this area so that the
Cu is exposed.
c. The RF ground pad (pin number 53) should have 16 Vias, each of which should
have a pad size of 24mil in diameter and a 16mil drill.
2) There should be no metal planes or traces in the region under the PCB antenna and
beside it for at least 3 mm. The module should be placed such that the antenna portion
is on the edge of the PCB. The figure below may be used as a reference.
Figure 5: PCB Antenna Guidelines
3) Refer to the Datasheet for details on how to connect GPIOs for different functions.
4) GPIO_2, GPIO_15, GPIO_21 and ULP_GPIO_0 are used for communicating with the
Host Processor in Low Power modes of the module. The datasheet has more details
regarding the same.
5) In the SDIO mode, pull-up resistors should be present on SDIO_CMD & SDIO Data lines
asper the SDIO physical layer specification, version 2.00.
Page 15
RS9113 Module Family
Module Integration Guide
Version 2.10
6) Ensurethat the following input signals are not floating when the module is powered up
and reset is deasserted. This can be done by ensuring that the Host processor
configures its signals (outputs) before deasserting the reset.
a. SPI Mode: SPI_CS and SPI_CLK
b. UART Mode: UART_RX and UART_CTS
7) SPI_INTR is the interrupt signal driven by the module. This signal may be configured as
Active-high (default mode) or Active-low. If it is active-high, an external pull-down
resistor may be required. If it is active-low, an external pull-up resistor may be
required. This resistor can be avoided if the following actions are carried out in the
Host processor:
a. To use the signal in the Active-high mode (which is the default mode), ensure
that, during the power up of the module, the module’s reset is asserted and
then deasserted as per the requirements of the reset signal.
b. To use the signal in the Active-low mode, during power up of the module,
mask the interrupt in the Host processor, program the interrupt mode to
active-low in the module and then unmask the interrupt in the Host processor.
8) Signal Integrity Guidelines for SPI/SDIO interface: Glitches in the SPI/SDIO clock can
potentially take the SPI/SDIO interface out of synchronization. The quality and integrity
of the clock line needs to be maintained. It is recommended to avoid using cables to
connect the Host processor with the module’s SPI/SDIO interface. In case a cable is
used for board to board connection, the following steps are recommended (please
note that this is not an exhaustive list of guidelines and depending on individual cases
additional steps may be needed.)
a. Minimize the length of the SPI/SDIO bus cable to as small as possible,
preferably to within an inch or two.
b. Increase the number of ground connections between the module PCB and the
Host processor PCB.
9) Module Version 3.0 onward, ANA33 may be connected to VINMOD (3.3V) directly or to
a lower supply source, down to 1.9V. Connecting ANA33 to the lower voltage results in
lesser power consumption, with no difference in performance of the module.
10) For module versions 2.0 and earlier, ANA33 needs to be connected to VINMOD (3.3V)
directly.
11) For USB, it is recommended that the components and their values in the BoM be
adhered to.
12) It is highly recommended that the two USB differential signals (USB_DP and USB_DN)
be routed in parallel with a spacing (say, a) which achieves 90 Ωof differential
impedances, 45 Ω for each trace.
Page 16
RS9113 Module Family
Module Integration Guide
Version 2.10
Figure 6: Spacing between USB_DP and USB_DN
13) In order to minimize crosstalk between the two USB differential signals (USB_DP and
USB_DN) and other signal traces routed close to them, it is recommended that a
minimum spacing of 3 x a be maintained for low-speed non-periodic signals and a
minimum spacing of 7 x a be maintained for high-speed periodic signals.
Figure 7: Spacing for Low-speed and High-speed signals around USB_DP/USB_DN
14) It is recommended that the total trace length of the signals between the RS9113
module and the USB connector be less than 450mm.
15) If the USB high-speed signals are routed on the Top layer, best results will be achieved
if Layer 2 is a Ground plane. Furthermore, there must be only one ground plane under
high-speed signals in order to avoid the high-speed signals crossing to another ground
plane.
Page 17
RS9113 Module Family
Module Integration Guide
Version 2.10
Figure 8: USB Signals and the Ground Plane
2.5 u.FL Connector for External Antenna
The RS9113 based module with integrated antennacomes with an option to connect an
external antenna through a u.FL connector. The choice between the on board antenna and
the external antenna can be made through a software command. The figures below show
the u.FL connector integrated on the module. The connector on the external antenna
should be pushed down to fit into the u.FL connector connected to the module.
Figure 9: u.FL Connector (Part No: Hirose U.FL-R-SMT (01))
Page 18
RS9113 Module Family
Module Integration Guide
Version 2.10
Figure 10: External Antenna
Please refer to the datasheet for details on the Antenna used for certifications like FCC, IC,
ETSI, etc.
Page 19
RS9113 Module Family
Module Integration Guide
Version 2.10
3 RS9113 Module without Integrated Antenna
In the following sections, we present reference schematics, BoM, Recommended PCB
Landing Pattern, Circuit and Layout Guidelinesfor the RS9113 Module without an antenna.
The schematics are shown for SDIO, SPI, UART, USB and USB-CDC host interface options.
3.1 Block Diagram
Figure 11: RS9113 Module without Integrated Antenna
3.2 Reference Schematics and BoM
3.2.1 Reference Schematics
Page 20
RS9113 Module Family
Module Integration Guide
Version 2.10
Figure 12: Reference Schematics for RS9113 Module without Integrated Antenna – Page 1
Title
Size Document Number Rev
Date: Sheet of
RS9113 based Module without Integrated Antenna
1 2Monday, June 15, 2015
Rev1.0
GPIO_15
U2
HOST MCU
NOTES:
1) These connections of GPIOs are needed only for Low Power modes. All or some of them may be left unconnected based
on the Low Power mode usage.
2) Choose between R2 and R7 based on whether GPIO_2 is active-low or active-high in Low Power mode.
3) Please refer to the Datasheet for more details.
GPIO_15
GPIO_2
ULP_GPIO_0
GPIO_21
ULP_GPIO_1
R2
100K
R7
100K
VINMOD
R12
100K
without Integrated Antenna
R8
100K
OPTION 1: Connect to VINMOD through supply filter
OPTION 2: Generate 1.9V from VINMOD and connect to ANA33
NOTE:
ANA33 may be connected to VINMOD (3.3V) through a supply filter or to a lower supply source down to 1.9V. An example
circuit to generate ANA33 is given below. Connecting ANA33 to the lower voltage results in lesser power consumption,
with no difference in performance of the module.
ANA33 Options
D3
RESET_N
U1A
RS9113 Module
VIN_MOD
49
ANA33
50
BBP_LMAC_VDD_12
91
VOUTLDOP1A
63
SDIO_VDD_18_33
27
GND
20
GPIO_0
75
GPIO_1
11
GPIO_2
10
GPIO_3
22
GPIO_4
12
GPIO_5
13
GPIO_6
76
GPIO_7
30
GPIO_8
83
GPIO_13
71
GPIO_14
9
GPIO_15
29
GPIO_16
28
GPIO_17
84
GPIO_18
82
GPIO_19
21
PDN
58
GPIO_21
81
VDD33
59
VRF33
52
VRF33
53
VBATT
100
GND
48
RF_OUT_1
37
RF_OUT_2
32
WURX
2
HOST_BB_EN
94
JNC
97
JP0
69
JP1
70
JP2
96
BOOTLOAD_EN
41
AUX_DAC_OUT
93
RESET_N
74
ULP_GPIO_0
3
ULP_GPIO_1
68
ULP_GPIO_2
99
ULP_ANAGPI
73
AUX_ADC_IN0
65
XTAL_32KHZ_P
4
XTAL_32KHZ_N
5
EXT_PA_ON
64
NC
39
NC
46
NC
54
NC
61
NC
62
NC
89
NC
31
NC
72
NC
56
NC
95
GND
1
GND
33
GND
34
GND
35
GND
36
GND
38
GND
42
GND
43
GND
44
GND
45
GND
47
GND
51
GND
57
GND
67
GND
85
GND
86
GND
87
GND
88
GND
90
GND
101
TP2
DBG_UART_TX
NOTE: TP2
is required
for debug
purposes.
VINMOD
NOTE: TP1 is
required for
debug purposes
only.
ANA33
FB1
BEADC2
0.1uF
C3
1uF
VINMOD
R5 100K
R6 100K
R9 100K
R10 100K
R11 100K
R13 100K
VINMOD
VINMOD_22
U5
Max8902B
OUT
8
BYP
7
FB
6
GS
4
GND
2
EP
9
POK
5
EN
3
IN
1
VINMOD_22
HOST_BB_EN
ANA33
U3
XC9236F08DER-G
LX
1
VOUT
3
VSS
5
VSS
2
VIN
6
CE
4
VINMOD
HOST_BB_EN
C8
10uF
R14 100K
VINMOD
VRF33
VIN_33
C6
150pF
C7
10uF
C9
0.01uF
C12
4.7pF
C11
10uF
RESET_N
GPIO_2
GPIO_21
ULP_GPIO_1
ULP_GPIO_0
R15
300K
L1 4.7uH
R16
187K
R4 4.7K
R3 4.7K
R21
10K
R1 4.7K
R19
10K
FB2
BEAD C4
2.2uF
C5
0.1uF
VINMOD ANA33
R20
120K
HOST_BB_EN
R23
56K
C1 8.2pF
50 Ohm RF line
Z2
TBD
Z3
TBD
Z1 TBD
TP1
ANT1
ANT1
1
ANT2
2
Place Z1, Z2, Z3 and ANT1 close to each other.
R18
100K
OPTION-1
Z1 , Z2, Z3 form the tuning network for matching the
impedance of the Antenna. The values depend upon the
layout. In case tuning network is not implemented Z1
should be placed as 8.2pF as default
C13
0.1uF
RESET_N
C14
8.2nF
R24
100K
R17 1M
U4
MAX6415
VCC
5
SRT
4
RESETn
1
GND
2
RESET IN
3
C10
0.1uF
OPTION-2
R22 402K
RESET Circuitry
SW1
1 2
VIN_33
VIN_33
Host MCU may directly drive the RESET_N
pin of the module as shown below.
OPTION-3
RESET_N
MCU pin
driving
RESET_N
Note: Ensure a reset assertion time of 20ms.
HOST MCU
GPIO Options
NOTE: Please refer to the
Datasheet for details on how to
connect the GPIOs for different
funtions
NOTE: The pullups on
GPIO_3/4/5/6 are not
required if ULP mode
is not used.
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Silicon Labs RS9113 Family Module User guide

Silicon Labs
Brand
Silicon Labs
Model
RS9113 Family Module
Type
User guide
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