LSI LSI53C1000 Ultra160 SCSI Reference guide

Type
Reference guide
®
DB14-000163-05
LSI53C320
Ultra320 SCSI
Bus Expander
TECHNICAL
MANUAL
September 2003
Version 2.2
ii
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000163-05, September 2003
This document describes the LSI Logic LSI53C320 Ultra320 SCSI Bus Expander
and will remain the official reference source for all revisions/releases of this
product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 2003 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic, the LSI Logic logo design, LVDlink, SureLINK, and TolerANT are
trademarks or registered trademarks of LSI Logic Corporation. All other brand
and product names may be trademarks of their respective companies.
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/index.html
KL
LSI53C320 Ultra320 SCSI Bus Expander Technical Manual iii
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Preface
This manual provides a description of the LSI53C320 Ultra320 SCSI Bus
Expander chip that supports all combinations of Single-Ended (SE) and
Low Voltage Differential (LVD) SCSI bus conversions.
Audience
This manual assumes prior knowledge of the current and proposed SCSI
standards. This manual also assumes that you are familiar with
microprocessors and related support devices. The people who benefit
from this book are
engineers and/or managers who are evaluating the LSI53C320 for
use in a system
engineers who are designing the LSI53C320 into a system.
Related Publications
For background information, please contact:
LSI Logic World Wide Web Home Page
www.lsilogic.com
ANSI
www.ansi.org
Global Engineering Documents
www.global.ihs.com
Ask for document number X3.131-1994 (SCSI-2) or X3.253
(SCSI-3 Parallel Interface)
iv Preface
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
ENDL Publications
www.rahul.net/endl/
(408) 867-6630
Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI
Tutor
Organization
This document has the following chapters and appendixes:
Chapter 1, Introduction, contains the general information about the
LSI53C320 product.
Chapter 2, Functional Descriptions, describes the block diagram
and operation of the LSI53C320.
Chapter 3, Signal Description, provides signal descriptions for the
LSI53C320.
Chapter 4, Specifications, contains the electrical characteristics,
timing diagrams, 272-PBGA diagram, and mechanical drawings for
the LSI53C320.
Appendix A, Wiring Diagrams, contains wiring diagrams for a typical
LSI53C320 usage.
Appendix B, Glossary, defines commonly used terms.
Revision Record
Date Version Remarks
2/2001 1.0 Advance/Confidential - includes 272 PBGA mechanical drawing
9/2002 1.1 Rearranged Chapters 2-3 into Chapters 2-4.
Updated the Specifications chapter for G12 processes.
Rewrote in active voice.
5/2003 2.0 Final Version for GCA.
Added the serial EEPROM interface information.
Added the maximum cable length information.
Noted that QAS is not supported in the Ultra160 SCSI mode.
5/2003 2.1 Added disclaimer on the EPBGA mechanical drawing.
9/2003 2.2 Added ground to address lines in Figure 2.5 and Figure A.1.
Contents v
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Contents
Chapter 1 Introduction
1.1 General Description 1-1
1.2 Applications 1-3
1.3 Benefits of Ultra320 SCSI 1-5
1.4 Benefits of SureLINK™ (Ultra320 SCSI Domain Validation) 1-6
1.5 Benefits of LVDlink™ Technology 1-6
1.6 Benefits of TolerANT
®
Technology 1-7
1.7 Features 1-7
Chapter 2 Functional Descriptions
2.1 LSI53C320 Block Diagram Description 2-1
2.1.1 SCSI Control Blocks 2-2
2.1.2 Retiming Logic Block 2-2
2.1.3 Precision Delay Control Block 2-3
2.1.4 State Machine Control Block 2-3
2.1.5 DIFFSENS Receiver Block 2-3
2.2 Ultra320 SCSI Functional Description 2-3
2.2.1 Ultra320 SCSI Features 2-3
2.2.2 SCSI Bus Interface 2-7
2.2.3 Maximum Cable Lengths 2-8
2.3 SCSI Signal Processing 2-11
2.3.1 Data and Data Parity Signals 2-11
2.3.2 Select Signal 2-11
2.3.3 Busy Signal 2-12
2.3.4 Reset Signal 2-12
2.3.5 Request and Acknowledge Signals 2-13
2.3.6 Control/Data, Input/Output, Message, and Attention
Signals 2-14
2.4 Internal Control Descriptions 2-14
vi Contents
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
2.4.1 Self-Calibration 2-14
2.4.2 Delay Line Structures 2-14
2.4.3 Busy Filters 2-15
2.5 Serial EEPROM Connection 2-15
Chapter 3 Signal Description
3.1 Signal Grouping 3-1
3.2 SCSI Interface Signals 3-3
3.3 Interface Control Signals 3-5
3.4 Serial EEPROM Signals 3-6
3.5 Power and Ground Signals 3-6
3.6 Test Signals 3-7
3.7 Signal Layout Considerations 3-8
Chapter 4 Specifications
4.1 Electrical Characteristics 4-1
4.1.1 DC Characteristics 4-1
4.1.2 TolerANT Technology Electrical Characteristics 4-6
4.1.3 AC Characteristics 4-7
4.2 Chip Drawings 4-8
4.2.1 Mechanical Drawing 4-8
4.2.2 BGA Drawing 4-11
Appendix A Wiring Diagrams
A.1 LSI53C320 Wiring Diagrams A-1
Appendix B Glossary
Index
Customer Feedback
Contents vii
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Figures
1.1 LSI53C320 SCSI Bus Modes 1-2
1.2 LSI53C320 Server Clustering 1-3
1.3 LSI53C320 SCSI Bus Device 1-4
2.1 LSI53C320 Block Diagram 2-2
2.2 Paced Transfer Example 2-5
2.3 Example of Precompensation 2-6
2.4 Electrical Cable Lengths at Ultra320 SCSI Speeds 2-10
2.5 Serial EEPROM Connection 2-16
3.1 LSI53C320 Functional Signal Grouping 3-2
4.1 LVD Driver 4-3
4.2 LVD Receiver 4-3
4.3 Rise and Fall Time Test Conditions 4-7
4.4 Clock Timing 4-8
4.5 272-Ball-Count PBGA (VG) Mechanical Drawing 4-9
4.6 LSI53C320 272-Ball BGA Top View 4-12
A.1 LSI53C320 Wiring Diagram 1 of 4 A-2
A.2 LSI53C320 Wiring Diagram 2 of 4 A-3
A.3 LSI53C320 Wiring Diagram 3 of 4 A-4
A.4 LSI53C320 Wiring Diagram 4 of 4 A-5
viii Contents
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Contents ix
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Tables
1.1 Types of Operation 1-2
1.2 SCSI Bus Length Limits in a Clustering Configuration 1-4
1.3 SCSI Bus Length Limits 1-5
2.1 DIFFSENS Voltage Levels 2-8
2.2 Total Cable Length for Ultra320 SCSI Using the
LSI53C320 2-10
3.1 SCSI A Side Interface Signals 3-3
3.2 SCSI B Side Interface Signals 3-4
3.3 Chip Interface Control Signals 3-5
3.4 Serial EEPROM Signals 3-6
3.5 Power and Ground Pins 3-6
3.6 Test Signals for LSI Logic Only 3-7
4.1 Absolute Maximum Stress Ratings 4-1
4.2 Operating Conditions 4-2
4.3 LVD Driver SCSI Signals—SD[15:0]±, SDP[1:0]±,
SCD±, SIO±, SMSG±, SREQ±,SACK±, SBSY±,
SATN±, SSEL±, SRST± 4-2
4.4 LVD Receiver SCSI Signals—SD[15:0]±, SDP[1:0]±,
SCD±, SIO±, SMSG±, SREQ±,SACK±, SBSY±,
SATN±, SSEL±, SRST± 4-3
4.5 Bidirectional SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/,
SACK/, SD[15:0]±, SDP[1:0]±, SREQ±,SACK± 4-4
4.6 Bidirectional SCSI Control Signals—SCD/, SIO/, SMSG/,
SBSY/, SATN/, SSEL/, SRST/, SCD±, SIO±, SMSG±,
SBSY±,SATN±, SSEL±, SRST± 4-4
4.7 DIFFSENS SCSI Signal 4-4
4.8 Input Capacitance 4-5
4.9 Input Control Signals—CLOCK, CHIP_RESET/,
WS_ENABLE/ 4-5
4.10 Output Control Signals—BSY_LED, XFER_ACTIVE 4-5
4.11 TolerANT Technology Electrical Characteristics 4-6
4.12 Clock Timing 4-8
x Contents
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
LSI53C320 Ultra320 SCSI Bus Expander Technical Manual 1-1
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Chapter 1
Introduction
This chapter describes the LSI53C320 Ultra320 SCSI Bus Expander and
includes these sections:
Section 1.1, “General Description, page 1-1
Section 1.2, “Applications, page 1-3
Section 1.3, “Benefits of Ultra320 SCSI, page 1-5
Section 1.4, “Benefits of SureLINK™ (Ultra320 SCSI Domain
Validation), page 1-6
Section 1.5, “Benefits of LVDlink™ Technology, page 1-6
Section 1.6, “Benefits of TolerANT
®
Technology, page 1-7
Section 1.7, “Features, page 1-7
1.1 General Description
The LSI53C320 Ultra320 SCSI Bus Expander is a single-chip solution
allowing the extension of SCSI device connectivity and/or cable length
limits. A SCSI bus expander couples bus segments without impact to the
software, firmware, or SCSI protocol implementation. The LSI53C320
Ultra320 SCSI Bus Expander connects Single-Ended (SE) Ultra SCSI
and Low Voltage Differential (LVD) Ultra320 SCSI peripherals together in
any combination. The LSI53C320 does not support High Voltage
Differential (HVD) mode.
The LSI53C320 supports any combination of the SE or LVD bus modes
on either the A Side or B Side port. This provides the system designer
with maximum flexibility in designing SCSI backplanes to accommodate
any SCSI bus mode. Each bus side on the LSI53C320 has an
independent RBIAS pin to allow for margining of each bus.
1-2 Introduction
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Figure 1.1 shows the two SCSI bus modes available on the A or B Side.
LVDlink transceivers provide the multimode LVD or SE capability. The
LSI53C320 operates as both an expander and a converter. In both SCSI
Bus Expander and Converter modes, the LSI53C320 isolates the cable
segments on the A Side and the B Side. This feature maintains the signal
integrity of each cable segment.
Figure 1.1 LSI53C320 SCSI Bus Modes
Table 1.1 shows the types of operational modes for the LSI53C320.
The LSI53C320 provides additional control capability through the pin-
level isolation mode (Warm Swap Enable). This feature permits logical
disconnection of the A Side bus or the B Side bus without disrupting
SCSI transfers currently in progress. For example, users can logically
disconnect the B Side bus while the A Side bus remains active.
The LSI53C320 is based on proven LSI Logic bus expander technology,
which includes signal filtering along with retiming to maintain skew
budgets. The LSI53C320 is independent of software. However, Domain
Validation technology does require software control.
Note: The LSI53C320 does not support Quick Arbitration and
Selection (QAS) while operating at Ultra160 SCSI rates.
Table 1.1 Types of Operation
Signal Type Speed
LVD to LVD Up to Ultra320 SCSI
SE to SE Up to Ultra SCSI
LVD to SE Up to Ultra SCSI
SE to LVD Up to Ultra SCSI
LSI53C320
SCSI Expander
A Side B Side
LVD
SE
LVD
SE
Applications 1-3
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
1.2 Applications
The LSI53C320 supports
server clustering environments
expanders creating distinct SCSI cable segments that are isolated
from each other
Configurations that use the LSI53C320 SCSI Bus Expander in the LVD
to LVD mode allow the system designer to take advantage of the inherent
cable distance, device connectivity, data reliability, and increased transfer
rate benefits of LVD signaling with Ultra320 SCSI peripherals. Section
2.2.3, “Maximum Cable Lengths, discusses additional limits on the total
SCSI cable length for systems operating at Ultra320 SCSI transfer rates.
Figure 1.2 shows how SCSI bus expanders couple bus segments with no
impact on the SCSI protocol or software. Two LSI53C320 expanders
configure three bus segments. Segment A is a point-to-point segment.
Segments B and C are load segments and have at least 8 inches
between every node. Table 1.2 shows the various distance requirements
for each SCSI bus segment.
Figure 1.2 LSI53C320 Server Clustering
Segment A
Segment B
Segment C
Primary Server
Secondary Server
Shared Disk Subsystem
SCSI Bus
Expander
SCSI Bus
Expander
1-4 Introduction
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Figure 1.3 shows cascading of the LSI53C320 to achieve four distinct
SCSI segments. Segments A and D are point-to-point segments.
Segments B and C are load segments and have at least 8-inch spacing
between every node. Table 1.3 shows the distance requirements for each
SCSI bus segment.
Figure 1.3 LSI53C320 SCSI Bus Device
Table 1.2 SCSI Bus Length Limits in a Clustering Configuration
Segment Mode Length Limit
A LVD (Ultra320 SCSI) Up to 12 meters
SE (Ultra SCSI) Up to 3 meters
1
1. The cable length can be more than 1.5 meters, since this is a point-to-point
connection.
B LVD (Ultra320 SCSI) Up to 12 meters
SE (Ultra SCSI) Up to 1.5 meters
C LVD (Ultra320 SCSI) Up to 12 meters
SE (Ultra SCSI) Up to 1.5 meters
A + B + C + D Ultra320 SCSI (only) Less than 29 meters
2
2. Refer to Section 2.2.3, “Maximum Cable Lengths, for more information on
cable length limits in an Ultra320 SCSI environment.
Segment A Segment B Segment C
Primary
Secondary
Shared Disk
SCSI Bus
Expander
SCSI Bus
Expander
Server
Server
SCSI Bus
Expander
Segment D
Subsystem
Shared Disk
Subsystem
Benefits of Ultra320 SCSI 1-5
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
1.3 Benefits of Ultra320 SCSI
The LSI53C320 SCSI Bus Expander supports Ultra320 SCSI. This
interface expands the bandwidth of the SCSI bus to allow faster
synchronous data transfers of up to 320 Mbytes/s. Ultra320 SCSI
provides double the data transfer rate of the Ultra160 SCSI interface.
The LSI53C320 performs 16-bit, Ultra320 SCSI synchronous data
transfers as fast as 320 Mbytes/s on the side of the device. This
advantage is most noticeable in heavily loaded systems or large block
size applications, such as video on-demand and image processing.
Ultra320 SCSI doubles both the data and clock frequencies from
Ultra160 SCSI. Due to the increased data and clock speeds, Ultra320
SCSI introduces skew compensation and intersymbol interference (ISI)
compensation. These new features simplify system design by resolving
timing issues at the chip level. Skew compensation adjusts for timing
differences between data and clock signals caused by cabling, board
traces, and so on. ISI compensation enhances the first pulse after a
change in state to ensure data integrity. The LSI53C320 performs skew
compensation on the receiver side of the device and ISI compensation
on the driver side of the device.
Ultra320 SCSI supports Cyclic Redundancy Check (CRC), which
provides error checking code to detect the validity of data. CRC
increases the reliability of data transfers by transferring four bytes of
code along with data. CRC detects all single bit errors, two bits in error,
or other error types within a single 32-bit range.
Table 1.3 SCSI Bus Length Limits
Segment Mode Length Limit
A, D LVD (Ultra320 SCSI) Up to 12 meters
SE (Ultra SCSI) Up to 1.5 meters
B, C LVD (Ultra320 SCSI) Up to 12 meters
SE (Ultra SCSI) Up to 1.5 meters
A + B + C + D Ultra320 SCSI (only) Less than 25 meters
1
1. Refer to Section 2.2.3, “Maximum Cable Lengths, for more information on
cable length limits in an Ultra320 SCSI environment.
1-6 Introduction
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
1.4 Benefits of SureLINK™ (Ultra320 SCSI Domain Validation)
SureLINK Domain Validation is a procedure that allows a host computer
and target SCSI peripheral to negotiate and find the optimal transfer
speed. This procedure improves overall reliability of the system by
ensuring data integrity.
Domain Validation software ensures robust SCSI interconnect
management and low risk Ultra320 SCSI implementations by extending
the domain validation guidelines documented in the SPI-4 specifications.
Domain validation verifies that the system is capable of transferring data
at Ultra320 SCSI speeds, allowing the LSI53C320 to renegotiate to a
lower data transfer speed and bus width if necessary. SureLINK Domain
Validation is the software control for the domain validation manageability
enhancements in the LSI53C320. SureLINK Domain Validation software
provides domain validation management at boot time as well as during
system operation.
SureLINK Domain Validation ensures robust system operation by providing
three levels of integrity checking on a per-device basis: Basic (Level 1) with
inquiry command; Enhanced (Level 2) with read/write buffer; and Margined
(Level 3) with margining of drive strength and slew rates.
1.5 Benefits of LVDlink™ Technology
The LSI53C320 supports LVDlink technology for SCSI, a signaling
technology that increases the reliability of SCSI data transfers over
longer distances than those supported by SE SCSI technology. The low
current output of LVD allows the I/O transceivers to be integrated directly
onto the chip. For backward compatibility to existing SE devices, the
LSI53C320 features multimode LVDlink transceivers that can switch
between LVD and SE modes.
Some features of integrated LVDlink transceivers are listed below:
supports SE or LVD modes
allows greater device connectivity and longer cable length
saves the cost of external differential transceivers
provides a long-term performance migration path
Benefits of TolerANT
®
Technology 1-7
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
1.6 Benefits of TolerANT
®
Technology
The LSI53C1320 features TolerANT technology, which provides active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation causes the SCSI Request, Acknowledge,
Data, and Parity signals to be actively driven HIGH rather than passively
pulled up by terminators.
TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
ensure correct clocking of data.
TolerANT technology increases noise immunity, balances duty cycles,
and improves SCSI transfer rates. In addition, TolerANT SCSI devices do
not cause glitches on the SCSI bus at power-up or power-down, which
protects other devices on the bus from data corruption. When used with
the LVDlink transceivers, TolerANT technology provides excellent signal
quality and data reliability in real world cabling environments.
1.7 Features
The LSI53C320
complies with the SCSI Parallel Interface 4 (SPI-4) Specifications
complies with SCSI Enhanced Parallel Interface (EPI)
Specifications
supports Double Transition (DT) clocking
supports CRC in DT data phases
supports Domain Validation technology
supports Ultra320 SCSI Packetized Transfers
provides SCSI signal and timing calibration
is backward-compatible with previous revisions of the SCSI
specification
1-8 Introduction
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
provides a flexible SCSI bus expander
supports any combination of LVD or SE transceivers
creates distinct SCSI bus segments that are isolated from each other
uses integrated LVDlink transceivers for direct attachment to either
LVD or SE bus segments
operates as a SCSI Bus Expander or a SCSI Bus Converter
LVD to LVD (Ultra320 SCSI or Ultra160 SCSI)
SE to SE (up to Ultra SCSI)
LVD to SE (up to Ultra SCSI)
SE to LVD (up to Ultra SCSI)
handles targets and initiators on either the A Side bus or B Side bus
accepts any asynchronous or synchronous transfer speeds up to
Ultra320 SCSI (for LVD to LVD mode only)
supports dynamic addition/removal of SCSI bus segments using the
isolation mode
does not consume a SCSI ID
propagates the RESET/ signal from one side to the other regardless
of the SCSI bus state
notifies initiator(s) of changes in transmission mode (SE/LVD) on A
or B Side segments by using the SCSI bus RESET/
provides a SCSI Busy LED driver for an activity indicator
supports cascading of up to four LSI53C320s
does not require software
requires a 40 MHz Input Clock
has a 272-pin Plastic Ball Grid Array package (PBGA).
LSI53C320 Ultra320 SCSI Bus Expander Technical Manual 2-1
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Chapter 2
Functional
Descriptions
This chapter describes all signals, their groupings, and their functions. It
includes these topics:
Section 2.1, “LSI53C320 Block Diagram Description, page 2-1
Section 2.2, “Ultra320 SCSI Functional Description, page 2-3
Section 2.3, “SCSI Signal Processing, page 2-11
Section 2.4, “Internal Control Descriptions, page 2-14
Section 2.5, “Serial EEPROM Connection, page 2-15
2.1 LSI53C320 Block Diagram Description
The LSI53C320 has no user programmable registers and does not
require software. SCSI control signals control all LSI53C320 functions.
Figure 2.1 shows a block diagram of the LSI53C320 device, which
consists of these specific areas:
A Side SCSI Control Block
LVD and SE Drivers and Receivers
B Side SCSI Control Block
LVD and SE Drivers and Receivers
Retiming Logic
Precision Delay Control
State Machine Control
2-2 Functional Descriptions
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Figure 2.1 LSI53C320 Block Diagram
The LSI53C320 passes data and parity from a source bus to a load bus.
The source bus receives the SCSI signals from the initiator. The load bus
transmits the SCSI signals to the target. The LSI53C320 retimes signals
to maintain the signal skew budget from the source bus to the load bus.
2.1.1 SCSI Control Blocks
The SCSI A Side pins internally connect to the corresponding SCSI B
Side pins. In the LVD/LVD mode, the A Side and B Side control blocks
connect to SCSI devices and accept any asynchronous or synchronous
Ultra320 SCSI data transfer rates. The SCSI control block supports
TolerANT and LVDlink technologies to enable the SCSI bus transfers.
For more information on these technologies, refer to Section 2.2.2.1,
“SCSI Bus Modes.
2.1.2 Retiming Logic Block
As SCSI signals propagate through the LSI53C320, the chip retimes the
signals to improve the SCSI timing. The Retiming Logic block contains
numerous delay elements, which the Precision Delay Control block
periodically calibrates to guarantee the output pulse widths, setup times,
and hold times.
Retiming
Logic
Precision
Delay
Control
State
Machine
Control
LVD
DIFFSENS
Receiver
L
VD
DIFFSENS
Receiv
er
SCSI Contr
ol Block
SCSI Contr
ol Bloc
k
L
VDlink Tr
ansceivers
LVDlink Transceivers
Control
Signals
A Side Signals
B Side Signals
A_DIFFSENS B_DIFFSENS
40 MHz Clock Input
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