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VersaLogic Anaconda (VL-EBX-18) Reference guide

  • Hello! I've reviewed the Programmer's Reference Manual for the Single Board Computer VL-EBX-18. This document provides detailed information about the board's hardware features, memory maps, and register-level access. It also covers the various interfaces like PC/104, PCI Express, and GPIO. I'm familiar with the contents and ready to assist with your questions about this single board computer.
  • What is the address for accessing the FPGA?
    How can I access the SPI registers?
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Programmer’s
Reference
Manual
REV. June 2018
Anaconda
(VL-EBX-18)
DMP Vortex86DX2 SoC-based
SBC with dual Ethernet, Video,
USB, SATA, Analog inputs,
Digital I/O, Counter/Timers,
Mini PCIe, microSD, SPX, and
PC/104-Plus Interface
EBX-18 Programmer’s Reference Manual ii
WWW.VERSALOGIC.COM
12100 SW Tualatin Road
Tualatin, OR 97062-7341
(503) 747-2261
Fax (971) 224-4708
Copyright © 2015-2018 VersaLogic Corp. All rights reserved.
Notice:
Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied warranties
of merchantability or fitness for any particular purpose.
VersaLogic reserves the right to revise this product and associated documentation at any time without
obligation to notify anyone of such changes.
PC/104 and the PC/104 logo are trademarks of the PC/104 Consortium.
EBX-18 Programmer’s Reference Manual iii
Product Release Notes
Release 1.0
First release of document
Release 1.1
Updated document to add FPGA fan registers. Refer to:
• Table 5 on page 5
• Table 17, on page 14
• Table 18, on page 14
• Table 19, on page 14
Release 1.2
Removed 8254 Timer and GPIO interrupts
Support
The EBX-18 Support page contains additional information and resources for this product
including:
Reference Manual (PDF format)
Operating system information and software drivers
VersaAPI Version 1.2.0 and later
Data sheets and manufacturers’ links for chips used in this product
BIOS information and upgrades
Utility routines and benchmark software
This is a private page for EBX-18 users that can be accessed only be entering this address
directly. It cannot be reached from the VersaLogic homepage.
The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with
your VersaLogic product.
VersaTech KnowledgeBase
EBX-18 Programmer’s Reference Manual iv
Contents
Introduction ................................................................................................................... 1
Related Documents ............................................................................................................. 1
System Resources and Maps ....................................................................................... 2
Memory Map ...................................................................................................................... 2
IRQ Map ............................................................................................................................. 2
I/O Map ............................................................................................................................... 3
FPGA Registers ............................................................................................................. 4
Accessing the FPGA ........................................................................................................... 4
FPGA I/O Space ................................................................................................................. 4
FPGA Register Map ........................................................................................................... 5
FPGA Register Descriptions............................................................................................... 6
Product Information Registers ............................................................................... 6
Status/Control Register .......................................................................................... 7
SPI Control Registers ............................................................................................ 8
SPI Data Registers ............................................................................................... 11
SPI Debug Control Register ................................................................................ 12
Miscellaneous FPGA Registers ........................................................................... 13
FANCON – Fan Control Register ....................................................................... 14
FANTACHLS, FANTACHMS – Fan Tach Status Registers ............................. 14
FPGA Interrupt Interface .................................................................................................. 15
Programming Information for Hardware Interfaces .................................................. 16
PC/104 Expansion Bus ..................................................................................................... 16
PCI Express Ports (PCIe) .................................................................................................. 17
Processor WAKE# Capabilities........................................................................................ 17
GPIO Configuration .......................................................................................................... 18
Industrial I/O Functions and SPI Interface ....................................................................... 20
Analog Input ..................................................................................................................... 22
Calibration ........................................................................................................... 22
Initiating an Analog Conversion .......................................................................... 22
Digital I/O Interface .......................................................................................................... 23
Digital I/O Port Configuration ............................................................................. 23
Serial Ports ........................................................................................................................ 23
COM3/COM4 Hardware Configuration .............................................................. 23
COM3/COM4 Software Configuration ............................................................... 24
Serial Port Assignment ........................................................................................ 25
COM Ports (FIFO UARTs) ................................................................................. 26
COM Port Baud Rate Support ............................................................................. 26
Programmable LED .......................................................................................................... 29
Appendix A – References............................................................................................ 30
Contents
EBX-18 Programmer’s Reference Manual v
Figures
Figure 1. COM3/COM4 Control and Termination Jumpers ............................................. 24
Tables
Table 1: Memory Map ........................................................................................................ 2
Table 2: IRQ Map ............................................................................................................... 2
Table 3: I/O Map ................................................................................................................. 3
Table 4: FPGA I/O Map ...................................................................................................... 4
Table 5: FPGA Register Map.............................................................................................. 5
Table 6: PCR – Product Code and LED Register ............................................................... 6
Table 7: PSR – Product Status Register .............................................................................. 6
Table 8: SCR –Status/Control Register .............................................................................. 7
Table 12: SPI Control Register ........................................................................................... 9
Table 13: SPI Status Register............................................................................................ 10
Table 14: SPI – SPI Debug Control Register .................................................................... 12
Table 15: ADM – ADC Control Register ......................................................................... 13
Table 16: MISCSR2 – Misc. Control Register #2 ............................................................ 13
Table 17: FANCON – Fan Control Register .................................................................... 14
Table 18: FANTACHLS – FANTACH Status Register Least Significant Bits ............... 14
Table 19: FANTACHMS – FANTACH Status Register Most Significant Bits ............... 14
Table 20: PC/104 ISA I/O, IRQ, and Memory Resources ................................................ 16
Table 21: PCIe Port Configuration ................................................................................... 17
Table 22: Vortex86DX2 GPIO Configuration .................................................................. 18
Table 23: Analog Input Register Values ........................................................................... 21
Table 24: Digital I/O Register Values ............................................................................... 21
Table 25: COM3/COM4 Control and Termination Jumpers ............................................ 24
Table 26: GPIO Port 2 Direction Register – 0x9A ........................................................... 25
Table 27: GPIO Port 2 Data Register – 0x7A ................................................................... 25
Table 28: Recommended Serial Port Settings for Vortex86DX2 BIOS ........................... 25
Table 29: COM Port PCI Address Map ............................................................................ 27
Table 30: Baud Rates, Divisors, and Base Clock and Ratio Selection for UARTs .......... 28
EBX-18 Programmer’s Reference Manual 1
Introduction
This document provides information for users requiring register-level information for developing
applications with the EBX-18.
Related Documents
The following documents available are on the EBX-18 Product Support Web Page:
EBX-18 Hardware Reference Manual – provides information on the board’s hardware
features including connectors and all interfaces.
EBX-18 BIOS Reference Manual – provides information on accessing and configuring
settings in the BIOS Setup program. All BIOS menus, submenus, and configuration options
are described.
VersaAPI Installation and Reference Guide – describes the shared library of API calls for
reading and controlling on-board devices on certain VersaLogic products.
1
EBX-18 Programmer’s Reference Manual 2
System Resources and Maps
Memory Map
Table 1: Memory Map
Address Range Description
00000000 – 0009FFFF
System RAM
000A0000 – 000AFFFF
EGA/VGA video memory
000B0000 – 000B7FFF
MDA RAM, Hercules graphics display RAM
000B8000 – 000BFFFF
CGA display RAM
000C0000 – 000C7FFF
EGA/VGA BIOS ROM
000C8000 – 000CFFFF
Boot ROM enable
000CC000 – 000CFFFF
Console redirection enable
000D0000 – 000D7FFF
Expansion ROM space
000D8000 – 000DBFFF
SPI Flash emulation floppy A enable
000DC000 – 000DFFFF
Expansion ROM space
000E0000 – 000EFFFF
USB Legacy SCSI ROM space
000F0000 – 000FFFFF
Motherboard BIOS
FEFBB400 – FEFBB4FF
On-board Ethernet adapter
FEFDB800 – FEFDBFFF
Standard enhanced PCI-to-USB host controller
FEFDBC00 – FEFDBCFF
Standard OpenHCD USB host controller
IRQ Map
Table 2: IRQ Map
IRQ Description
IRQ0
System timer
IRQ1
Keyboard controller
IRQ2
Cascade for IRQ8 – IRQ15
IRQ3
COM3 / Vortex86DX2 UART2
IRQ4
COM1 / Vortex86DX2 UART1
IRQ5
USB
IRQ6
USB
IRQ7
USB/Ethernet 10/100Mbit LAN
IRQ8
Real-time clock
IRQ9
Multimedia device
IRQ10
COM2 / Vortex86DX2 UART9
IRQ11
COM4 / Vortex86DX2 UART4
IRQ12
Mouse
IRQ13
Math coprocessor
IRQ14
Hard disk controller #1
IRQ15
Hard disk controller #2
2
System Resources and Maps
EBX-18 Programmer’s Reference Manual 3
I/O Map
Table 3: I/O Map
I/O Address Range Device/Owner
0000h – 000Fh
0020h – 0021h
0022h – 0023h
002Eh – 002Fh
0040h – 0043h
0048h – 004Bh
004Eh – 004Fh
0060h
0061h
0062h – 0063h
0064h
0065h
0066h
0067h
0068h – 006Dh
0070h – 0071h
0072h – 0075h
0078h – 007Ch
0080h – 008Fh
0092h
0098h – 009Ch
00A0h – 00A1h
00C0h – 00DFh
00E0h – 00EFh
0170h – 0177h
01F0h – 01F7h
02E8h – 02EFh
02F8h – 02FFh
0376h
03E8h – 03EFh
03F6h
03F8h – 03FFh
0480h – 048Fh
0490h – 0499h
04D0h – 04D1h
0CF8h – 0CFFh
DE00h – DEFFh
FC00h – FC05h
FC08h – FC0Dh
EBX-18 Programmer’s Reference Manual 4
FPGA Registers
Accessing the FPGA
To access the FPGA, obtain the PCI Base Address Register value (BAR) and add it to the Offset
Address provided in Table 5 below. The PCI BAR can be obtained by reading the 32-bit
hexadecimal value (indicated by the 0x prefix) loaded in the PCI Configuration register at
address 0x10 for PCI Bus 02, Dev 04, Func 00.
The FPGA 32-bit PCI Configuration BAR would normally be read as 0x0000C801 (the LSB=1
simply enables I/O space and is not used with the base address calculation) if there are no other
PCI expansion cards plugged into the system (including PCIe Minicards) which equates to the
FPGA I/O Base Address at 0xC800. Add the Offset Address (found in column 1 of Table 5) to
obtain the I/O address for each 8-bit register.
Example:
FPGA I/O Base Address
0xC800
SPICONTROL offset address
+ 0x08
I/O address for accessing the SPICONTROL register
= 0xC808
FPGA I/O Space
The FPGA is mapped into I/O space on the PCI bus. Without any PCI expansion cards (PC/104-
Plus) in use, the FPGA is the only endpoint device on the PCI bus. The address range will be
mapped into the I/O Space, but because this is a PCI-based device, the base address is subject to
change with the use of PCIe or PCI expansion card use; therefore, it should be read each power
cycle for use in calculating the FPGA register addresses.
FPGA access: PCI I/O space
FPGA access size: All 8-bit (single byte) I/O accesses
FPGA Address Range: PCI I/O BAR for Bus 02/Device 04/Function 00 added to offset
range of 0x00 to 0x3FF (1 Kbyte window, but only addresses 0x00 to 0xFF contain utilized
registers).
The three 8254 timers only require four bytes of addressing and are located at the end of the
256-byte I/O block. The only requirement is that the base address must be aligned on a 4-byte
block. Table 4 lists the FPGA’s I/O map.
Table 4: FPGA I/O Map
Offset Address Range Device Size
0x00 – 0xFB
FPGA registers
252 bytes
0xFC – 0xFF
8254 timer address registers
4 bytes
3
FPGA Registers
EBX-18 Programmer’s Reference Manual 5
FPGA Register Map
Register Access Key
R/W Read/Write
RO Read-only (status or reserved)
R/WC Read-status/Write-1-to-Clear
WO Write-only (0 if read)
RSVD Reserved (registers implemented but not used)
Table 5: FPGA Register Map
Offset
Address Identifier D7 D6 D5 D4 D3 D2 D1 D0
0x00 PCR PLED EBX-18 PRODUCT_CODE = 0010000
0x01 PSR REV_LEVEL RSVD 0 0
0x02 SCR 0 0 0 DEBUG_LED RSVD 0 0 0
0x03 TICR RSVD RSVD RSVD RSVD 0 IMSK_TC5 IMSK_TC4 IMSK_TC3
0x04 TISR INTRTEST TMRTEST TMRIN4 TMRIN3 0 ISTAT_TC5 ISTAT_TC4 ISTAT_TC3
0x05 TCR TIM5GATE TIM4GATE TIM3GATE TM45MODE TM4CLKSEL TM3CLKSEL TMROCTST TMRFULL
0x06 Reserved 0 0 0 0 0 0 0 0
0x07 Reserved 0 0 0 0 0 0 0 0
0x08 SPICONTROL CPOL CPHA SPILEN1 SPILEN0 MAN_SS SS2 SS1 SS0
0x09 SPISTATUS RSVD RSVD SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY
0x0A SPIDATA0 MSB LSB
0x0B SPIDATA1 MSB LSB
0x0C SPIDATA2 MSB LSB
0x0D SPIDATA3 MSB LSB
0x0E SPI 0 MUXSEL2 MUXSEL1 MUXSEL0 0 0 SPILB 0
0x0F ADM 0 0 0 0 0 ADCBUSY 0 ADCONVST
0x11 MISCSR2 NO_BATT W_DISABLE 0 0 0 0 0 USB_OBDIS
0x2C FANCON 0 0 0 0 0 0 0 FAN_OFF
0x2E FANTACHLS MSB <========================> LSB
0x2F FANTACHMS MSB <========================> LSB
0xFC
8254 Timer
Address 0
MSB LSB
0xFD
8254 Timer
Address 1
MSB LSB
0xFE
8254 Timer
Address 2
MSB LSB
0xFF
8254 Timer
Address 3
MSB LSB
FPGA Registers
EBX-18 Programmer’s Reference Manual 6
FPGA Register Descriptions
Register Access Key
R/W Read/Write
RO Read-only (status or reserved)
R/WC Read-status/Write-1-to-Clear
WO Write-only (0 if read)
RSVD Reserved (registers implemented but not used)
PRODUCT INFORMATION REGISTERS
The FPGA register at offset 0x00 (PCR VersaReg) provides read access to the product code. At
offset 0x01 (PSR VersaReg), the revision level can be read.
Table 6: PCR – Product Code and LED Register
Bit
Identifier
Access
Default
Description
7 PLED R/W 0
Drives PLED LED on the paddleboard.
0 – LED is off (default)
1 – LED is on (can be used by software)
6-0
PRODUCT_CODE
RO
0010000
Product Code for the EBX-18 (0x10)
Table 7: PSR – Product Status Register
Bit Identifier Access Default Description
7:3 REV_LEVEL[4:0] RO N/A
Revision level of the PLD (incremented every FPGA release)
0 – Indicates production release revision level when BETA
status bit (bit 0) is set to ‘0’
1 – Indicates development release revision level when BETA
status bit (bit 0) is set to ‘1’
2
Reserved
RO
1
Reserved. Writes are ignored; reads always return 1.
1
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
0
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
FPGA Registers
EBX-18 Programmer’s Reference Manual 7
STATUS/CONTROL REGISTER
Table 8: SCR –Status/Control Register
Bit Identifier Access Default Description
7 Reserved RO N/A Reserved. Writes are ignored; reads always return 0.
6
Reserved
RO
N/A
Reserved. Writes are ignored; reads always return 0.
5
Reserved
RO
N/A
Reserved. Writes are ignored; reads always return 0.
4 DEBUG_LED R/W 1
Debug LED (controls the blue LED):
0 – LED is off and follows its primary function (MSATA_DAS)
1 – LED is on (indicates FPGA is programmed by default)
3
Reserved
RSVD
N/A
Reserved. Writes are ignored; reads always return 0.
2
Reserved
RO
N/A
Reserved. Writes are ignored; reads always return 0.
1 Reserved RO N/A Reserved. Writes are ignored; reads always return 0.
0
Reserved
RO
N/A
Reserved. Writes are ignored; reads always return 0.
FPGA Registers
EBX-18 Programmer’s Reference Manual 8
SPI CONTROL REGISTERS
This section describes the SPI registers for the EBX-18. In this section, the term “BAR” refers to
the PCI Base Address Register value. Refer to the section titled Accessing the FPGA on page 4
for information on determining the values of the BAR and the Offset address.
SPICONTROL (Read/Write) BAR + Offset 08h
D7 D6 D5 D4 D3 D2 D1 D0
CPOL CPHA SPILEN1 SPILEN0 MAN_SS SS2 SS1 SS0
FPGA Registers
EBX-18 Programmer’s Reference Manual 9
Table 9: SPI Control Register
Bit Mnemonic Description
D7 CPOL
SPI Clock Polarity – Sets the SCLK idle state.
0 = SCLK idles low
1 = SCLK idles high
D6 CPHA
SPI Clock Phase – Sets the SCLK edge on which valid data will be read.
0 = Data read on rising edge
1 = Data read on falling edge
D5-D4 SPILEN(1:0)
SPI Frame Length – Sets the SPI frame length. This selection works in manual and auto
slave select modes.
SPILEN1 SPILEN0 Frame Length
0 0 8-bit
0 1 16-bit
1 0 24-bit
1 1 32-bit
D3 MAN_SS
SPI Manual Slave Select Mode – This bit determines whether the slave select lines are
controlled through the user software or are automatically controlled by a write operation to
SPIDATA3. If MAN_SS = 0, then the slave select operates automatically; if MAN_SS = 1,
then the slave select line is controlled manually through SPICONTROL bits SS2, SS1,
and SS0.
0 = Automatic, default
1 = Manual
D2-D0 SS(2:0)
SPI Slave Select – These bits select which slave select will be asserted. The SSx# pin
on the EBX-18 will be directly controlled by these bits when MAN_SS = 1.
SS2 SS1 SS0 EBX-18 Slave Select
0 0 0 None N/A
0 0 1 SS#0 SPX device 1
0 1 0 SS#1 SPX device 2
0 1 1 SS#2 SPX device 3
1 0 0 SS#3 SPX device 4
1 0 1 ADC (Note1) SPI device 5
1 1 0 DIO (Note 2) SPI device 6
1 1 1 None N/A
Notes:
1. The ADC (Analog-to-Digital Converter) is a Linear Tech LTC1857.
2. The DIO (Digital I/O) is made up of two Microchip MCP23S17 devices. The SPI Slave Select for Device 6 selects
them both, so the SPI slave address must be used to differentiate the two devices. DIO[16:1] are accessed with
slave address (binary) 0100000X (X = R/W bit), and DIO[32:17] are accessed with slave address 0100001X.
SPISTATUS (Read/Write) BAR + Offset 09h
D7 D6 D5 D4 D3 D2 D1 D0
Reserved Reserved SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY
FPGA Registers
EBX-18 Programmer’s Reference Manual 10
Table 10: SPI Status Register
Bit Mnemonic Description
D7-D6
Reserved
Reserved
D5-D4 SPICLK(1:0)
SPI SCLK Frequency – These bits set the SPI clock frequency.
SPICLK1 SPICLK0 Frequency
0 0 1.042 MHz
0 1 2.083 MHz
1 0 4.167 MHz
1 1 8.333 MHz
D3 HW_IRQ_EN
Hardware IRQ Enable – Enables or disables the use of the FPGA interrupt by an SPI
device.
0 = SPI interrupt disabled, default
1 = SPI interrupt enabled – passed to FPGA interrupt output
D2 LSBIT_1ST
SPI Shift Direction – Controls the SPI shift direction of the SPIDATA registers. The
direction can be shifted toward the least significant bit or the most significant bit.
0 = SPIDATA data is left-shifted (MSB first), default
1 = SPIDATA data is right-shifted (LSB first)
D1 HW_INT
SPI Device Interrupt State – This bit is a status flag that indicates when the hardware
SPX signal SINT# is asserted.
0 = Hardware interrupt on SINT# is de-asserted
1 = Interrupt is present on SINT#
This bit is read-only and is cleared when the SPI device’s interrupt is cleared.
D0 BUSY
SPI Busy Flag – This bit is a status flag that indicates when an SPI transaction is
underway.
0 = SPI bus idle
1 = SCLK is clocking data in and out of the SPIDATA registers
This bit is read-only.
FPGA Registers
EBX-18 Programmer’s Reference Manual 11
SPI DATA REGISTERS
SPIDATA0 (Read/Write) BAR + Offset 0Ah
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
SPIDATA1 (Read/Write) BAR + Offset 0Bh
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
SPIDATA2 (Read/Write) BAR + Offset 0Ch
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
SPIDATA3 (Read/Write) BAR + Offset 0Dh
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this
register initiates the SPI clock and, if the MAN_SS bit = 0, also asserts a slave select to begin an
SPI bus transaction. Increasing frame sizes from 8-bit use the lowest address for the least
significant byte of the SPI data word; for example, the LSB of a 24-bit frame would be
SPIDATA1. Data is sent according to the LSBIT_1ST setting. When LSBIT_1ST = 0, the MSB
of SPIDATA3 is sent first, and received data will be shifted into the LSB of the selected frame
size set in the SPILEN field. When LSBIT_1ST = 1, the LSB of the selected frame size is sent
first, and the received data will be shifted into the MSB of SPIDATA3.
FPGA Registers
EBX-18 Programmer’s Reference Manual 12
SPI DEBUG CONTROL REGISTER
Table 11: SPI – SPI Debug Control Register
Bit Identifier Access Default Description
7 Reserved RO 0 Reserved – Writes are ignored. Reads always return 0
6-4 MUXSEL(2:0) R/W 000
connector):
• 000 – Select mSATA using only pin 43 (MSATA_DETECT).
This is an Intel-mode that is reliable for PCIe minicards but not
for mSATA modules that inadvertently ground this signal. This
signal is purposely pulled low by the FPGA to avoid
accidentally switching the SATA channel when no mSATA or
PCIe Minicard is present. See the Minicard description for
more info.
• 001 – Use only Pin 51 (PRES_DISABLE2#). This is the
default method and is defined in the Draft mSATA spec but
some minicards use it as a second Wireless disable.
• 010 – Use either Pin 43 or Pin 51. This will work just like 001
because Pin 43 is disabled by an FPGA pull-down.
• 011 – Force PCIe mode on the Minicard
• 100 – Force mSATA mode on the Minicard.
• 101 – Undefined (same as 000)
• 110 – Undefined (same as 000)
• 111 – Undefined (same as 000)
Note: When the Minicard uses PCIe, the SATA channel
automatically switches to the SATA connector.
3
Reserved
RO
0
2
Reserved
RO
0
1 SPILB R/W 0
(debug/test mode).
0 – Normal operation
1 – Loop SPI output data back to the SPI input data (data output
0
RESERVED
RO
0
FPGA Registers
EBX-18 Programmer’s Reference Manual 13
MISCELLANEOUS FPGA REGISTERS
Table 12: ADM – ADC Control Register
Bit Identifier Access Default Description
7 Reserved RO 0 Reserved. Writes are ignored; reads always return 0.
6
Reserved
RO
0
5
Reserved
RO
0
4 Reserved RO 0 Reserved. Writes are ignored; reads always return 0.
3
Reserved
RO
0
2 ADCBUSY RO 0 A '1' if A/D channels 1-8 are busy doing a conversion, '0' otherwise.
1 Reserved RO 0 Reserved. Writes are ignored; reads always return 0.
0 ADCONVST WO 0 Writing a '1' to this will cause the A/D channels 1-8 to start a
Table 13: MISCSR2 – Misc. Control Register #2
Bit Identifier Access Default Description (Note)
7 NO_BATT RO N/A
Indicates whether the V14 jumper is set to use a battery:
0 – Using the RTC Battery
6 W_DISABLE R/W 0
Controls the W_DISABLE (wireless disable) signal going to the
PCIe Minicard:
0 – W_DISABLE signal is not asserted (enabled)
1 – W_DISABLE signal is asserted (disabled)
There are other control sources that can be configured to control
this signal and if enabled the control becomes the “OR” of all
5
Reserved
RO
0
4
Reserved
RO
0
3
Reserved
RO
0
2
Reserved
RO
0
1
Reserved
RO
0
0 USB_OBDIS R/W 0
Disable control for the on-board USB port VBUS power switches
(there are two with a common overcurrent):
0 – VBUS power switches are enabled
1 – VBUS power switched are disabled.
The I2164 power switches latch-off in overcurrent and can only be
re-enabled by a power-cycle or by setting this bit to a ‘1 and then a
Note: This is a register in the always-on power well of the FPGA. It will hold its state during reboots and can only be
reset by a power cycle. It is primarily used for control signals for the always-powered Ethernet controllers and the USB
hubs.
FPGA Registers
EBX-18 Programmer’s Reference Manual 14
FANCON – FAN CONTROL REGISTER
The fan is always on by default. To turn the fan off, write a 1 to bit 0. No PWM fan control is
supported on the EBX-18. Reset type is Platform.
Table 14: FANCON – Fan Control Register
Bits Identifier Access Default Description
7-1
Reserved
RO
0000000
0 FAN_OFF R/W 0 0 – Fan is on
FANTACHLS, FANTACHMS – FAN TACH STATUS REGISTERS
These registers contain the number of fan tach output samples over a one-second sampling
period. The value is always valid after the fan speed stabilizes and is updated every 1 second
(after a delay of 1 second). Currently, only the lower 10-bits have a valid tach reading (that is,
the upper 6 bits will always be zero). The fan tach count should never overflow in the one second
period, but it if does, the value will “stick” at 0x03FF. Reset type is n/a.
The board can handle up at least a 10,000 RPM fan with a fan tach output of up to four uniform
pulses per revolution. The duty cycle of the fan tach output pulse can be as low as 25% (typically
they are very close to 50%). The conversion to RPM is as follows:
RPM = (FANTACH x 60) / PPR
Where…
• FANTACH - the 16-bit register reading
• PPR – fan tach pulses per revolution (typically either 1, 2, or 4)
Table 15: FANTACHLS – FANTACH Status Register Least Significant Bits
Bits Identifier Access Default Description
7-0 FANTACH[7:0] RO N/A
Least significant eight bits of FANTACH.
Read this register first since it latches the value for the most
significant eight bits.
Table 16: FANTACHMS – FANTACH Status Register Most Significant Bits
Bits Identifier Access Default Description
7-0 FANTACH[15:8] RO N/A Most significant eight bits of FANTACH.
Read this register after reading FANTACHLS.
Integrator’s Note:
The FANTACHLS register must be read first. It will latch a copy of the MS bits so that when
FANTACHMS is read, it is based on the same 16-bit value. This assumes that a 16-bit word read
on the PCI bus reads the even (LS) address before the odd (MS) address.
FPGA Registers
EBX-18 Programmer’s Reference Manual 15
FPGA Interrupt Interface
The FPGA signal FPGA_INT# is an active low interrupt routed to the Vortex86DX2 GPIO pin
GP02. The source for this interrupt signal can be from the following FPGA functions:
Timer
SPX interface
DIO devices
The INTRTEST bit in the TISR may be used to test this signal connectivity since there is no
SERIRQ availability for this board (because the FPGA interface is PCI based instead of LPC
based).
The timer interrupts are always enabled but can be masked individually with TICR
IMSK_TC(5:3). There is only one SPISTATUS register bit HW_IRQ_EN to enable/disable both
the SPX and DIO interrupts.
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