Multiscanning Color Monitor
TECHNICAL SERVICE MANUAL
LM-1510A(LM-1510B)
--14--
P
P
i
i
n
n
O
O
u
u
t
t
D
D
i
i
a
a
g
g
r
r
a
a
m
m
Figure 1. gmZAN2 Pin Diagram
CVSS1
Reserved
PSCAN
Reserved
CVSS!A
PD47
PD46
RVSS1
PD45
PD44
SRVDD1
RVDD1
PD43
PD42
PD41
PD40
PD39
SRVSS1
PD38
PD37
SRVDD2
PD36
PD35
PD34
PD33
PD32
PD31
PD30
PD29
RVSS2
PD28
PD27
RVDD2
PD26
PD25
PD24
PD23
PD22
PD21
RVDD2A
OSD_DATA2
OSD_DATA1
OSD_DATA0
OSD_CLK
OSD_VREF
OSD_HREF
CVSS4
MFB0
MFB1
MFB2
MFB3
MFB4
RVDD3A
MFB5
MFB6
MFB7
MFB8
HCL K
MFB9
IRQ
RESETn
HDATA
HFS
N/C
ADC_RVDDA
RED+
RED-
ADC_RGNDA
ADC_GVDDA
GREEN+
GREEN-
ADC_GGNDA
ADC_BVDDA
BLUE+
BLUE-
ADC_BGNDA
ADC_VDDA
Reserved
ADC_GNDA
SUB_GNDA
OSD_DATA3
OSD_FSW
MFB11
MFB10
DVDD
DVSS
DAC_DGNDA
DAC_DVDDA
PLL_DVDDA
Reserved
PLL_DGNDA
SUB_DGNDA
SUB_SGNDA
PLL_SGNDA
Reserved
PLL_SVDDA
DAC_SVDDA
DAC_SGNDA
SVDD
SVSS
TCLK
XTAL
PLL_RVDDA
PLL_RGNDA
Reserved
SUB_RGNDA
CVSS5
VSYNC
SYN_VDD
HSYNC/CS
SYN_VSS
Reserved
STI_TM 1
STI_TM 2
SCAN_IN1
Reserved
SCAN_IN2
SRVSS2
SCAN_OUT1
SCAN_OUT2
ADC_GND1
ADC_VDD1
ADC_GND2
ADC_VDD2
PPWR
PBIAS
PHS
PVS
CVSS3
PD0
PD1
PD2
PD3
PD4
PD5
RVDD3
PD6
PD7
PD8
RVSS4
RVDD2B
CVSS2A
CVDD2
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
RVSS3
PD17
PD18
PD19
PCLK B
PCLK A
PDISPE
PD20
CVSS2
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
gmZAN2 (160-Pin PQFP)
--15--
LM-1510A(LM-1510B) Technical Service Manual
FEATURES
8051 core, 12MHz operating frequency with double CPU clock option
0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating
1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP)
Maximum 14 channels of PWM DAC
Maximum 31 I/O pins
SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment
Built-in low power reset circuit
Built-in self-test pattern generator with four free-running timings
Compliant with VESA DDC1/2B/2Bi/2B+ standard
Dual slave IIC addresses; H/W auto transfer DDC1/DDC2x data
Single master IIC interface for internal device communication
Maximum 4-channel 6-bit ADC
Watchdog timer with programmable interval
Flash-ROM program code protection selection
40-pin DIP, 42-pin SDIP or 44-pin PLCC package
GENERAL DESCRIPTIONS
The MTV312M micro-controller is an 8051 CPU core embedded device especially tailored for CRT/LCD
Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC
interface, 4-channel A/D converter, and a 64K-byte internal program Flash-ROM.
BLOCK DIAGRAM
XFR
P0.0-7
P2.0-3
RD
WR
ALE
INT1
P0.0-7
P2.0-3
RD
WR
ALE
INT1
8051
CORE
P1.0-7
P3.0-2
P3.4-5
RST
X1
X2
ADC
A
D0-3
PWM DAC
DA0-13
DDC & IIC
INTERFACE
ISCL
ISDA
HSCL
HSDA
AUXRAM &
DDCRAM
HSYNC
VSYNC
HBLANK
VBLANK
H/VSYNC
CONTROL
P6.0-7
P5.0-6
AUX
I/O
P4.0-2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MTV312M64
--16--
PIN CONNECTION
MTV312M
40 Pin
PDIP
DA2/P5.2 401
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DA1/P5.1
DA0/P5.0
VDD3
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
HSYNC
DA3/P5.3
VSYNC
DA4/P5.4
DA8/HLFHO
DA9/HALFV
DA5/P5.5
HBLANK/P4.1
DA7/HCLAMP
DA6/P5.6
VBLANK/P4.0
RST
P6.5/DA11
P6.4/DA10
P6.6/DA12
HSCL/P3.0/Rxd
P6.0/AD0
P6.1/AD1
HSDA/P3.1/Txd
P1.7
MTV312M
44 Pin
PLCC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
P1.6
24
P1.7
P6.1/AD1
P1.5
P6.0/AD0
HSDA/P3.1/Txd
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
23
22
21
20
28
27
26
25
NC 6
5
4
3
2
1
44
43
42
41
40
NC
VDD3
DA0/P5.0
DA1/P5.1
DA2/P5.2
VSYNC
HSYNC
DA3/P5.3
DA4/P5.4
DA5/P5.5
19
18
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
P6.3/AD3
P6.4/DA10
HSCL/P3.0/Rxd
P6.5/DA11
P6.6/DA12
DA8/HLFHO
DA9/HALFV
HBLANK/P4.1
DA7/HCLAMP
DA6/P5.6
VBLANK/P4.0
P6.7/DA13
MTV312M
42 Pin
SDIP
DA2/P5.2
40
1
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2221
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DA1/P5.1
DA0/P5.0
RST
VDD
VSS
VDD3
NC
NC
HSYNC
DA3/P5.3
VSYNC
DA4/P5.4
DA8/HLFHO
DA9/HALFV
DA5/P5.5
HBLANK/P4.1
DA7/HCLAMP
DA6/P5.6
VBLANK/P4.0
42
41
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
X2
X1
P6.6/DA12
P6.5/DA11
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P6.4/DA10
P6.0/AD0
P1.7
P1.6
P6.1/AD1
P1.5
--17--
LM-1510A(LM-1510B) Technical Service Manual
PIN CONFIGURATION
A CMOS output pin means it can sink and drive at least 4mA current. It is not recommended to use such
pin as input function.
A open drain pin means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as
input or output function and needs an external pull up resistor.
A 8051 standard pin is a pseudo open drain pin. It can sink at least 4mA current when output is at low level,
and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA
to maintain the pin at high level. It can be used as input or output function. It needs an external pull up
resistor when driving heavy load device.
POWER CONFIGURATION
The MTV312M can work on 5V or 3.3V power supply system.
In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, all
output pins can swing from 0~5V, input pins can accept 0~5V input range. And ADC conversion range is 5V.
However, X1 and X2 pins must be kept below 3.3V.
In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V,
HSYNC, VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. And
the ADC conversion range is 3.3V.
8051 Standard Pin
4mA
4mA
Output
Data
Pin
CMOS Output Pin
Open Drain Pin
2 OSC
period
delay
4mA 10uA
Output
Data
120uA
Pin
4mA
Input
Data
No Current
4mA
Output
Data
Pin
Input
Data
VDD
VDD3
5V
10u
MTV312M in
5V System
3.3V
VDD
VDD3
MTV312M in
3.3V System
--18--
Universal Serial Bus (USB) Version 1.1
Compliant
32-Pin LQFP
≤
Package With a 0.8 mm Pin
Pitch
3.3-V Low Power ASIC Logic
Integrated USB Transceivers
State Machine Implementation Requires No
Firmware Programming
One Upstream Port and Four Downstream
Ports
All Downstream Ports Support Full-Speed
and Low-Speed Operations
Two Power Source Modes
± Self-Powered Mode
± Bus-Powered Mode
Power Switching and Over-current
Reporting Is Provided Ganged or Per Port
Supports Suspend and Resume Operations
Supports Programmable Vendor ID and
Product ID With External Serial EEPROM
3-State EEPROM Interface Allows EEPROM
Sharing
Push-Pull Outputs for PWRON
Eliminate
the Need for External Pullup Resistors
Noise Filtering on OVRCUR
Provides
Immunity to Voltage Spikes
Package Pinout Allows 2-Layer PCB
Low EMI Emission Achieved by a 6-MHz
Crystal Input
Migrated From Proven TUSB2040 Hub
Lower Cost Than the TUSB2040 Hub
Enhanced System ESD Performance
Supports 6 MHz Operation Through a
Crystal Input or a 48 MHz Input Clock
description
The TUSB2046B is a 3.3-V CMOS hub device that provides one upstream port and four downstream ports in
compliance with the 1.1 Universal Serial Bus (USB) specification. Because this device is implemented with a
digital state machine instead of a microcontroller, no firmware programming is required. Fully compliant USB
transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support
both full-speed and low-speed devices by automatically setting the slew rate according to the speed of the
device attached to the ports. The configuration of the BUSPWR pin selects either the bus-powered or the
self-powered mode.
VF PACKAGE
(TOP VIEW)
31 30 29 28 27
910
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DP4
DM4
OVRCUR4
PWRON4
DP3
DM3
OVRCUR3
PWRON3
DP0
DM0
V
CC
RESET
EECLK
EEDATA/GANGED
GND
BUSPWR
32 26
11 12 13
14 15
PWRON1
OVRCUR1
DM1
DP1
DM2
SUSPND
TSTMODE
XTAL1
XTAL2
GND
TSTPLL/48MCLK
EXTMEM
16
25
DP2
PWRON2
OVRCUR2
V
CC
TUSB2046B/B1
--19--
LM-1510A(LM-1510B) Technical Service Manual
description (continued)
Configuring the GANGED input determines the power switching and over-current detection modes for the
downstream ports. External power management devices such as the TPS2044 are required to control the 5-V
source to the downstream ports according to the corresponding values of the PWRON
pin. Upon detecting any
over-current conditions, the power management device sets the corresponding OVRCUR
pin of the
TUSB2046B to a logic low. If GANGED is high, all PWRON
outputs switch together and if any OVRCUR is
activated, all ports transition to power off state. If GANGED is low, the PWRON
outputs and OVRCUR inputs
operate on a per port basis.
The TUSB2046B provides the flexibility of using a 6-MHz or a 48-MHz clock. The logic level of the TSTMODE
terminal controls the selection of the clock source. When TSTMODE is low, the output of the internal APLL
circuitry is selected to drive the internal core of the chip. When TSTMODE is high, the TSTPLL/48MCLK input
is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal
oscillator cell is also powered down while TSTMODE is high.
Low EMI emission is achieved because the TUSB2046B is able to utilize a 6 MHz crystal input. Connect the
crystal as shown in Figure 6. An internal PLL then generates the 48 MHz clock used to sample data from the
upstream port and to synchronize the 12 MHz used for the USB clock. If low power suspend and resume are
desired, a passive crystal or resonator must be used. However, a 6-MHz oscillator may be used by connecting
the output to the XTAL1 terminal and leaving the XTAL2 terminal open. The oscillator TTL output must not
exceed 3.6 V.
For 48-MHz operation, the clock can not be generated with a crystal, using the XTAL2 output, since the internal
oscillator cell only supports fundamental frequency.
Refer to Figure 7 and Figure 8 in the
input clock configuration
section for more detailed information regarding
input clock configuration.
The EXTMEM
pin enables or disables the optional EEPROM interface. When the EXTMEM pin is high, the
product ID (PID) displayed during enumeration is the general-purpose USB hub. For this default, pin 5 is
disabled and pin 6 functions as the GANGED input pin. If custom PID and Vendor ID (VID) descriptors are
desired, the EXTMEM
pin must be low (EXTMEM = 0). For this configuration, pin 5 and pin 6 function as the
EEPROM interface with pin 5 and pin 6 functioning as the EECLK and EEDATA, respectively. See Table 1 for
a description of the EEPROM memory map.
Other useful features of the TUSB2046B include a package with a 0.8 mm pin pitch for easy PCB routing and
assembly, push-pull outputs for the PWRON
pins eliminate the need for pullup resistors required by traditional
open collector I/Os, and OVRCUR
pins have noise filtering for increased immunity to voltage spikes.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BLOCK DIAGRAM
Analog
R
·
··
·
G
·
··
·
B
20 Mhz
12 Mhz
ZENESIS
(gmZAN1 or gmZAN2)
LVDS Channels
(CS5824)
Panel Connector
HYDIS (HT15X13)
SAMSUNG (LTM150XH-L01)
Micro
Controller
(MTV312M)
MODEL NAME : L50C(S527B/L550B/L1510B)
AUDIO & USB
AUDIO (TDA7496L)
USB (TUSB2046B)
6 Mhz
Sub B/D
AUDIO MUTE
<Doc> B
7. BLOCK DIAGRAM
A
77Friday, January 04, 2002
Title
Size Document Number Rev
Date: Sheet of
A
A
B
B
C
C
D
D
E
E
5 5
4 4
3 3
2 2
1 1
01.09.04
3
1
SHEET
CONTENTS
4. LVDS & Power
A
Date
G.H.NAM
4
2. gmZAN1/2 2
CommentsAuthorSCHEMATIC
REVISION HISTORY
L50C(S527B/L550B/L1510B) Schematic
3. MCU(MTV312M)
Ver
Initial release ver A1. Contents, Revision History
5
01.11.29
S527
NOISE
SOLUTION
E
5. AUDIO & USB
6. OSD 6
77. BLOCK DIAGRAM
02.01.03
B L1510B MP
W.S.IM
NONE B
1. Contents
B
17Friday, January 04, 2002
Title
Size Document Number Rev
Date: Sheet
of
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ANALOG SUPPLY
DECOUPLING
ANALOG AND DIGITAL GROUNDS MUST BE
INTERCONNECTED AT A SINGLE POINT
NOTE:
3.3
DIGITAL
SUPPLY
DECOUPLING
3.3
DIGITAL
SUPPLY
DECOUPLING
VGA INPUT
CONNECTOR
SOT23
SOT23
SOT23
SOT23 SOT23
SOT23SOT23
Default R218
R211 NC
REV. E
REV. E
U203A NC
NONE B
2. gmZAN1 or gmZAN2
C
27Friday, January 04, 2002
Title
Size Document Number Rev
Date: Sheet
of
DVDDA
SVDDA
VDDA
PD16
PD2
PD10
PD5
PD13
PD11
PD4
PD9
PD17
RVDDA
PD0
PD3
PDISPE
PD1
PD6
PD8
PD12
PD7
PD14
PD15
PD[0..5]
PD[6..11]
PD[12..17]
PD37
PD38
PD39
PD40
PD41
PD36
PVS
PHS
PCLKA
VGA_SCL
VGA_VSYNC
VGA_HSYNC
BLUE-
RED-
GREEN-
GREEN+
RED+
BLUE+
GREEN
RED
BLUE
IRQ
HFS
MFB3
MFB9
MFB1
MFB2
MFB8
HCLK
RESETn
MFB7
HDATA0
MFB0VGA_SCL
VGA_SDA
VGA_SDA
+3.3V
GND
+3.3V
GND
ZAN1_3.3V/ ZAN2_2.5V
GND
ZAN1_3.3V/ ZAN2_2.5V
GND GNDGND GND
GND
+5V
GND
GND
+5V
GND
GND GND
+5V
GND
GND
GND
GND
GND
GND
GND
GND
R217
10K
U200
gmZAN1/gmZAN2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
6061
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
108
114
115
116
117
118
119
120
121
122
123
124
125
126
127 128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
113
112
111
110
109
107
106
105
104
144
CVSS1
RESERVED
PSCAN
RESERVED
CVSS1A
PD47
PD46
RVSS1
PD45
PD44
SRVDD1
RVDD1
PD43
PD42
PD41
PD40
PD39
SRVSS1
PD38
PD37
SRVDD2
PD36
PD35
PD34
PD33
PD32
PD31
PD30
PD29
RVSS2
PD28
PD27
RVDD2
PD26
PD25
PD24
PD23
PD22
PD21
RVDD2A
CVSS2
PD20
PDISPE
PCLKA
PCLKB
PD19
PD18
PD17
RVSS3
PD16
PD15
PD14
PD13
PD12
PD11
PD10
PD9
CVDD2
CVSS2A
RVDD2BRVSS4
PD8
PD7
PD6
RVDD3
PD5
PD4
PD3
PD2
PD1
PD0
CVSS3
PVS
PHS
PBIAS
PPWR
ADC_VDD2
ADC_GND2
ADC_VDD1
ADC_GND1
SUB_GNDA
ADC_GNDA
RESERVED
ADC_VDDA
ADC_BGNDA
BLUE-
BLUE+
ADC_BVDDA
ADC_GGNDA
GREEN-
GREEN+
ADC_GVDDA
ADC_RGNDA
RED-
RED+
ADC_RVDDA
N/C
HFS
HDATA
RESETn
IRQ
MFB9
HCLK
CVDD4
CVSS4
OSD_HREF
OSD_VREF
OSD_CLK
OSD_DATA0
OSD_DATA1
OSD_DATA2
OSD_DATA3
OSD_FSW
MFB11
MFB10
DVDD
DVSS
DAC_DGNDA DAC_DVDDA
PLL_DVDDA
RESERVED
PLL_DGNDA
SUB_DGNDA
SUB_SGNDA
PLL_SGNDA
RESERVED
PLL_SVDDA
DAC_SVDDA
DAC_SGNDA
SVDD
SVSS
TCLK
XTAL/RESERVED
PLL_RVDDA
RESERVED
SUB_RGNDA
CVSS5
VSYNC
SYN_VDD
HSYNC/CS
SYN_VSS
RESERVED
STI_TM1
STI_TM2
SCAN_IN1
RESERVED
SCAN_IN2
SRVSS2
SCAN_OUT1
SCAN_OUT2
MFB0
MFB1
MFB2
MFB3
MFB4
MFB5
MFB6
MFB7
MFB8
PLL_RGNDA
R219 0
R213
47K
C216
0.1uF
R209 22
C232 0.01uF
R220 0
C224
0.1uF
C241
18pF
C208
0.1uF
C209
22uF/16V
C230 0.01uF
R211
0
C227
0.1uF
R218 0
C218
0.1uF
C233 0.01uF
C213
0.1uF
X200
20MHz
U203B
74LCX14 SO14
3 4
14
7
C200
22uF/16V
C242
18pF
U203C
74LCX14 SO14
5 6
14
7
R208 100
R200 100
C228
0.1uF
C229
0.1uF
C235 0.01uF
C243
NC
C210
22uF/16V
R202 100
C214
0.1uF
C205
0.1uF
D200
6.2V
R206
75
C201
22uF/16V
C202
0.1uF
C217
0.1uF
U203A
74LCX14 SO14
1 2
14
7
R205
75
C225
22uF/16V
R203 100
R214 100
C223
22uF/16V
C219
0.1uF
R204
75
R210 22
D204
RLS4148
D206 KDS226
C203
0.1uF
C212
0.1uF
R215 100
R216
10K
C206
22uF/16V
D207 KDS226
D205 KDS226
D208
6.2V
C226
0.1uF
C207
0.1uF
C239
0.1uF
C231 0.01uF
C222
0.1uF
D201
6.2V
C211
0.1uF
U203D
74LCX14 SO14
9 8
14
7
CN200
DB15HD
1
6
2
7
3
8
4
9
5
11
12
13
14
15
10
D202
6.2V
C220
0.1uF
U202
24LC21 8P SOIC
4
8 1
2
3
7
6
5
GND
VCC NC
NC
NC
VCLK
SCL
SDA
R207 100
R212
47K
C221
0.1uF
C234 0.01uF
C240
47pF
R201 100
C204
0.1uF
C215
0.1uF
D203
6.2V
PD[0..5] SHEET 4
PD[6..11] SHEET 4
PD[12..17] SHEET 4
PD36 SHEET 4
PD37 SHEET 4
PD38 SHEET 4
PD39 SHEET 4
PD41 SHEET 4
PD40 SHEET 4
PVS SHEET 4
PHS SHEET 4
PDISPE SHEET 4
PCLKA SHEET 4
HCLKSHEET 3
KEY_DOWNSHEET 3
HDATAF2SHEET 3
KEY_UPSHEET 3
SELECTSHEET 3
MENUSHEET 3
HFSSHEET 3
HDATAF3SHEET 3
HDATAF0SHEET 3
HDATAF1SHEET 3
/IRQSHEET 3
ZAN_RSTSHEET 3
VGA_CON SHEET 3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KEY_UP
LED_ORANGE_EN
LED_GRN_EN
SELECT
PWM_BRIGHT
INVERTER
CONNECTOR
HDATAF0
HDATAF1
HDATAF2
HDATAF3
Only L1510B
NONE B
3. MCU(MTV312M)
C
37Friday, January 04, 2002
Title
Size Document Number Rev
Date: Sheet
of
KEY_DOWN
MUTE
GND
+5V
GNDGND
GND
+5V
GND
+5V
GND
+5V
+12V
+5V
+5V
+5V
GND
GND
GND
+12V
GND
+5V
R301
10K
C309
1uF/50V
C302
0.1uF
R319 470
C304
10uF/16V
C305
10uF/16V
R314 470
MTV312M
44Pin
PLCC
U303
MTV312M
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
RST
VDD
P6.3/AD3
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
P1.1
P3.2/INTO
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P6.1/AD1
P6.0/AD0
P3.1/Txd
P3.0/Rxd
P6.4/DA10
P6.5/DA11
P6.6/DA12
P6.7/DA13
DA6/P5.6
DA7/HCLAMP
VBLANK/P4.0
HBLANK/P4.1
DA9/HALFV
DA8/HALFH
DA5/P5.5
DA4/P5.4
DA3/P5.3
HSYNC
VSYNC
DA2/P5.2
DA1/P5.1
DA0/P5.0
VDD3
NC
NC
C313
0.1UF
C319
0.1uF
C314
0.1uF
R302 10K
C315
0.1uF
C308
18pF
R313 330
C316
0.1uF
R304 10K
C317
0.1uF
D301
RLS4148
C318
0.1uF
R312 330
U301
24LC08SOIC
1
2
3
4 5
6
7
8
A0
A1
A2
VSS SDA
SCL
WP
VCC
R303 10K
X300
12MHz
R300
10K
R307
1K
R306 10K
R334 10K
CN303
HEADER 7
1
2
3
4
5
C303
0.1uF
C306
0.1uF
R315
10K
CN301
HEADER 8
1
2
3
4
5
6
7
8
R321 10K
R305 10K
R309 4.7K
C307
18pF
R322 10K
R308 4.7K
R310 4.7K
R323 10K
R324 10K
C301
0.1uF
CN302
HEADER 6
1
2
3
4
5
6
C300
10uF/16V
HDATAF[0..3] SHEET 2
HFS SHEET 2
HCLK SHEET 2
/IRQ SHEET 2
MENU
SHEET 2
KEY_UP
SHEET 2
KEY_DOWN
SHEET 2
SELECT
SHEET 2
LVDS_EN SHEET 4
ZAN_RST SHEET 2
PANEL_POWERSHEET 4 VGA_CON SHEET 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1pxl/clk
RED
GREEN
BLUE
NONE B
4. LVDS & POWER
C
47Friday, January 04, 2002
Title
Size Document Number Rev
Date: Sheet
of
PD10
PD0
PD8
PD3
SLVDSR/F
PD16
PD[12..17]
PD36
PD13
PD4
PD14
PD12
PD40
PD5
PDISPE
PD7PD[6..11]
PHS
SLVDSPDN
PD38
PD2
PCLKA
SPLL-VCC
PD[0..5]
PD9
PD1
PD17
PD6
PVS
PD15
PD11
PD37
PD41
PD39
SO-TD6
STTL-GND
RX0-
RX1+
RX1-
RX0+
RX2-
RX2+
RXCLK-
RXCLK+
RX3-
RX3+
RX0-
RX0+
RX1-
RX1+
RX2-
RX2+
RXCLK-
RXCLK+
RX3-
RX3+
SPLL-GND
+3.3V
GND GND
LVDS_3.3V
ZAN1_3.3V / ZAN2_2.5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PANEL_3.3V
GND
GND
GND
LVDS_3.3V
GND
GND
GND
PANEL_3.3V
GND
GND
GND
GND
+5V
+12V
U403
CS5824
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
VCC TA4
TD1 TA3
TA5 TA2
TA6 GND3
GND TA1
TB0 TA0
TB1 TD0
TD2 LVDSGND
VCC1 TA-
TD3 TA+
TB2 TB-
TB3 TB+
GND1 LVDSVCC
TB4 LVDSGND1
TB5 TC-
TD4 TC+
R/F TCLK-
TD5 TCLK+
TB6 TD-
TC0 TD+
GND2 LVDSGND2
TC1 PLLGND
TC2 PLLVCC
TC3 PLLGND1
TD6 /PDWN
VCC2 CLKIN
TC4 TC6
TC5 GND4
C408
0.1uF
C401
0.1uF
R404 33
R401
1K
C402
0.1uF
C420
33pF
R402 33
C413
22uF/16V
U400
RC1117.3.3
SOT223
1
3 2
GND
VIN VOUT
CN400
POWER
12V
6
5V2
GND
4
5V
5
GND
3
12V
1
R403 33
C421
33pF
C426
100uF/16V
C422
33pF
C423
100uF/16V
C424
0.1uF
C405
22uF/16V
C411
22uF/16V
C414
22uF/16V
C406
0.1uF
R400
1K
R406 4.7K
C415
0.1uF
U401
ZAN1 RC1117_3.3 / ZAN2 RC1117_2.5
SOT223
1
3 2
GND
VIN VOUT
C416
0.1uF
C409
0.1uF
C407
22uF/16V
CN401
DF-14A-20P-1.25H
15
18
8
12
11
10
9
7
6
5
4
3
2
20
19
17
16
14
13
1
RXCLK+
RX3+
RX1-
RX2+
RX2-
GND
RX1+
GND
RX0+
RX0-
GND
GND
VDD
NC
GND
RX3-
GND
RXCLK-
GND
VDD
C412
0.1uF
C410
22uF/16V
U402
RC1117.3.3
SOT223
1
3 2
GND
VIN VOUT
C425
0.1uF
C404
0.1uF
C400
0.1uF
R405 33
C403
0.1uF
C419
33pF
U404
SI4435 SO8
1
2
3
4
8
7
6
5
S
S
S
G
D
D
D
D
PD[0..5]SHEET 2
PD[6..11]SHEET 2
PD[12..17]SHEET 2
PD36SHEET 2
PD37SHEET 2
PD38SHEET 2
PD39SHEET 2
PD40SHEET 2
PD41SHEET 2
PHSSHEET 2
PVSSHEET 2
PDISPESHEET 2
PCLKASHEET 2
RX0-
RX1-
RX1+
RX0+
RX2-
RX2+
RXCLK-
RXCLK+
RX3-
RX3+
RX0-
RX0+
RX1-
RX1+
RX2-
RX2+
RXCLK-
RXCLK+
RX3-
RX3+
PANEL_POWERSHEET 2
LVDS_EN SHEET 3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
WC-A3
TDA7496L
TUSB2046BTUSB2046B
<Doc> B
5. AUDIO & USB
C
57Friday, January 04, 2002
Title
Size Document Number Rev
Date: Sheet
of
GND
GND
GND
GND
GND
GND
GND
3.3V
GND
GND
GND
GND
GND
GND
GND
GND
GND
5V
GND
GND
GND
GND
GND
GND
GND
GND GND
3.3V
GND
GND
5V
5V
GND
GND
C503
0.1uF
R500 240
C520
0.47uF
R528 100
R503 22
R526 10K
R506
30K
CN521
1
2
3
4
5
6
7
OUTR
GND
OUTL
GND
VOL
GND
+5V
RN503
15K
18
27
36
45
C529
330uF/16V
CN500
UP
4
3
2
1
GND
DP
DM
5V
R502 1.5K
C51147pF
RN502
22
1 8
2 7
3 6
4 5
C524 0.47uF
C528 330uF/16V
CN502
DOWN3,4
3
2
1
4
5
8
7
6
DP3
DM3
5V
GND
5V
GND
DP4
DM4
C506
0.1uF
C521 0.01uF
X500
6MHz
C523 0.01uF
R505 15K
C525 0.1uF
C522 0.47uF
C504
47PF
C526
1uF
C530 330uF/16V
U502
SOT223
3 4
1
2
VIN VOUT
GND
GND
C50847pF
CN501
DOWN1,2
3
2
1
4
5
8
7
6
DP1
DM1
5V
GND
5V
GND
DP2
DM2
C517
47PF
100R524
R504 22
C515
47PF
F500
miniSMDC075
R525 100
C513 47pF
C51047pF
R527 100
CN522
1
2
3
4
5
+12V
GND
+5V
GND
MUTE
R522 100
C507 47pF
C51447pF
R529 100
RN504
15K
18
27
36
45
C500 100uF/10V
C516
47PF
10K
R523
C509 47pF
R501 240
C50210uF/16V
Q520
TT2N3904D
3
2
1
C512 47pF
C527 330uF/16V
C50110uF/16V
RN501
22
18
27
36
45
U500
19
18
17
15
14
13
31
4
22
27
10
23
3
7
6
8
5
28
9
11
12
1
32
2
29
30
21
20
16
24
26
25
DM3
OVRCUR3
PWRON3
DM2
OVRCUR2
PWRON2
TSTMODE
RESET
OVRCUR4
TSTPLL/48MCLK
OVRCUR1
DM4
VCC
GND
EEDATA/GNDGED
SUBPWR
EECLK
GND
PWRON1
DM1
DP1
DP0
SUSPEND
DM0
XTAL2
XTAL1
PWRON4
DP3
DP2
DP4
EXTMEM
VCC
U520
11
12
17
7
15
3
10
5
9
13
2
1
6
4
16
14
18
20
19
STBY
MUTE
OUTL
VAROUT_R
Vs
GND
SVR
VAROUT_L
INR
GND
GND
GND
VOLUME
INL
Vs
OUTR
GND
GND
GND
C505
0.1uF
CN520
AUDIOJACK
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SELECT
LED_GRN_EN
PWR_SW
6. OSD
6. OSD6. OSD
6. OSD
OUTR
OUTL
MENU
LED_ORANGE_EN
KEY_UP
KEY_DOWN
<Doc> B
<Title>
C
67Friday, January 04, 2002
Title
Size Document Number Rev
Date: Sheet
of
GND
GND
GND
GND
GND
GND
GND
C602 0.1uF
C601 0.1uF
R601 5.1 1/2W
LED600
GREEN AMBER
2
3
1
R604470
CN602
HEADER 4
1
2
3
4
SW600 TACT SW
12
R602
50K
C605
0.01uF
C600 0.1uF
SW604
TACT SW
12
SW603 TACT SW
12
△
▽
JACK600
EARPHONE JACK
1
2
3
4
5
C603 0.1uF
SW601 TACT SW
12
SW602
TACT SW
12
R600 5.1 1/2W
CN600
HEADER 7
1
2
3
4
5
6
7
OUTR
GND
OUTL
GND
VOL
GND
+5V
R603470
C604
0.1uF
CN601
HEADER8
1
2
3
4
5
6
7
8
!" #$%
&&'! (
% &'
!
!" ! #!!
!
)' %!%
!*
!&' !&'*!
-
1
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2
-
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-
4
-
5
-
6
-
7
-
8
-
9
-
10
-
11
-
12
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13
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18
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