SIM MOTOROLA
REFERENCE MANUAL ix
Figure Title Page
1-1 System Integration Module Block Diagram .................................................... 1-2
1-2 SIM Input and Output Signals ........................................................................1-3
3-1 System Configuration and Protection ............................................................. 3-1
3-2 Periodic Interrupt Timer and Software Watchdog Timer ................................ 3-7
4-1 System Clock with 32.768-kHz Reference Crystal ......................................... 4-2
4-2 System Clock with 4.194-MHz Reference Crystal .......................................... 4-3
4-3 Crystal Layout Example ................................................................................. 4-4
4-4 Conditioning the XFC and V
DDSYN
Pins ......................................................... 4-6
5-1 Input Sample Window .................................................................................... 5-5
5-2 Read Cycle Flowchart .................................................................................... 5-9
5-3 Read Cycle Timing Diagram ........................................................................ 5-10
5-4 Write Cycle Flow Chart ................................................................................. 5-11
5-5 Write Cycle Timing Diagram ......................................................................... 5-13
5-6 Read-Modify-Write Timing ............................................................................ 5-14
5-7 Operand Byte Order ..................................................................................... 5-15
5-8 Byte Operand to 8-Bit Port ........................................................................... 5-16
5-9 Byte Operand to 16-Bit Port, Even (ADDR0 = 0) .........................................5-17
5-10 Byte Operand to 16-Bit Port, Odd (ADDR0 = 1) ........................................... 5-17
5-11 Word Operand to 8-Bit Port, Aligned ............................................................ 5-18
5-12 Word Operand to 8-Bit Port, Misaligned ....................................................... 5-19
5-13 Word Operand to 16-Bit Port, Aligned .......................................................... 5-19
5-14 Word Operand to 16-Bit Port, Misaligned ..................................................... 5-20
5-15 Long-Word Operand to 8-Bit Port, Aligned ...................................................5-21
5-16 Timing of a Long-Word Read of an 8-Bit Port .............................................. 5-22
5-17 Timing of a Long-Word Write to an 8-Bit Port .............................................. 5-23
5-18 Long-Word Operand to 8-Bit Port, Misaligned ............................................. 5-24
5-19 Long-Word Operand to 16-Bit Port, Aligned .................................................5-25
5-20 Timing of Long-Word Read or Write, 16-Bit Port .......................................... 5-26
5-21 Long-Word Operand to 16-Bit Port, Misaligned ........................................... 5-27
5-22 Connecting an 8-Bit Memory Device ............................................................ 5-29
5-23 Connecting a 16-Bit Memory Device ............................................................ 5-30
5-24 Connecting Two 8-bit Memory Devices ........................................................ 5-31
5-25 CPU Space Address Encoding ....................................................................5-32
5-26 CPU32 Breakpoint Operation Flow .............................................................. 5-34
5-27 CPU16 Breakpoint Operation Flow .............................................................. 5-35
5-28 Breakpoint Acknowledge Cycle Timing — Opcode Returned (CPU32 Only) 5-36
5-29 Breakpoint Acknowledge Cycle Timing — Exception Signaled ....................5-37
5-30 LPSTOP Interrupt Mask Level ......................................................................5-38
5-31 Bus Error Without DSA
CK ............................................................................ 5-41
5-32 Late Bus Error with DSA
CK .......................................................................... 5-42
5-33 Retry Sequence ............................................................................................5-44
LIST OF ILLUSTRATIONS
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