Infineon CYT2B63BADQ0AZEGS Technical Reference
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TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 2
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TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 3
Contents Overview
Section A: Overview 25
1. Introduction ................................................................................................................... 26
2. Getting Started .............................................................................................................. 33
3. Document Construction ................................................................................................. 36
Section B: CPU Subsystem 39
4. CPU Subsystem (CPUSS) ............................................................................................. 40
5. Inter-Processor Communication ..................................................................................... 45
6. Protection Unit .............................................................................................................. 50
7. Direct Memory Access ................................................................................................... 69
8. Code Flash..................................................................................................................109
9. Work Flash ..................................................................................................................125
10. SRAM Interface ........................................................................................................... 136
11. BootROM ....................................................................................................................143
12. Interrupts .................................................................................................................... 155
13. Device Security ........................................................................................................... 169
14. Chip Operational Modes .............................................................................................. 171
15. Fault Subsystem.......................................................................................................... 173
Section C: System Resources Subsystem (SRSS) 177
16. Power Supply and Monitoring ...................................................................................... 178
17. Device Power Modes ................................................................................................... 187
18. Clocking System.......................................................................................................... 198
19. Reset System .............................................................................................................. 218
20. Watchdog Timer .......................................................................................................... 223
21. Real-Time Clock .......................................................................................................... 240
Section D: Input/Output Subsystem Overview 246
22. I/O System .................................................................................................................. 247
Section E: Digital Subsystem 275
23. CAN FD Controller ...................................................................................................... 276
24. Serial Communications Block (SCB) ............................................................................ 336
25. Timer, Counter, and PWM ............................................................................................ 391
26. Local Interconnect Network (LIN) ................................................................................. 462
27. Cryptography Block ..................................................................................................... 487
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 4
28. Event Generator (EVTGEN) ......................................................................................... 489
29. Trigger Multiplexer....................................................................................................... 498
30. Clock Extension Peripheral Interface (CXPI) ................................................................ 504
Section F: Analog Subsystem 530
31. SAR ADC ....................................................................................................................531
Section G: Program and Debug Overview 560
32. Program and Debug Interface ...................................................................................... 561
33. Nonvolatile Memory Programming ............................................................................... 572
34. Flash Boot................................................................................................................... 609
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 5
Contents
Section A: Overview 25
1. Introduction 26
1.1 Device Characteristics ............................................................................................................26
1.1.1 CPU Subsystem.....................................................................................................26
1.1.2 Communication ......................................................................................................26
1.1.3 Miscellaneous ........................................................................................................26
1.2 Top Level Architecture............................................................................................................27
1.2.1 CPU Subsystem.....................................................................................................28
1.2.1.1 CPU........................................................................................................28
1.2.1.2 DMA Controllers .....................................................................................28
1.2.1.3 Flash.......................................................................................................28
1.2.1.4 SRAM with 32-KB Retention Granularity................................................28
1.2.1.5 ROM .......................................................................................................28
1.2.1.6 Cryptography Accelerator for Security ...................................................28
1.2.2 System Resources.................................................................................................28
1.2.2.1 Power System ........................................................................................28
1.2.2.2 Regulators ..............................................................................................29
1.2.2.3 Clock System .........................................................................................29
1.2.2.4 IMO Clock Source ..................................................................................29
1.2.2.5 ILO Clock Source ...................................................................................29
1.2.2.6 PLL and FLL...........................................................................................29
1.2.2.7 Clock Supervisor ....................................................................................29
1.2.2.8 EXT_CLK ...............................................................................................29
1.2.2.9 ECO........................................................................................................29
1.2.2.10 WCO.......................................................................................................29
1.2.2.11 Reset ......................................................................................................30
1.2.2.12 Watchdog Timers ...................................................................................30
1.2.2.13 Power Modes .........................................................................................30
1.2.3 Peripherals.............................................................................................................30
1.2.3.1 Peripheral Clock Dividers .......................................................................30
1.2.3.2 Peripheral Protection Unit ......................................................................30
1.2.3.3 12-bit SAR ADC .....................................................................................30
1.2.3.4 Timer/Counter/PWM (TCPWM)..............................................................30
1.2.3.5 Serial Communication Blocks (SCB)......................................................31
1.2.3.6 Local lnterconnect Network (LIN) ...........................................................31
1.2.3.7 CAN FD ..................................................................................................31
1.2.3.8 Clock Extension Peripheral Interface (CXPI) .........................................32
1.2.3.9 One-Time-Programmable (OTP) eFuse.................................................32
1.2.3.10 Event Generator .....................................................................................32
1.2.3.11 Trigger Multiplexer..................................................................................32
1.2.4 I/Os ........................................................................................................................32
1.2.4.1 GPIO ......................................................................................................32
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 6
1.2.4.2 Drive Modes ...........................................................................................32
1.2.4.3 Port Nomenclature: ................................................................................32
1.2.4.4 Smart I/O ................................................................................................32
2. Getting Started 33
2.1 Support ...................................................................................................................................33
2.2 Product Upgrades...................................................................................................................33
2.3 Development Kits....................................................................................................................33
2.3.1 Starter Kit ...............................................................................................................33
2.3.2 Evaluation Board....................................................................................................34
2.3.3 Base Board ............................................................................................................34
2.3.4 Sample Driver Library (SDL)..................................................................................35
2.3.5 Development Tools ................................................................................................35
2.3.6 Cypress Auto-Flash Utility (AFU) ...........................................................................35
2.4 Application Notes....................................................................................................................35
3. Document Construction 36
3.1 Major Sections ........................................................................................................................36
3.2 Documentation Conventions...................................................................................................36
3.2.1 Register Conventions.............................................................................................36
3.2.2 Numeric Naming ....................................................................................................36
3.2.3 Units of Measure....................................................................................................37
3.2.4 Acronyms and Abbreviations .................................................................................37
Section B: CPU Subsystem 39
Top Level Architecture .....................................................................................................................39
4. CPU Subsystem (CPUSS) 40
4.1 Features..................................................................................................................................40
4.2 How It Works ..........................................................................................................................40
4.3 Address Map...........................................................................................................................41
4.4 Registers.................................................................................................................................41
4.5 Operating Modes and Privilege Levels ...................................................................................44
4.6 Instruction Set.........................................................................................................................44
5. Inter-Processor Communication 45
5.1 Features..................................................................................................................................45
5.1.1 IPC Channel...........................................................................................................45
5.1.2 IPC Interrupt...........................................................................................................46
5.1.3 IPC Channels and Interrupts..................................................................................46
5.2 Implementing Locks................................................................................................................47
5.3 Message Passing ...................................................................................................................47
5.4 Registers.................................................................................................................................49
6. Protection Unit 50
6.1 Features..................................................................................................................................50
6.2 Configuration ..........................................................................................................................51
6.2.1 Block Diagram........................................................................................................51
6.2.2 Protection Unit Structure........................................................................................51
6.2.3 Master with Missing Access Attributes ...................................................................52
6.3 Protection Context ..................................................................................................................52
6.3.1 Protection Context Configuration ...........................................................................52
6.3.2 Protection Context 0 and 1 ....................................................................................53
6.4 Protection Structure ................................................................................................................53
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 7
6.4.1 Address Region .....................................................................................................53
6.4.2 Access Control Attributes.......................................................................................54
6.4.3 Protection Violation ................................................................................................55
6.4.4 Protection of Protection Structures ........................................................................55
6.4.5 MPU .......................................................................................................................57
6.4.6 SMPU.....................................................................................................................57
6.4.7 PPU........................................................................................................................58
6.4.7.1 ECC for SRAM .......................................................................................58
6.4.7.2 ECC Error Injection ................................................................................59
6.4.7.3 ECC Parity Generation by Software.......................................................59
6.4.8 Protection Structure Types.....................................................................................60
6.5 SWPU .....................................................................................................................................63
6.5.1 SWPU Layout ........................................................................................................63
6.5.2 SWPU Configuration..............................................................................................65
6.6 Registers.................................................................................................................................67
7. Direct Memory Access 69
7.1 Peripheral DMA (P-DMA) .......................................................................................................69
7.1.1 Overview ................................................................................................................69
7.1.2 Channels................................................................................................................70
7.1.3 Descriptors.............................................................................................................71
7.1.4 Interrupts................................................................................................................73
7.1.5 P-DMA Controller Status Registers........................................................................74
7.1.6 P-DMA Controller Design.......................................................................................74
7.1.6.1 P-DMA channel configuration SRAMs ...................................................76
7.1.6.2 ECC for P-DMA Channel Configuration SRAMs ....................................76
7.1.7 Functionality...........................................................................................................78
7.1.8 P-DMA Descriptor Structure...................................................................................80
7.2 Memory DMA (M-DMA) ..........................................................................................................83
7.2.1 Overview ................................................................................................................83
7.2.2 Channels................................................................................................................83
7.2.3 Descriptors.............................................................................................................84
7.2.4 Interrupts................................................................................................................87
7.2.5 Control and Active Registers..................................................................................87
7.2.6 M-DMA Controller Design ......................................................................................87
7.2.7 Examples ...............................................................................................................88
7.2.8 M-DMA Descriptor Structure ..................................................................................89
7.3 AXI DMA .................................................................................................................................93
7.3.1 Overview ................................................................................................................94
7.3.2 Channels................................................................................................................94
7.3.3 Descriptors.............................................................................................................96
7.3.4 Interrupts................................................................................................................98
7.3.5 Control, Status, and Active Registers ....................................................................99
7.3.6 Rules for Generating AXI Transactions..................................................................99
7.3.7 AXI DMA Controller Design....................................................................................99
7.3.8 Examples .............................................................................................................100
7.3.9 AXI DMA Descriptor Structure .............................................................................101
7.4 Registers...............................................................................................................................105
8. Code Flash 109
8.1 Features................................................................................................................................109
8.2 Configuration ........................................................................................................................109
8.2.1 Block Diagram......................................................................................................109
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 8
8.2.2 Flash Controller....................................................................................................110
8.2.2.1 Bus Error ..............................................................................................111
8.2.2.2 Wait Cycle Count..................................................................................112
8.2.2.3 Power Modes .......................................................................................112
8.2.2.4 CM0+ and CM4 CPU Caches ..............................................................112
8.2.2.5 Code Flash ECC ..................................................................................114
8.2.2.6 Software Generating Code Flash ECC ................................................116
8.2.2.7 Cache ECC ..........................................................................................116
8.2.2.8 Software Generating Cache ECC ........................................................117
8.2.3 Flash Geometry ...................................................................................................117
8.2.3.1 Interface, Regions, and Type of Use....................................................117
8.2.3.2 Geometries...........................................................................................118
8.2.3.3 Logical Bank.........................................................................................119
8.2.4 OTA – Over The Air Support ................................................................................119
8.2.4.1 Dual Bank Mode and Remap Functionality ..........................................119
8.2.5 Address Map of Code Flash ................................................................................120
8.2.5.1 Address Mapping for 512 KB Memory .................................................120
8.2.5.2 Address Mapping for 1 MB Memory.....................................................121
8.2.5.3 Address Mapping for 2 MB Memory.....................................................122
8.3 Operation ..............................................................................................................................123
8.3.1 SROM APIs..........................................................................................................123
8.4 Registers...............................................................................................................................123
9. Work Flash 125
9.1 Features................................................................................................................................125
9.2 Configuration ........................................................................................................................125
9.2.1 Block Diagram......................................................................................................125
9.2.2 Flash Controller....................................................................................................126
9.2.2.1 Bus Error ..............................................................................................126
9.2.2.2 Work Flash ECC...................................................................................127
9.2.2.3 Software Generating Work Flash ECC.................................................128
9.2.3 Flash Geometry ...................................................................................................128
9.2.3.1 Interface, Regions, and Type of Use....................................................128
9.2.3.2 Geometries...........................................................................................129
9.2.3.3 Logical Bank.........................................................................................130
9.2.4 Over-the-Air (OTA) Support .................................................................................130
9.2.4.1 Dual Bank Mode and Remap Functionality ..........................................130
9.2.5 Address Map of Work Flash.................................................................................131
9.2.5.1 Address Mapping for 64 KB Memory ...................................................131
9.2.5.2 Address Mapping for 96 KB Memory ...................................................132
9.2.5.3 Address Mapping for 128 KB Memory .................................................133
9.3 Operation ..............................................................................................................................134
9.3.1 Read ....................................................................................................................134
9.3.2 SROM APIs..........................................................................................................134
9.4 Registers...............................................................................................................................135
10. SRAM Interface 136
10.1 Features................................................................................................................................136
10.2 Configuration ........................................................................................................................137
10.2.1 Block Diagram......................................................................................................137
10.2.2 Wait States...........................................................................................................138
10.2.3 Operation .............................................................................................................138
10.2.4 Write Buffer ..........................................................................................................139
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 9
10.3 ECC Details ..........................................................................................................................139
10.3.1 ECC Parity Generation for SRAM Write Accesses ..............................................139
10.3.2 ECC Syndrome Generation for SRAM Read Accesses.......................................139
10.3.3 ECC Error Injection ..............................................................................................140
10.3.4 ECC Parity Generation by Software ....................................................................140
10.4 RAM Retention Configuration ...............................................................................................141
10.5 Registers...............................................................................................................................142
11. BootROM 143
11.1 Features................................................................................................................................143
11.2 ROM Controller.....................................................................................................................143
11.2.1 Wait States...........................................................................................................143
11.3 ROM Boot Process ...............................................................................................................144
11.3.1 Life-Cycle Stages and Protection States .............................................................144
11.3.2 Multicore Boot ......................................................................................................144
11.3.3 Secure Boot .........................................................................................................144
11.3.4 Protection Setting.................................................................................................144
11.3.4.1 SMPU Configuration in SFlash.............................................................144
11.3.4.2 SWPU Configuration in SFlash ............................................................145
11.3.4.3 PPU Configuration in SFlash................................................................145
11.3.4.4 Boot Protection Settings in SFlash.......................................................148
11.3.4.5 Security Enhancement PPU Configuration in SFlash ..........................149
11.3.5 Debug and Test Access Restrictions....................................................................150
11.3.6 SWD/JTAG Initialization.......................................................................................150
11.3.7 Waking up from Hibernate ...................................................................................150
11.3.8 ROM Boot Flow Chart..........................................................................................151
11.4 MMIO Registers and eFuse Used by ROM Boot..................................................................152
11.4.1 MMIO Registers ...................................................................................................152
11.4.2 eFuse Bits ............................................................................................................153
12. Interrupts 155
12.1 Features................................................................................................................................155
12.2 How It Works ........................................................................................................................156
12.3 Interrupts and Exceptions – Operation .................................................................................157
12.3.1 Interrupt/Exception Handling................................................................................157
12.3.2 Level Interrupts ....................................................................................................157
12.3.3 Exception Vector Table ........................................................................................158
12.4 Exception Sources................................................................................................................160
12.4.1 Reset Exception...................................................................................................160
12.4.2 Non-Maskable Interrupt Exception.......................................................................160
12.4.3 HardFault Exception ............................................................................................160
12.4.4 Memory Management Fault Exception ................................................................160
12.4.5 Bus Fault Exception .............................................................................................160
12.4.6 Usage Fault Exception.........................................................................................160
12.4.7 Supervisor Call (SVCall) Exception .....................................................................161
12.4.8 PendSV Exception ...............................................................................................161
12.4.9 SysTick Exception................................................................................................161
12.5 Interrupt Sources ..................................................................................................................161
12.6 Exception Priority..................................................................................................................163
12.7 Enabling and Disabling Interrupts.........................................................................................163
12.8 Exception States...................................................................................................................164
12.8.1 Pending Exceptions .............................................................................................164
12.9 Stack Usage for Exceptions..................................................................................................165
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 10
12.10 Interrupts and Low-Power Modes.........................................................................................165
12.11 Exception – Initialization and Configuration..........................................................................165
12.12 Registers...............................................................................................................................166
13. Device Security 169
13.1 Features................................................................................................................................169
13.2 How It Works ........................................................................................................................169
13.2.1 Life-Cycle Stages.................................................................................................169
13.2.2 Memory and Peripheral Protection ......................................................................170
13.2.3 Flash Write and eFuse Read/Write Protection.....................................................170
13.2.4 Hardware-based Cryptography............................................................................170
14. Chip Operational Modes 171
14.1 Boot ......................................................................................................................................171
14.2 User ......................................................................................................................................171
14.3 Trusted..................................................................................................................................171
14.4 Debug ...................................................................................................................................172
15. Fault Subsystem 173
15.1 Fault Report Structure ..........................................................................................................174
15.2 Fault and Reset ....................................................................................................................175
15.3 Fault and Power Modes........................................................................................................175
15.4 Register List..........................................................................................................................176
Section C: System Resources Subsystem (SRSS) 177
Top Level Architecture ...................................................................................................................177
16. Power Supply and Monitoring 178
16.1 Features................................................................................................................................178
16.2 Power Supply........................................................................................................................178
16.2.1 Core Regulators...................................................................................................179
16.2.2 Power Pins and Rails...........................................................................................180
16.2.3 Power Sequencing Requirements .......................................................................180
16.2.4 Power Supply Sources.........................................................................................180
16.3 Voltage Monitoring................................................................................................................181
16.3.1 Power-On-Reset (POR) .......................................................................................181
16.3.2 Brownout-Detection (BOD) ..................................................................................181
16.3.2.1 BOD on VDDD .....................................................................................181
16.3.2.2 BOD on VDDA......................................................................................181
16.3.2.3 BOD on VCCD .....................................................................................181
16.3.3 Over-Voltage Detection (OVD).............................................................................182
16.3.3.1 OVD on VDDD .....................................................................................182
16.3.3.2 OVD on VDDA......................................................................................182
16.3.3.3 OVD on VCCD .....................................................................................182
16.3.4 Low-Voltage-Detection (LVD)...............................................................................182
16.3.5 Over-Current Detection........................................................................................183
16.3.6 Voltage Monitoring by ADC ..................................................................................183
16.4 Register List..........................................................................................................................186
17. Device Power Modes 187
17.1 Features................................................................................................................................187
17.2 Device Power Modes............................................................................................................188
17.2.1 Active and Sleep Modes ......................................................................................188
17.2.1.1 Low-Power Profiles - LPACTIVE and LPSLEEP..................................188
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 11
17.2.2 DeepSleep Mode .................................................................................................189
17.2.3 Hibernate Mode ...................................................................................................189
17.2.4 Other Operational States .....................................................................................190
17.2.4.1 XRES/OFF State ..................................................................................190
17.2.4.2 Reset ....................................................................................................190
17.3 Power Mode Transitions .......................................................................................................191
17.3.1 Power-up Transitions ...........................................................................................192
17.3.2 Low-Power Mode Transition ................................................................................192
17.3.3 Wakeup................................................................................................................195
17.3.4 Internal Reset Transitions ....................................................................................195
17.3.5 Powering Down/Brownout/Overvoltage ...............................................................195
17.3.6 Debugger Effect on Device Power Modes ...........................................................195
17.4 Summary ..............................................................................................................................196
17.5 Register List..........................................................................................................................197
18. Clocking System 198
18.1 Block Diagram ......................................................................................................................199
18.2 Clock Sources.......................................................................................................................199
18.2.1 Internal Main Oscillator (IMO) ..............................................................................199
18.2.2 External Crystal Oscillator (ECO) ........................................................................200
18.2.2.1 ECO Trimming......................................................................................200
18.2.3 External Clock (EXT_CLK) ..................................................................................201
18.2.4 Internal Low-speed Oscillator (ILO) .....................................................................201
18.2.5 Watch Crystal Oscillator (WCO)...........................................................................202
18.2.6 ECO Prescaler .....................................................................................................202
18.2.7 LPECO.................................................................................................................202
18.2.8 LPECO Prescaler.................................................................................................202
18.3 Clock Generation ..................................................................................................................202
18.3.1 PLL Without SSCG and Fractional Operation......................................................202
18.3.2 PLL with SSCG and Fractional Operation (400-MHz PLL) ..................................203
18.3.2.1 Spread Spectrum Clock Generation (SSCG) .......................................203
18.3.2.2 Fractional Operation.............................................................................204
18.3.3 Frequency-Locked Loop (FLL).............................................................................205
18.4 Clock Trees...........................................................................................................................206
18.4.1 Path Clocks..........................................................................................................206
18.4.2 High-Frequency Root Clocks ...............................................................................207
18.4.3 Low-Frequency Root Clocks................................................................................207
18.4.4 Timer Clock..........................................................................................................207
18.4.5 Clock Output Function .........................................................................................208
18.5 CLK_HF Distribution .............................................................................................................208
18.5.1 CLK_FAST ...........................................................................................................208
18.5.2 CLK_PERI............................................................................................................208
18.5.3 CLK_SLOW .........................................................................................................208
18.5.4 PCLK....................................................................................................................208
18.5.5 CLK_GR...............................................................................................................208
18.6 Peripheral Clock Dividers .....................................................................................................208
18.6.1 Fractional Clock Dividers .....................................................................................209
18.6.2 Peripheral Clock Divider Configuration ................................................................209
18.6.2.1 Phase Aligning Dividers .......................................................................209
18.7 Clock Calibration Counters ...................................................................................................210
18.8 Clock Supervision (CSV) ......................................................................................................211
18.8.1 Overview ..............................................................................................................211
18.8.2 CSV Operation.....................................................................................................213
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 12
18.9 Registers...............................................................................................................................215
19. Reset System 218
19.1 Reset Sources ......................................................................................................................219
19.1.1 Power-on Reset ...................................................................................................219
19.1.2 Brownout Detection Reset ...................................................................................219
19.1.3 Over-Voltage Detection Reset .............................................................................219
19.1.4 Over-Current Reset..............................................................................................220
19.1.5 External Reset .....................................................................................................220
19.1.6 Watchdog Timer Reset ........................................................................................220
19.1.7 Internal System Reset..........................................................................................220
19.1.8 Fault Detection Reset ..........................................................................................220
19.1.9 Clock-Supervision Reset......................................................................................220
19.1.10 Hibernate Wakeup Reset .....................................................................................220
19.1.11 PMIC Reset..........................................................................................................220
19.2 Identifying Reset Sources.....................................................................................................221
19.3 Register List..........................................................................................................................222
20. Watchdog Timer 223
20.1 Features................................................................................................................................223
20.2 Block Diagram ......................................................................................................................224
20.3 Basic Watchdog Timer..........................................................................................................224
20.3.1 Overview ..............................................................................................................224
20.3.2 Watchdog Reset ..................................................................................................227
20.3.3 Watchdog Interrupt ..............................................................................................228
20.4 Multi-Counter Watchdog Timer.............................................................................................229
20.4.1 Overview ..............................................................................................................229
20.4.2 How It Works........................................................................................................230
20.4.2.1 Subcounter 0/1 Operation ....................................................................230
20.4.2.2 32-bit Counter Operation......................................................................233
20.4.3 Enabling and Disabling MCWDT .........................................................................235
20.4.4 Watchdog Reset ..................................................................................................236
20.4.5 Watchdog Interrupt ..............................................................................................236
20.5 Reset Cause Detection.........................................................................................................237
20.6 Debug Mode .........................................................................................................................237
20.7 CPU Select ...........................................................................................................................238
20.8 Register List..........................................................................................................................238
21. Real-Time Clock 240
21.1 Features................................................................................................................................240
21.2 Block Diagram ......................................................................................................................241
21.3 Power Supply........................................................................................................................241
21.4 Clocking ................................................................................................................................241
21.5 Reset ....................................................................................................................................242
21.6 Real-Time Clock ...................................................................................................................242
21.6.1 Reading RTC User Registers ..............................................................................243
21.6.2 Writing to RTC User Registers.............................................................................243
21.7 WCO/LPECO Calibration......................................................................................................243
21.7.1 Absolute Accuracy Calibration .............................................................................243
21.8 Alarm Feature .......................................................................................................................244
21.9 Backup Registers..................................................................................................................245
21.10 Real Time Clock Registers ...................................................................................................245
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 13
Section D: Input/Output Subsystem Overview 246
Top Level Architecture ...................................................................................................................246
22. I/O System 247
22.1 Features................................................................................................................................247
22.2 GPIO Interface Overview......................................................................................................247
22.3 I/O Cell Architecture..............................................................................................................249
22.4 High Speed I/O (HSIO) .........................................................................................................250
22.5 Digital Input Buffer ................................................................................................................250
22.6 Digital Output Driver .............................................................................................................251
22.6.1 Drive Modes.........................................................................................................251
22.6.2 Slew Rate Control ................................................................................................253
22.7 High-Speed I/O Matrix ..........................................................................................................256
22.8 I/O State on Power Up..........................................................................................................257
22.9 Behavior in Low-Power Modes .............................................................................................257
22.10 Interrupt ................................................................................................................................258
22.11 Peripheral Connections ........................................................................................................259
22.11.1 Firmware-Controlled GPIO ..................................................................................259
22.11.2 Analog I/O ............................................................................................................260
22.11.3 Serial Communication Block (SCB) .....................................................................260
22.12 Smart I/O ..............................................................................................................................260
22.12.1 Overview ..............................................................................................................260
22.12.2 Block Components...............................................................................................261
22.12.2.1 Clock and Reset ...................................................................................261
22.12.2.2 Synchronizer ........................................................................................262
22.12.2.3 LUT3.....................................................................................................262
22.12.2.4 Data Unit ..............................................................................................265
22.12.3 Routing.................................................................................................................268
22.12.4 Operation .............................................................................................................268
22.12.5 Example Application.............................................................................................269
22.13 Registers...............................................................................................................................273
Section E: Digital Subsystem 275
Top Level Architecture ...................................................................................................................275
23. CAN FD Controller 276
23.1 Overview...............................................................................................................................276
23.1.1 Features...............................................................................................................276
23.1.2 Features Not Supported.......................................................................................277
23.2 Configuration ........................................................................................................................277
23.2.1 Block Diagram......................................................................................................277
23.2.2 Dual Clock Sources .............................................................................................277
23.2.3 Interrupt Lines ......................................................................................................277
23.3 Functional Description ..........................................................................................................278
23.3.1 Operation Modes .................................................................................................278
23.3.1.1 Software Initialization ...........................................................................278
23.3.1.2 Normal Operation .................................................................................279
23.3.1.3 CAN FD Operation ...............................................................................279
23.3.1.4 Transmitter Delay Compensation.........................................................280
23.3.1.5 Restricted Operation mode ..................................................................281
23.3.1.6 Bus Monitoring Mode ...........................................................................282
23.3.1.7 Disable Automatic Retransmission.......................................................282
23.3.1.8 Power Down (Sleep Mode) ..................................................................282
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 14
23.3.1.9 Test Mode ............................................................................................282
23.3.1.10 Application Watchdog...........................................................................283
23.3.2 Timestamp Generation ........................................................................................283
23.3.3 Timeout Counter ..................................................................................................284
23.3.4 RX Handling.........................................................................................................285
23.3.4.1 Acceptance Filtering.............................................................................285
23.3.4.2 RX FIFOs .............................................................................................287
23.3.4.3 Dedicated RX Buffers...........................................................................289
23.3.4.4 Debug on CAN Support........................................................................290
23.3.5 TX Handling .........................................................................................................291
23.3.5.1 Transmit Pause ....................................................................................291
23.3.5.2 Dedicated TX Buffers ...........................................................................291
23.3.5.3 TX FIFO................................................................................................292
23.3.5.4 TX Queue.............................................................................................292
23.3.5.5 Mixed Dedicated TX Buffers/TX FIFO..................................................292
23.3.5.6 Mixed Dedicated TX Buffers/TX Queue ...............................................293
23.3.5.7 Transmit Cancellation...........................................................................293
23.3.5.8 TX Event Handling ...............................................................................293
23.3.6 FIFO Acknowledge Handling ...............................................................................294
23.3.7 Configuring the CAN Bit Timing ...........................................................................294
23.3.7.1 CAN Bit Timing.....................................................................................294
23.3.7.2 CAN Bit Rates ......................................................................................296
23.4 Message RAM ......................................................................................................................298
23.4.1 Message RAM Configuration ...............................................................................298
23.4.2 RX Buffer and FIFO Element ...............................................................................298
23.4.3 TX Buffer Element................................................................................................300
23.4.4 TX Event FIFO Element.......................................................................................301
23.4.5 Standard Message ID Filter Element ...................................................................302
23.4.6 Extended Message ID Filter Element ..................................................................304
23.4.7 Trigger Memory Element .....................................................................................305
23.4.8 ECC for Message RAM........................................................................................307
23.4.8.1 Correctable ECC Error .........................................................................307
23.4.8.2 Non-correctable ECC Error ..................................................................307
23.4.8.3 Address Error .......................................................................................307
23.4.8.4 ECC Error Injection ..............................................................................308
23.4.8.5 ECC Parity Generation by software .....................................................308
23.4.9 Message RAM OFF .............................................................................................309
23.4.10 RAM Watchdog (RWD) ........................................................................................309
23.5 TTCAN Operation .................................................................................................................309
23.5.1 Reference Message.............................................................................................309
23.5.1.1 Level 1..................................................................................................309
23.5.1.2 Level 2..................................................................................................309
23.5.1.3 Level 0..................................................................................................309
23.5.2 TTCAN Configuration...........................................................................................310
23.5.2.1 TTCAN Timing......................................................................................310
23.5.2.2 Message Scheduling ............................................................................311
23.5.2.3 Trigger Memory ....................................................................................312
23.5.2.4 TTCAN Schedule Initialization..............................................................314
23.5.3 TTCAN Gap Control.............................................................................................315
23.5.4 Stop Watch ..........................................................................................................316
23.5.5 Local Time, Cycle Time, Global Time, and External Clock Synchronization........316
23.5.6 Synchronization Triggers .....................................................................................318
23.5.7 TTCAN Error Level ..............................................................................................319
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 15
23.5.8 TTCAN Message Handling ..................................................................................320
23.5.8.1 Reference Message .............................................................................320
23.5.8.2 Message Reception..............................................................................320
23.5.8.3 Message Transmission ........................................................................320
23.5.9 TTCAN Interrupt and Error Handling ...................................................................321
23.5.10 Level 0 .................................................................................................................322
23.5.10.1 Synchronizing.......................................................................................322
23.5.10.2 Handling Error Levels...........................................................................323
23.5.10.3 Master Slave Relation ..........................................................................323
23.5.11 Synchronization to External Time Schedule ........................................................323
23.6 Setup Procedures .................................................................................................................324
23.6.1 General Program Flow.........................................................................................324
23.6.2 Clock Stop Request .............................................................................................324
23.6.3 Message RAM OFF Operation ............................................................................324
23.6.4 Message RAM ON Operation ..............................................................................324
23.6.5 Consolidated Interrupt Handling ..........................................................................325
23.6.6 Procedures Specific to M_TTCAN Channel.........................................................325
23.6.6.1 CAN Bus Configuration ........................................................................326
23.6.6.2 Message RAM Configuration ...............................................................326
23.6.6.3 Interrupt Configuration..........................................................................328
23.6.6.4 Transmit Frame Configuration..............................................................329
23.6.6.5 Interrupt Handling.................................................................................330
23.7 Registers...............................................................................................................................333
24. Serial Communications Block (SCB) 336
24.1 Features................................................................................................................................336
24.2 Block Diagram ......................................................................................................................337
24.2.1 AHB-Lite Bus Interface ........................................................................................337
24.2.2 Trigger Interface...................................................................................................337
24.2.2.1 DMA/DW Trigger Signals .....................................................................337
24.2.2.2 tr_i2c_scl_filtered Signal ......................................................................338
24.2.3 Serial Protocol Interfaces.....................................................................................338
24.2.4 Clock and Reset Interface....................................................................................338
24.2.5 Block Enable ........................................................................................................338
24.2.6 Interrupt Interface.................................................................................................338
24.3 Operation Modes ..................................................................................................................340
24.3.1 Buffer Modes........................................................................................................340
24.3.1.1 FIFO Mode ...........................................................................................341
24.3.1.2 EZ Mode...............................................................................................341
24.3.1.3 CMD_RESP Mode ...............................................................................341
24.3.2 Clocking Modes ...................................................................................................341
24.4 Serial Peripheral Interface (SPI) ...........................................................................................343
24.4.1 Features...............................................................................................................343
24.4.2 General Description .............................................................................................343
24.4.3 SPI Modes of Operation.......................................................................................344
24.4.3.1 Motorola SPI.........................................................................................344
24.4.3.2 Texas Instruments SPI .........................................................................346
24.4.3.3 National Semiconductors SPI...............................................................347
24.4.4 SPI Buffer Modes.................................................................................................348
24.4.4.1 FIFO Mode ...........................................................................................348
24.4.4.2 EZSPI Mode .........................................................................................349
24.4.4.3 Command-Response Mode .................................................................351
24.4.5 Clocking and Oversampling .................................................................................352
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 16
24.4.5.1 Clock Modes.........................................................................................352
24.4.5.2 Using SPI Master to Clock Slave .........................................................354
24.4.5.3 Oversampling and Bit Rate ..................................................................354
24.4.6 SPI Master SELECT Output Timing Control ........................................................355
24.4.7 SPI Parity Functionality........................................................................................356
24.4.8 Loop-back ............................................................................................................356
24.4.9 Enabling and Initializing SPI ................................................................................356
24.4.10 I/O Pad Connection..............................................................................................357
24.4.10.1 SPI Master............................................................................................357
24.4.10.2 SPI Slave..............................................................................................358
24.4.11 SPI Registers .......................................................................................................359
24.5 UART ....................................................................................................................................360
24.5.1 Features...............................................................................................................360
24.5.2 General Description .............................................................................................360
24.5.3 UART Modes of Operation...................................................................................360
24.5.3.1 Standard Protocol.................................................................................360
24.5.3.2 UART Multi-Processor Mode................................................................365
24.5.3.3 UART Local Interconnect Network (LIN) Mode ....................................365
24.5.3.4 SmartCard (ISO7816) ..........................................................................368
24.5.3.5 IrDA ......................................................................................................369
24.5.4 Clocking and Oversampling .................................................................................370
24.5.5 Loop-back ............................................................................................................370
24.5.6 Enabling and Initializing UART ............................................................................370
24.5.7 I/O Pad Connection..............................................................................................371
24.5.7.1 Standard UART Mode ..........................................................................371
24.5.7.2 SmartCard Mode ..................................................................................372
24.5.7.3 LIN Mode..............................................................................................373
24.5.7.4 IrDA Mode ............................................................................................373
24.5.8 UART Registers ...................................................................................................373
24.6 Inter Integrated Circuit (I2C) .................................................................................................374
24.6.1 Features...............................................................................................................374
24.6.2 General Description .............................................................................................374
24.6.3 Terms and Definitions ..........................................................................................374
24.6.3.1 Clock Stretching ...................................................................................375
24.6.3.2 Bus Arbitration......................................................................................375
24.6.4 I2C Modes of Operation.......................................................................................375
24.6.4.1 Write Transfer.......................................................................................376
24.6.4.2 Read Transfer ......................................................................................376
24.6.5 I2C Buffer Modes .................................................................................................377
24.6.5.1 FIFO Mode ...........................................................................................377
24.6.5.2 EZI2C Mode .........................................................................................378
24.6.5.3 Command-Response Mode .................................................................379
24.6.6 Clocking and Oversampling .................................................................................380
24.6.6.1 Glitch Filtering ......................................................................................381
24.6.6.2 Oversampling and Bit Rate ..................................................................382
24.6.7 Loop-back ............................................................................................................383
24.6.8 Enabling and Initializing the I2C...........................................................................383
24.6.8.1 Configuring for I2C FIFO Mode ............................................................383
24.6.8.2 Configuring for EZ and CMD_RESP Modes ........................................384
24.6.9 I/O Pad Connections............................................................................................384
24.6.10 I2C Registers .......................................................................................................384
24.7 SCB Interrupts ......................................................................................................................385
24.7.1 SPI Interrupts .......................................................................................................385
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 17
24.7.2 UART Interrupts ...................................................................................................386
24.7.3 I2C Interrupts .......................................................................................................386
24.8 Registers...............................................................................................................................388
24.8.1 SPI Registers .......................................................................................................388
24.8.2 UART Registers ...................................................................................................389
24.8.3 I2C Registers .......................................................................................................389
25. Timer, Counter, and PWM 391
25.1 Features................................................................................................................................391
25.2 Block Diagram ......................................................................................................................392
25.2.1 Enabling and Disabling Counters in TCPWM Block ............................................392
25.2.2 Clocking ...............................................................................................................392
25.2.2.1 Clock Prescaling...................................................................................393
25.2.2.2 Count Event..........................................................................................393
25.2.3 Trigger Inputs.......................................................................................................393
25.2.4 Synchronization of Multiple Counters ..................................................................397
25.2.5 Trigger Outputs ....................................................................................................399
25.2.6 Internal Events .....................................................................................................400
25.2.6.1 Underflow Event ...................................................................................400
25.2.6.2 Overflow Event .....................................................................................400
25.2.6.3 TC Event ..............................................................................................401
25.2.6.4 cc0_match (cc1_match) Event .............................................................401
25.2.7 Interrupts..............................................................................................................403
25.2.8 Debug Mode ........................................................................................................403
25.2.9 PWM Outputs.......................................................................................................403
25.2.10 Power Modes .......................................................................................................406
25.3 Operation Modes ..................................................................................................................406
25.3.1 Timer Mode..........................................................................................................407
25.3.1.1 Configuring Counter for Timer Mode....................................................413
25.3.2 Capture Mode ......................................................................................................413
25.3.2.1 Configuring Counter for Capture Mode ................................................416
25.3.3 Quadrature Decoder Mode ..................................................................................417
25.3.3.1 Quadrature QUAD_RANGE0 Mode .....................................................420
25.3.3.2 Configuring Counter for Quadrature Mode (QUAD_RANGE0 mode) ..422
25.3.3.3 Quadrature QUAD_RANGE0_CMP Mode ...........................................423
25.3.3.4 Quadrature QUAD_RANGE1_CMP Mode ...........................................425
25.3.3.5 Quadrature QUAD_RANGE1_CAPT Mode .........................................427
25.3.4 Pulse Width Modulation (PWM) Mode .................................................................428
25.3.4.1 PWM Mode Functionalities...................................................................431
25.3.4.2 Configuring Counter for PWM Mode for Stepper Motor Control (SMC) .....
444
25.3.4.3 Configuring Counter for PWM Mode ....................................................450
25.3.5 Pulse Width Modulation with Dead Time Mode ...................................................450
25.3.5.1 Configuring Counter for PWM with Dead Time Mode ..........................452
25.3.6 Pulse Width Modulation Pseudo-Random Mode (PWM PR) ...............................452
25.3.6.1 Configuring Counter for Pseudo-Random PWM Mode ........................457
25.3.7 Shift Register (SR) ...............................................................................................457
25.3.7.1 SR Mode Functionality Overview .........................................................458
25.3.7.2 Features of SR Mode ...........................................................................459
25.4 Design Configuration Parameters.........................................................................................460
25.5 Recovery...............................................................................................................................460
25.6 Initialize.................................................................................................................................460
25.7 Pin Status .............................................................................................................................460
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 18
25.8 TCPWM Registers ................................................................................................................461
26. Local Interconnect Network (LIN) 462
26.1 Features................................................................................................................................462
26.1.1 LIN .......................................................................................................................462
26.1.2 UART ...................................................................................................................462
26.2 Block Diagram ......................................................................................................................463
26.2.1 Internal Bus Interface...........................................................................................463
26.2.2 Test Registers ......................................................................................................463
26.2.3 LIN Channel .........................................................................................................463
26.3 Clocking ................................................................................................................................463
26.3.1 Baud Rate and Sample Point...............................................................................463
26.3.1.1 Baud Rate Calculation for LIN Master and Fixed LIN Slave Clock ......464
26.3.1.2 Baud Rate Calculation Adjusted LIN Slave Clock ................................464
26.3.1.3 Example: Master ..................................................................................464
26.4 LIN Message Frame Format.................................................................................................465
26.4.1 Break and Synchronization Fields .......................................................................465
26.4.2 PID Field ..............................................................................................................466
26.4.3 Response Space..................................................................................................466
26.4.4 Data Fields...........................................................................................................466
26.4.4.1 Response Transmission (LINx_CHy_CMD.TX_RESPONSE) .............466
26.4.4.2 Response Reception (LINx_CHy_CMD.RX_RESPONSE) ..................467
26.4.5 Checksum Field ...................................................................................................467
26.4.5.1 Response Transmission (LINx_CHy_CMD.TX_RESPONSE) .............467
26.4.5.2 Response Reception (LINx_CHy_CMD.RX_RESPONSE) ..................467
26.5 Timeout Operation ................................................................................................................467
26.6 Wakeup.................................................................................................................................467
26.6.1 Wakeup Signal Transmission...............................................................................467
26.6.2 Wakeup Signal Reception....................................................................................468
26.6.3 Wake up in Low Power Mode ..............................................................................468
26.7 External Transceiver Control ................................................................................................468
26.8 Test Modes ...........................................................................................................................468
26.8.1 Interrupt Test ........................................................................................................468
26.8.2 Loop-back Mode ..................................................................................................468
26.8.2.1 Partial Disconnect Mode ......................................................................468
26.8.2.2 Full Disconnect Mode...........................................................................468
26.8.3 Error Injection Mode.............................................................................................469
26.9 Operation ..............................................................................................................................470
26.9.1 LIN Operation.......................................................................................................470
26.9.1.1 LIN Message Transfer..........................................................................470
26.9.1.2 LIN Software Flow Chart ......................................................................472
26.9.2 UART Operation ..................................................................................................474
26.9.2.1 Transmission ........................................................................................474
26.9.2.2 Reception .............................................................................................474
26.9.2.3 Extended Features ...............................................................................474
26.9.2.4 Multiple Transfer...................................................................................474
26.10 Noise Filter............................................................................................................................474
26.10.1 Example ...............................................................................................................474
26.11 Interrupts...............................................................................................................................477
26.11.1 Overview ..............................................................................................................477
26.11.2 Transmission Interrupts .......................................................................................480
26.11.2.1 TX Header Done ..................................................................................480
26.11.2.2 TX Response Done ..............................................................................480
TRAVEO™ T2G Architecture TRM, Document No. 002-19314 Rev. *H 19
26.11.2.3 TX Wakeup Done .................................................................................481
26.11.3 Reception Interrupts.............................................................................................481
26.11.3.1 RX Break Wakeup Done ......................................................................481
26.11.3.2 RX Header SYNC Done .......................................................................481
26.11.3.3 RX Header Done ..................................................................................481
26.11.3.4 RX Response Done..............................................................................482
26.11.4 Error and Status Interrupts...................................................................................483
26.11.4.1 Transmitter Bit Error .............................................................................484
26.11.4.2 Receive Synchronization Error.............................................................485
26.11.4.3 Receiver Frame Error...........................................................................485
26.11.4.4 Receiver PID Parity Error .....................................................................485
26.11.4.5 Response Checksum Error ..................................................................485
26.11.4.6 Receiver Noise Detection.....................................................................486
26.11.4.7 Timeout Detection ................................................................................486
26.12 Registers ............................................................................................................................................ 486
27. Cryptography Block 487
27.1 Features Overview................................................................................................................487
27.2 System Diagram ...................................................................................................................487
27.3 Block Diagram ......................................................................................................................488
27.4 Function Description .............................................................................................................488
27.4.1 Operating Mode ...................................................................................................488
27.4.2 Memory Map and Register Definitions.................................................................488
27.4.3 Instruction Set ......................................................................................................488
28. Event Generator (EVTGEN) 489
28.1 Features................................................................................................................................489
28.2 Block Diagram ......................................................................................................................489
28.2.1 Enabling and Disabling EVTGEN Block...............................................................490
28.2.2 Counters ..............................................................................................................490
28.2.2.1 Clock and Prescaling............................................................................490
28.2.2.2 Ratio .....................................................................................................491
28.2.2.3 Software Control...................................................................................491
28.2.2.4 Hardware Control .................................................................................491
28.2.3 Counter Status .....................................................................................................491
28.2.4 Comparator Structures.........................................................................................492
28.2.5 Interrupts..............................................................................................................494
28.2.6 DeepSleep interrupt accuracy analysis................................................................495
28.2.7 Use Case .............................................................................................................496
28.2.8 Register List..................................................................................................................... 497
29. Trigger Multiplexer 498
29.1 Features................................................................................................................................498
29.2 Description............................................................................................................................498
29.3 Trigger Multiplexing ..............................................................................................................499
29.4 Trigger Functionality .............................................................................................................501
29.5 Registers...............................................................................................................................503
30. Clock Extension Peripheral Interface (CXPI) 504
30.1 Features................................................................................................................................504
30.2 Block Diagram ......................................................................................................................505
30.3 Clocking ................................................................................................................................505
30.3.1 Baud Rate ............................................................................................................505
30.3.2 Sample Point........................................................................................................507
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Infineon CYT2B63BADQ0AZEGS Technical Reference
- Category
- Motherboards
- Type
- Technical Reference
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