Transcend 64GB 2.5" SATAII User manual

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2.5” Solid State Disk

Transcend Information Inc.

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Description

DescriptionDescription

Description

Due to smaller size (fit the standard dimensions of

2.5” SATA Hard Disk Drives), huge capacity, high

speed, and low power consumption, Solid State Disk

is perfect replacement storage device for PCs,

Laptops, gaming systems, and handheld devices.

Placement

PlacementPlacement

Placement

Features

Features Features

Features

• RoHS compliant

• Fully compatible with devices and OS that support the

SATA 3Gb/s standard

• Non-volatile Flash Memory for outstanding data

retention

• Built-in ECC (Error Correction Code) functionality and

wear-leveling algorithm ensures highly reliable of data

transfer

• Shock resistance

Dimensions

DimensionsDimensions

Dimensions

Side Millimeters Inches

A

100.30 ± 0.40 3.949 ± 0.016

B

69.85 ± 0.20 2.750 ± 0.008

C

9.50 ± 0.15 0.374 ± 0.004

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Specifications

SpecificationsSpecifications

Specifications

Physical Specification

Form Factor

2.5-inch HDD

Storage Capacities

32 GB to 512 GB

Length

100.0 0 ± 0.40

Width

69.85 ± 0.20

Dimensions (mm)

Height

9.50 ± 0.15

Input Voltage

5V ± 5%

Weight

66g ± 5g

Connector

SATA 7+15 pins combo connector

Environmental Specifications

Operating Temperature

0 to 70

Storage Temperature

- 40 to 85

Operating

0% to 95% (Non-condensing)

Humidity

Non-Operating

0% to 95% (Non-condensing)

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Power Requirements

Input Voltage

5V ± 5% @25

Mode Max. (mA) Max. (W)

Write

(peak)

450 1.79

Read

(peak)

400 1.77

Power Consumption

(32GB)

Idle

(peak)

142 0.71

Write

(peak)

640 2.5

Read

(peak)

453 2.1

Power Consumption

(64GB)

Idle

(peak)

144 0.72

Write

(peak)

687 3.44

Read

(peak)

438 2.19

Power Consumption

(128GB)

Idle

(peak)

144 0.72

Write

(peak)

795 3.98

Read

(peak)

462 2.31

Power Consumption

(256GB)

Idle

(peak)

146 0.73

Write

(peak)

884 4.42

Read

(peak)

500 2.5

Power Consumption

(512GB)

Idle

(peak)

266 1.33

Performance

Model P/N Sequential Read

(Max.)

Sequential Write

(Max.)

TS32GSSD25S-M 210 MB/s 70 MB/s

TS64GSSD25S-M 260 MB/s 130 MB/s

TS128GSSD25S-M 240 MB/s 170 MB/s

TS256GSSD25S-M 240 MB/s 200 MB/s

TS512GSSD25S-M 240 MB/s 190 MB/s

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* Note: Reference to the IEC 60068-2-6 Testing procedures; Operating-Sine wave, 5-800Hz/1 oct., 1.5mm, 3g, 0.5 hr./axis,

total 1.5 hrs.

* Note: Reference to the IEC 60068-2-27 Testing procedures; Operating-Half-sine wave, 1500g, 0.5ms, 3 times/dir., total 18

times.

Actual Capacity

Model P/N User Max. LBA Cylinder Head Sector

TS32GSSD25S-M 62,533,296 16,383 16 63

TS64GSSD25S-M 125,045,424 16,383 16 63

TS128GSSD25S-M 250,069,680 16,383 16 63

TS256GSSD25S-M 500,118,192 16,383 16 63

TS512GSSD25S-M 1,000,215,216 16,383 16 63

Reliability

Data Reliability

Supports BCH ECC 16/24 bits in 1024 bytes

Data Retention

10 years

MTBF

1,000,000 hours

Vibration

Operating

3.0G, 5 - 800Hz

Non-Operating

3.0G, 5 - 800Hz

Shock

Operating

1500G, 0.5ms

Non-Operating

1500G, 0.5ms

Regulations

Compliance

CE, FCC and BSMI

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Package Dimensions

Package DimensionsPackage Dimensions

Package Dimensions

Below figure illustrates the Transcend 2.5” SATA Solid State Disk. All dimensions are in mm.

*Note: Tighten mounting screws with no more than 1.0Kg-cm (0.07ft-lbs) of torque.

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Pin Pin

Pin Assignments

AssignmentsAssignments

Assignments

Pin No. Pin Name Pin No. Pin Name

01 GND 02 A+

03 A- 04 GND

05 B- 06 B+

07 GND 08 NC

09 NC 10 NC

11 GND 12 GND

13 GND 14 5V

15 5V 16 5V

17 GND 18 GND

19 GND 20 NC

21 NC 22 NC

Pin Pin

Pin Layout

LayoutLayout

Layout

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Block Diagram

Block DiagramBlock Diagram

Block Diagram

Flash

SATA II 3.0Gb/s

SATA

SSD

Controller

SATA Connector

DRAM

Flash

16bits

8bits

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Reliability

Reliability Reliability

Reliability

Wear-Leveling algorithm

The controller supports static/dynamic wear leveling. When the host writes data, the controller will find and use the block

with the lowest erase count among the free blocks. This is known as dynamic wear leveling. When the free blocks' erase

count is higher than the data blocks', it will activate the static wear leveling, replacing the not so frequently used user

blocks with the high erase count free blocks.

ECC algorithm

The controller uses BCH16/BCH24 ECC algorithm per 1024 bytes. BCH16/BCH24 can correct up to 16 or 24 random

error bits within 1024 data bytes.

Bad-block management

When the flash encounters ECC failed, program fail or erase fail, the controller will mark the block as bad block to prevent

the used of this block and caused data lost later on.

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SATA Interface

SATA InterfaceSATA Interface

SATA Interface

Out of bank signaling

There shall be three Out Of Band (OOB) signals used/detected by the Phy: COMRESET, COMINIT, and COMWAKE.

COMINIT, COMRESET and COMWAKE OOB signaling shall be achieved by transmission of either a burst of four Gen1

ALIGN

P

primitives or a burst composed of four Gen1 Dwords with each Dword composed of four D24.3 characters, each

burst having a duration of 160 UI

OOB

. Each burst is followed by idle periods (at common-mode levels), having durations as

depicted in Figure 4 and Table 2.

Figure 4 : OOB signals

Table 2 : OOB signal times

COMRESET

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COMRESET always originates from the host controller, and forces a hardware reset in the device. It is indicated by

transmitting bursts of data separated by an idle bus condition. The OOB COMRESET signal shall consist of no less than six

data bursts, including inter-burst temporal spacing. The COMRESET signal shall be:

1) Sustained/continued uninterrupted as long as the system hard reset is asserted, or

2) Started during the system hardware reset and ended some time after the negation of system hardware reset, or

3) Transmitted immediately following the negation of the system hardware reset signal.

The host controller shall ignore any signal received from the device from the assertion of the hardware reset signal until the

COMRESET signal is transmitted. Each burst shall be 160 Gen1 UI’s long (106.7 ns) and each inter-burst idle state shall be

480 Gen1 UI’s long (320 ns). A COMRESET detector looksfor four consecutive bursts with 320 ns spacing (nominal). Any

spacing less than 175 ns or greater than 525 ns shall invalidate the COMRESET detector output. The COMRESET

interface signal to the Phy layer shall initiate the Reset sequence shown in Figure 5 below. The interface shall be held

inactive for at least 525 ns after the last burst to ensure far-end detector detects the negation properly.

Figure 5 : comreset sequence

Description:

1. Host/device are powered and operating normally with some form of active communication.

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2. Some condition in the host causes the host to issue COMRESET

3. Host releases COMRESET. Once the condition causing the COMRESET is released, the host releases the COMRESET

signal and puts the bus in a quiescent condition.

4. Device issues COMINIT – When the device detects the release of COMRESET, it responds with a COMINIT. This is also

the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT.

5. Host calibrates and issues a COMWAKE.

6. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional).

Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN

sequence starting at the device's highest supported speed. After ALIGNP Dwords have been sent

for 54.6us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP

primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional speeds

are available the device tries the next lower supported speed by sending ALIGNP Dwords at that rate for

54.6 us (2048 nominal Gen1 Dword times.) This step is repeated for as many slower speeds as are supported. Once the

lowest speed has been reached without response from the host, the device enters an error state.

7. Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate.

Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at

the same speed as received. A host shall be designed such that it acquires lock in 54.6us (2048

nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword

times) after detecting the release of COMWAKE to receive the first ALIGNP. This ensures interoperability with

multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times)

the host restarts the power-on sequence – repeating indefinitely until told to stop by the Application layer.

8. Device locks – the device locks to the ALIGN sequence and, when ready, sends SYNCP indicating it is ready to start

normal operation.

9. Upon receipt of three back-to-back non-ALIGNP primitives, the communication link is established and normal operation

may begin.

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COMINIT

COMINIT always originates from the drive and requests a communication initialization. It is electrically identical to the

COMRESET signal except that it originates from the device and is sent to the host. It is used by the device to request a

reset from the host in accordance to the sequence shown in Figure 6, below.

Figure 6 : cominit sequence

Description:

1. Host/device are powered and operating normally with some form of active communication.

2. Some condition in the device causes the device to issues a COMINIT

3. Host calibrates and issues a COMWAKE.

4. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional).

Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN

sequence starting at the device's highest supported speed. After ALIGN

P

Dwords have been sent for 54.6 us (2048 nominal

Gen1 Dword times) without a response from the host as determined by detection of ALIGN

P

primitives received from the

host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the

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device tries the next lower supported speed by sending ALIGN

P

Dwords at that rate for 54.6 us (2048 nominal Gen1 Dword

times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached

without response from the host, the device enters an error state.

5. Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate.

Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at

the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword

times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting

the release of COMWAKE to receive the first ALIGN

P

. This ensures interoperability with multi-generational and

synchronous designs. If no ALIGN

P

is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the

power-on sequence – repeating indefinitely until told to stop by the Application layer. 6. Device locks – the device locks to

the ALIGN sequence and, when ready, sends SYNC

P

indicating it is ready to start normal operation.

6. Upon receipt of three back-to-back non-ALIGN

P

primitives, the communication link is established and normal operation

may begin.

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Power on sequence timing diagram

The following timing diagrams and descriptions are provided for clarity and are informative.

Figure 7 : power on sequence

Description:

1. Host/device power-off - Host and device power-off.

2. Power is applied - Host side signal conditioning pulls TX and RX pairs to neutral state (common mode voltage).

3. Host issues COMRESET

4. Host releases COMRESET. Once the power-on reset is released, the host releases the COMRESET signal and puts the

bus in a quiescent condition.

5. Device issues COMINIT – When the device detects the release of COMRESET, it responds with a COMINIT. This is also

the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT.

6. Host calibrates and issues a COMWAKE.

7. Device responds – The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional).

Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN

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sequence starting at the device's highest supported speed. After ALIGN

P

primitives have been sent for 54.6 us (2048

nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGN

P

primitives received

from the host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the

device tries the next lower supported speed by sending ALIGN

P

primitives at that rate for 54.6 us (2048 nominal Gen1

Dword times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached

without response from the host, the device shall enter an error state.

8. Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate.

Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at

the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword

times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting

the release of COMWAKE to receive the first ALIGN

P

. This insures interoperability with multi-generational and synchronous

designs. If no ALIGN

P

is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the power-on

sequence – repeating indefinitely until told to stop by the Application layer.

9. Device locks – the device locks to the ALIGN sequence and, when ready, sends the SYNC

P

primitive indicating it is ready

to start normal operation.

10. Upon receipt of three back-to-back non-ALIGN

P

primitives, the communication link is established and normal operation

may begin.

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ATA command register

This table with the following paragraphs summarizes the ATA command set.

Command Table

PARAMETERS USED

Command Name Code

SC SN CY DR HD FT

CHECK POWER MODE E5h X X X O X X

EXECUTE DIAGNOSTICS 90h X X X O X X

FLUSH CACHE E7h X X X O O X

FLUSH CACHE EXT EAh X X X O O X

IDENTIFY DEVICE ECh X X X O X X

IDLE E3h O X X O X X

IDLE IMMEDIATE E1h X X X O X X

INITIALIZE DEVICE PARAMETERS

91h O X X O O X

READ BUFFER E4h X X X O X X

READ DMA C8h or C9h O O O O O X

READ DMA EXT 25h O O O O O X

READ FPDMA QUEUED 60h O O O O O O

READ LOG EXT 2Fh O O O O O O

READ MULTIPLE C4h O O O O O X

READ MULTIPLE EXT 29h O O O O O X

READ SECTOR(S) 20h or 21h O O O O O X

READ SECTOR(S) EXT 24h O O O O O X

READ VERIFY SECTOR(S) 40h or 41h O O O O O X

READ VERIFY SECTOR(S) EXT 42h O O O O O X

RECALIBRATE 10h X X X O X X

SECURITY DISABLE PASSWORD

F6h X X X O X X

SECURITY ERASE PREPARE F3h X X X O X X

SECURITY ERASE UNIT F4h X X X O X X

SECURITY FREEZE LOCK F5h X X X O X X

SECURITY SET PASSWORD F1h X X X O X X

SECURITY UNLOCK F2h X X X O X X

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V0.1

SEEK 7xh X X O O O X

SET FEATURES EFh O X X O X O

SET MULTIPLE MODE C6h O X X O X X

SLEEP E6h X X X O X X

SMART B0h X X O O X O

STANDBY E2h X X X O X X

STANDBY IMMEDIATE E0h X X X O X X

WRITE BUFFER E8h X X X O X X

WRITE DMA CAh or CBh O O O O O X

WRITE DMA EXT 35h O O O O O X

WRITE DMA FUA EXT 3Dh O O O O O X

WRITE FPDMA QUEUED 61h O O O O O O

WRITE MULTIPLE C5h O O O O O X

WRITE MULTIPLE EXT 39h O O O O O X

WRITE MULTIPLE FUA EXT CEh O O O O O X

WRITE SECTOR(S) 30h or 31h O O O O O X

WRITE SECTOR(S) EXT 34h O O O O O X

Note:

O = Valid, X = Don't care

SC = Sector Count Register

SN = Sector Number Register

CY = Cylinder Low/High Register

DR = DEVICE SELECT Bit (DEVICE/HEAD Register Bit 4)

HD = HEAD SELECT Bit (DEVICE/HEAD Register Bit 3-0)

FT = Features Register

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V0.1

ATA

ATAATA

ATA Command Specifications

Command Specifications Command Specifications

Command Specifications

CHECK POWER MODE (E5h)

The host can use this command to determine the current power management mode.

EXECUTE DIAGNOSTICS (90h)

This command performs the internal diagnostic tests implemented by the drive.

FLUSH CACHE (E7h)

This command is used by the host to request the device to flush the write cache. If there is data in the write cache, that data

shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error

occurs.

FLUSH CACHE EXT (EAh)

48-bit feature set mandatory command. This command is used by the host to request the device to flush the write cache. If

there is data in the write cache, that data shall be written to the media. The BSY bit shall remain set to one until all data has

been successfully written or an error occurs.

IDENTIFY DEVICE (ECh)

This commands read out 512Bytes of drive parameter information. Parameter Information consists of the arrangement and

value as shown in the following table. This command enables the host to receive the Identify Drive Information from the

device.

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V0.1

Identify Device Information Default Value

Word Value F/V Description

0 0040h

F

X

V

X

General configuration bit-significant information:

15 0 = ATA device

14-8 Retired

7-6 Obsolete

5-3 Retired

2 Reserved

1 Retired

0 Reserved

1

3C8Ah

3FFFh

F

Number of logical cylinders

15498 (8GB capacity)

16383 (above 16GB capacity)

2 C837h V Specific configuration

3 0010h F Number of logical heads

4-5 0000h X Retired

6 003Fh F Number of logical sector per logical track

7-8 0000h X Reserved for assignment by the CompactFlash_ Association

9 0000h X Retired

10-19 XXXXh F Serial number (20 ASCII characters)

20-21 0000h X Retired

22 0000h X Obsolete

23-26 XXXXh F Firmware revision (8 ASCII characters)

27-46 XXXXh F Model number (40 ASCII characters)

47 8010h

F

15-8 80h

7-0 00h = Reserved

01h = Maximum number of 1 sectors on READ/WRITE MULTIPLE commands

48 0000h F Reserved

49 2F00h

F

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Capabilities

15-14 Reserved for the IDENTIFY PACKET DEVICE command.

13 1 = Standby timer values as specified in this standard are supported

0 = Standby timer values shall be managed by the device

12 Reserved for the IDENTIFY PACKET DEVICE command.

11 1 = IORDY supported

0 = IORDY may be supported

10 1 = IORDY may be disabled

9 1 = LBA supported

8 1 = DMA supported.

7-0 Retired

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V0.1

50 4000h

F

X

F

Capabilities

15 Shall be cleared to zero.

14 Shall be set to one.

13-2 Reserved.

1 Obsolete

0 Shall be set to one to indicate a device specific Standby timer value minimum.

51-52 0000h X Obsolete

53 0007h

F

X

15-3 Reserved

2 1 = the fields reported in word 88 are valid

0 = the fields reported in word 88 are not valid

1 1 = the fields reported in words 70:64 are valid

0 = the fields reported in words 70:64 are not valid

0 1 = the fields reported in words 58:54 are valid

0 = the fields reported in words 58:54 are not valid

54 XXXXh X Number of current cylinders

55 00XXh X Number of current heads

56 XXXXh X Number of current sector per track

57-58 XXXXh X Current capacity in sectors

59 0110h

V

15-9 Reserved

8 1 = Multiple sector setting is valid

7-0 xxh = Setting for number of sectors that shall be transferred per interrupt on R/W Multiple command

60-61 XXXXh F Total number of user addressable sectors

62 0000h X Obsolete

63 0007h

F

V

F

15-11 Reserved

10 1 = Multiword DMA mode 2 is selected

0 = Multiword DMA mode 2 is not selected

9 1 = Multiword DMA mode 1 is selected

0 = Multiword DMA mode 1 is not selected

8 1 = Multiword DMA mode 0 is selected

0 = Multiword DMA mode 0 is not selected

7-3 Reserved

2 1 = Multiword DMA mode 2 and below are supported

1 1 = Multiword DMA mode 1 and below are supported

0 1 = Multiword DMA mode 0 is supported

64 0003h

F

15-8 Reserved

7-0 Advanced PIO modes supported

65 0078h F Minimum Multiword DMA transfer cycle time per word

66 0078h F Manufacturer’s recommended Multiword DMA transfer cycle time

67 0078h F Minimum PIO transfer cycle time without flow control

68 0078h F Minimum PIO transfer cycle time with IORDY flow control

69-70 0000h Reserved

71-74 0000h Reserved for the IDENTIFY PACKET DEVICE command

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