Hardware Intel® RAID Portable Cache Module AXXRPCM3 Technical Product Specification
Revision 1.1
Intel order number E20184-002
7
Table 3. Pin Descriptions
Pin Type Function
CK, CK
1
Input Clock: CK and CK
1
are differential system clock inputs. All address and control inputs are
sampled on the crossing of the positive edge of CK and negative edge of CK
1
. Output
(read) data is referenced to the crossing of CK and CK
1
(both direction of crossing).
ODT[1:0] Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS
1
and DM
signal for x4 and DQ, DQS, DQS
1
RDQS, RDQS
1
and DM for x8 configurations. For x16
configuration ODT is applied to each DQ, UDQS, UDQS LDQS, LDQS, UDM and LDM
signal. The ODT pin will be ignored if the EMRS (1) is programmed to disable ODT.
S
1
[1:0] Input Chip Select: Enables the associated SDRAM command decoder when low and disables
decoder when high. When decoder is disabled, new commands are ignored and previous
operations continue. These input signals also disable all outputs (except CKE and ODT)
of the register(s) on the DIMM when both inputs are high. When both S [0:1] are high, all
register outputs (except CKE, ODT and Chip select) remain in the previous state.
CKE# Input Clock Enable: CKE high activates and CKE low deactivate internal clock signals and
device input buffers and output drivers. Taking CKE low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power- Down (row Active in any
bank). CKE is synchronous for power down entry and exit and or Self-Refresh entry. CKE
is asynchronous for Self-Refresh exit. CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK
1
, ODT and CKE are disabled during
power-down. Input buffers, excluding CKE are disabled during Self-Refresh.
A0 - A13 Input Address Inputs: Provides the row address for Activate commands and the column
address and Auto-Pre-.charge bit A10 (=AP) for Read/Write commands to select one
location out of the memory array in the respective bank. A10 (=AP) is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10=low)
or all banks (A10=high). If only one bank will be precharged, the bank is selected by BA0
and BA1. The address inputs also provide the op-code during Mode Register Set
commands. Row address A13 is used on x4 and x8 components only.
BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define which bank the Activate, Read, Write, or
Precharge command is applied to. BA0 and BA1 also determine if the mode register or
extended mode register will be accessed during a MRS or EMRS cycle.
RAS
1
Input Row Address Strobe: When sampled at the positive rising edge of the clock RAS
1
, this
command defines the operation to be executed by the SDRAM.
CAS
1
Input Column Address Strobe: When sampled at the positive rising edge of the clock, CAS
1
defines the operation to be executed by the SDRAM.
WE
1
Input Write Enable: When sampled at the positive rising edge of the clock, WE
1
defines the
operation to be executed by the SDRAM.
DM[8:0] Input Data Mask: Masks write data when high, and they are issued concurrently with input data.
DQS[8:0] Input/ Output Data Strobe: Positive line of the differential data strobe for input and output data.
DQS
1
[8:0] Input/ Output Data Strobe: Negative line of the differential data strobe for input and output data.
DQ[63:0] Input/Output Data Lines: Data input/output pins.
CB[7:0] - Check Bit: input/output lines, used for ECC.
VDDQ SUPPLY DQ Power Supply: 1.8 V +/- 0.1 V
VDDSPD SUPPLY Serial EEPROM: Positive power supply (wired to a separate power pin at the connector
which supports from 1.7 V to 3.6 V (nominal 1.8 V, 2.5 V and 3.3 V operations.
VDD SUPPLY Power Supply: 1.8 V +/- 0.1 V
VSS SUPPLY Ground:
VREF SUPPLY Reference voltage: For SSTL18 inputs.