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Configurable BISR Chain

Siemens Configurable BISR Chain User guide

  • Hello! I've analyzed the provided document, which is a white paper detailing a configurable BISR chain repair system for faster memory repair data loading. The document explains the system design, its advantages over existing methods, and presents experimental results. I'm ready to answer any questions you have about the described system.
  • What is the main problem this system aims to solve?
    How does this system achieve faster repair data loading?
    What is the purpose of the segment selection circuit (SSC)?
    What does the term 'BISR' stand for?
Configurable BISR
Chain for Fast Repair
Data Loading
Wei Zou Benoit Nadeau-Dostie
Siemens Digital Industries Software
Motivation
• Today’s designs may have tens of thousands of memories
with repair redundancy
•It takes a long time to load the repair data serially during
system power-up
•Can we take advantage of the fact that very few of the
memories actually need repair to significantly speed up the
process?
2
Outline
•The general memory repair system
•Prior work
•Configurable BISR chain repair system
•Experimental results
•Conclusions
3
The general memory repair system
Fuse
Box
Fuse
Box
Controller MEM
BISR
MEM
BISR
MEM
BISR
BIST CONTROLLER
BISR
MEM
BISR
MEM
BISR
MEM
BIST CONTROLLER
repair
enable
repair address
•Dedicated repair register for each memory
•Repair enable indicates that memory needs repair
•Most repair registers contain only contain 0s and allow compression of repair information in
fuse box
4
Prior work (repair sharing)
Fuse
Box Fuse
Box
Controller MEM1
BISR
MEM0 MEM2
BIST CONTROLLER
MEM4
BISR
MEM3 MEM5
BIST CONTROLLER
Nadeau-Dostie
ITC 2020
•Use same repair solution for several memories
•Good results obtained for memories using row repair and memories behind a shared bus
•Limited application for distributed memories using column repair
•Potential yield loss 5
Prior work (memory bypass)
Fuse
Box Fuse
Box
Controller MEM0
BISR
1
0
BAPSS
FF
MEM1
BISR
1
0
BAPSS
FF
MEM2
BISR
1
0
BAPSS
FF
MEM3
BISR
1
0
BAPSS
FF
MEM4
BISR
1
0
BAPSS
FF
MEM5
BISR
1
0
BAPSS
FF
Devanathan
DAC 2013
•Each repair register can be bypassed
•Configuration chain loaded first to select repair registers to include in chain
•Pipeline flop needed to avoid long asynchronous paths
•Speedup limited to about 5X 6
Fuse
Box Fuse
Box
Controller
BIST CONTROLLER0
MEM0
BISR
BIST CONTROLLER1
1D|CF 1D|CF
MEM1
BISR
MEM2
BISR
MEM3
BISR
MEM4
BISR
MEM5
BISR
SSC
SI SO
BP
CTL
SEL
SSC
SI SO
BP
CTL
SEL
Configurable BISR chain repair system
•Extend Devanathan’s idea to bypass several repair registers at a time
•Bypassing longer segments reduces the overhead associated to the configuration chain
7
Segment selection circuit (SSC)
1
0
1
0
1
0Q
SI
BP
UE
SO
SE
CF
SSC
“0”
UR
SR
SEL
Q
D
D
1D
reg0
reg1
•Structure similar to Segment Insertion Bit (SIB) of IEEE 1687
–Selects/bypasses associated chain segment
•SSC has additional circuitry to identify segments that need repair
–1-detection logic
8
9
Fuse
Box Fuse
Box
Controller
BIST CONTROLLER0
MEM0
BISR
BIST CONTROLLER1
1D|CF
MEM1
BISR
MEM2
BISR
MEM3
BISR
MEM4
BISR
MEM5
BISR
SSC
SI SO
BP
SEL
SSC
SI
SO
BP
SEL
D Q
D Q
1D|CF
•Left segment included in scan path because at least one memory needs repair
•Right segment bypassed because none of the memories need repair
–Segment input forced to 0
Active scan path with bypassed segment
Active scan path (configuration chain selected)
10
BIST CONTROLLER0
MEM0
BISR
BIST CONTROLLER1
1D|CF
MEM1
BISR
MEM2
BISR
MEM3
BISR
MEM4
BISR
MEM5
BISR
SSC
SI
SO
BP
SEL
SSC
SI
SO
BP
SEL
D Q D Q
1D|CF
•All segments are bypassed to load chain configuration
Fuse
Box Fuse
Box
Controller
Repair data programming sequence
11
Apply Power-up sequence
Run Memory BIST
Transfer repair data from BIST
controller to BISR register
Run 1-detection to generate
the segment selection data
Rotate the configuration
chain to program the
segment selection data to the
fuse box
Calculate the new BISR
chain length by injecting 1
Program the repair data of
selected BISR segment to
the fuse box
Transfer repair data from
BIST controller to BISR
register
Config the BISR chain
based on the segment
selection data
Power-up sequence
12
Reset BISR chain and SSC
Inject leading 1 and load
the segment selection data
to the configuration chain
Update configuration
chain length and apply
segment selection data to
config the BISR chain
Reset reg0 of SSC
Update the BISR chain
length
Inject leading 1 and load
the repair data to the BISR
chain
Partitioning algorithm considerations
13
•Number of segments depends on a few factors
•Most important one is defect density
–High defect density requires shorter segments to reduce
probability of having to include a segment
•Segments of pre-existing IP blocks must be included as is
–Not always possible to implement optimal segment size
Calculation of optimal segment size
•The BISR Chain Shifting time T = Nrepair X L/Nseg + 2 X Nseg
–L: the total length of the repair registers
–Nseg: number of segments
–Nrepair : number of segments requiring repair
•To minimize T
–( Nrepair X L / Nseg + 2 X Nseg )′ = 0
• 𝑂𝑝𝑡𝑖𝑚𝑎𝑙 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑒𝑔𝑚𝑒𝑛𝑡𝑠: 𝑁𝑠𝑒𝑔 = 𝑁𝑟𝑒𝑝𝑎𝑖𝑟 𝑋 𝐿/2
• 𝑂𝑝𝑡𝑖𝑚𝑎𝑙 𝑆𝑒𝑔𝑚𝑒𝑛𝑡 𝑠𝑖𝑧𝑒 𝑁𝑠𝑖𝑧𝑒 = 𝐿/𝑁𝑠𝑒𝑔
14
15
-
20
40
60
80
100
120
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
M2/M3 M1/M3
vs. Generic
vs. Devanathan
# of memories
Repair data loading speedup factor (single repair)
Speedup factor
16
vs. Generic
vs. Devanathan
# of memories
Speedup factor
Repair data loading speedup factor (two repairs)
-
10
20
30
40
50
60
70
80
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
M2/M3 M1/M3
17
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
12345678910 11 12 13 14 15 16 17 18 19 20
1 faulty memory 2 faulty memories 3 faulty memories 4 faulty memories 5 faulty memories
6 faulty memories 7 faulty memories 8 faulty memories 9 faulty memories 10 faulty memories
Assumed # of
repairs
Actual # of
repairs
Clock cycles
Reference: Generic method requires 100110 clock cycles
Repair data loading cycles
(assumed vs actual number of repairs)
Conclusions
•A configurable BISR chain repair system is proposed to speed
up repair data loading during chip power-up
•Experimental results show that number of clock cycles can be
reduced by one to two orders of magnitude compared to
previous methods
18
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