Texas Instruments CDCLVP2108EVM User guide

Category
Security device components
Type
User guide
User's Guide
SCAU030 May 2009
Low Additive Phase Noise Clock Buffer Evaluation Board
Figure 1. CDCLVP2108 Evaluation Board
Features:
Easy-to-use evaluation board to fan out low phase noise clocks
Easy device setup
Fast configuration
Control pins configurable through jumpers
Board powered at +2.5-/+3.3-V
Single-ended or differential input clocks
CDCLVP2108 supports 16 LVPECL outputs; CDCLVP2108EVM supports four LVPECL outputs
Contents
1 General Description ......................................................................................................... 2
2 Signal Path and Control Circuitry .......................................................................................... 2
3 Getting Started ............................................................................................................... 2
4 Input Clock Selection ........................................................................................................ 2
5 Output Clock .................................................................................................................. 3
6 Schematics and Layout ..................................................................................................... 3
List of Figures
1 CDCLVP2108 Evaluation Board ........................................................................................... 1
2 CDCLVP2108EVM—Schematic ........................................................................................... 4
3 CDCLVP2108EVM—Schematic ........................................................................................... 5
4 CDCLVP2108EVM—Schematic ........................................................................................... 6
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1 General Description
2 Signal Path and Control Circuitry
3 Getting Started
3.1 Power-Supply Connections
4 Input Clock Selection
4.1 Configuring Single-ended Input
General Description
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The CDCLVP2108 is a high-performance, low additive phase noise clock buffer. It has two universal input
buffers that support either single-ended or differential clock inputs. Each input feeds a bank of eight
LVPECL outputs. The device also features on-chip bias generators that can provide the LVPECL
common-mode voltage to the device inputs.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP2108.
This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP2108
device functionalities. Throughout this document, the acronym EVM and the phrases evaluation module
and evaluation board are synonymous with the CDCLVP2108EVM. See Figure 1 for an illustration of the
CDCLVP2108EVM.
For optimum performance, the board is equipped with 50- SMA connectors and well-controlled, 50-
impedance microstrip transmission lines.
The CDCLVP2108 supports single-ended inputs up to 200 MHz and differential inputs up to 2 GHz. The
device provides up to 16 LVPECL outputs operating at the input frequency. For more information about
the CDCLVP2108, see the CDCLVP2108 product data sheet available for download from the TI web site
(www.ti.com ).
The CDCLVP2108EVM has self-explanatory labeling and uses similar naming conventions as the
CDCLVP2108 product data sheet. In this user's guide, all words in boldface and italic print reflect the
actual labeling on the EVM. The CDCLVP2108EVM can be used with either single-ended or differential
inputs.
Connect the power-supply source to the banana plug labeled VDD (P4), and connect the ground of the
power-supply source to GND (P5). There are decoupling capacitors and ferrite bead to isolate the EVM
power from the CDCLVP2108 device power pins.
The CDCLVP2108EVM can use a supply voltage of 2.375 V to 3.6 V.
The CDCLVP2108EVM offers users the option of receiving either a differential or single-ended clock as
the clock input. The default option is for the differential signal at both device inputs. The inputs can be
applied through the SMAs (J103, J104 or J105, J106). These inputs are ac-coupled to the device inputs.
The common-mode voltage for these inputs after the ac-coupling capacitors are provided by 50 (R152,
R153 and R154, R155) to the device on-chip bias generator (V
AC_REF
) pins. Either of the two input clocks
can be selected using jumper JP1. When JP1 is shorted, IN0 is selected. When JP1 is open, IN1 is
selected.
For a single-ended clock applied to IN0, remove capacitors C68 and C69 and replace them with 0-
resistors of the same footprint. The single-ended signal should be applied to INP0 (J103) and the dc bias
voltage should be applied to INN0 (J104).
For a single-ended clock applied to IN1, remove capacitors C72 and C73 and replace them with 0-
resistors of the same footprint. The single-ended signal should be applied to INP1 (J105) and the dc bias
voltage should be applied to INN1 (J106).
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5 Output Clock
6 Schematics and Layout
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Output Clock
The CDCLVP2108 generates up to 16 LVPECL outputs. Four outputs are available on the
CDCLVP2108EVM (outputs 0, 7, 8, and 15) through the following SMAs:
J13, J23 for OUT0
J17, J27 for OUT7
J33, J32 for OUT8
J39, J38 for OUT15
The LVPECL outputs are terminated with 150 to ground and ac-coupled to the respective SMAs.
Figure 2 through Figure 4 show the printed circuit board (PCB) schematics.
Note: Board layouts are not to scale. These figures are intended to show how the board is laid out;
they are not intended to be used for manufacturing CDCLVP2108EVM PCBs.
SCAU030 May 2009 Low Additive Phase Noise Clock Buffer Evaluation Board 3
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VCC2
VCC3
VCC5
VCC6
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC1
VCC4
VDD
VDD
VDD
VDD
OUTP0
OUTN0
OUTN1
OUTP1
OUTN2
OUTP2
OUTN3
OUTP3
OUTN10
OUTN9
OUTP10
OUTN8
OUTP9
OUTN11
OUTP8
OUTP11
OUTN6
OUTN5
OUTP6
OUTN4
OUTP5
OUTN7
OUTP4
OUTP7
INP0
INN0
INP1
INN1
OUTN15
OUTN14
OUTP14
OUTN13
OUTP13
OUTN12
OUTP12
OUTP15
INP0
INN0
INP1
INN1
C
DCELVP2108
C
USTOMER EVAL
B
oard
1216: VAC_REF
21
08: VAC_REF0
IN_SEL
2
INP1
3
INN1
4
NC1
5
VCC1
6
VCC2
7
V
AC_REF
8
INN0
9
INP0
10
NC2
11
VCC3
13
OUTP0
14
OUTN0
15
OUTP1
16
OUTN1
17
OUTP2
18
OUTN2
19
OUTP3
20
OUTN3
21
VCC4
24
OUTP4
22
OUTN4
23
OUTP5
25
OUTN5
26
OUTP6
27
OUTN6
28
OUTP7
29
OUTN7
30
VCC5
37
OUTP8
31
TH_P
AD
49
OUTN8
32
OUTP9
33
OUTN9
34
OUTP10
35
OUTN10
36
OUTP11
38
OUTN11
39
VCC6
48
GND
1
GND2
12
OUTP12
40
OUTN12
41
OUTP13
42
OUTN13
43
OUTP14
44
OUTN14
45
OUTP15
46
OUTN15
47
U2
CDCLVP1216
U2
CDCLVP1216
C142
0.1uF
C142
0.1uF
C161
0.1uF
C161
0.1uF
C73
0.1uF
C73
0.1uF
C152
0.1uF
C152
0.1uF
C144
0.1uF
C144
0.1uF
12
R154
50
R154
50
C41
10uF/6.3V
C41
10uF/6.3V
12
R153
50
R153
50
C42
10uF/6.3V
C42
10uF/6.3V
2
3
1
4
5
J105
SMA-EDGE
J105
SMA-EDGE
C68
0.1uF
C68
0.1uF
12
R152
50
R152
50
P4
VDD3.3V
P4
VDD3.3V
D26
LEDGREEN
D26
LEDGREEN
D12
MBRS2040LT3
D12
MBRS2040LT3
12
R156
0
R156
0
2
3
1
4
5
J103
SMA-EDGE
J103
SMA-EDGE
12
R120
301
R120
301
C135
10uF
C135
10uF
C72
0.1uF
C72
0.1uF
C160
0.1uF
C160
0.1uF
1 2
R130
10k
R130
10k
1 2
L5
BLM15HD102SN1D
L5
BLM15HD102SN1D
P5
GND
P5
GND
C69
0.1uF
C69
0.1uF
2
3
1
4
5
J106
SMA-EDGE
J106
SMA-EDGE
C38
10uF/6.3V
C38
10uF/6.3V
1
2
JP1JP1
C136
10uF
C136
10uF
1 2
L6
BLM15HD102SN1D
L6
BLM15HD102SN1D
2
3
1
4
5
J104
SMA-EDGE
J104
SMA-EDGE
C159
0.1uF
C159
0.1uF
12
R155
50
R155
50
Schematics and Layout
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space
Figure 2. CDCLVP2108EVM—Schematic
4 Low Additive Phase Noise Clock Buffer Evaluation Board SCAU030 May 2009
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OUTP1
OUTN1
OUTP0
OUTN0
OUTP2
OUTN2
OUTP7
OUTN7
OUTP5
OUTN5
OUTP4
OUTN4
OUTP6
OUTN6
OUTP3
OUTN3
1 2
R81 150R81 150
1 2
R88 150R88 150
C47
0.1uF
C47
0.1uF
1
JP25JP25
1 2
R101 150R101 150
2
3
1
4
5
J13
SMA-EDGE
J13
SMA-EDGE
C46
0.1uF
C46
0.1uF
1 2
R87 150R87 150
1
JP20JP20
1 2
R86 150R86 150
1 2
R102150R102150
1
JP21JP21
1
JP22JP22
1
JP23JP23
1 2
R80 150R80 150
1
JP24JP24
2
3
1
4
5
J17
SMA-EDGE
J17
SMA-EDGE
1
2
R64
150
R64
150
1
JP8JP8
1
JP9JP9
1
2
R63
150
R63
150
1 2
R83 150R83 150
1
JP26JP26
C62
0.1uF
C62
0.1uF
1 2
R82 150R82 150
1
JP10JP10
1 2
R85 150R85 150
1 2
R84 150R84 150
1
JP11JP11
2
3
1
4
5
J27
SMA-EDGE
J27
SMA-EDGE
2
3
1
4
5
J23
SMA-EDGE
J23
SMA-EDGE
1
JP12JP12
1
2
R61
150
R61
150
1
2
R59
150
R59
150
1 2
R89 150R89 150
C61
0.1uF
C61
0.1uF
www.ti.com
Schematics and Layout
space
Figure 3. CDCLVP2108EVM—Schematic
SCAU030 May 2009 Low Additive Phase Noise Clock Buffer Evaluation Board 5
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OUTP9
OUTN9
OUTP8
OUTN8OUTP10
OUTN10
OUTP15
OUTN15
OUTP13
OUTN13
OUTP12
OUTN12
OUTP14
OUTN14
OUTP11
OUTN11
C93
0.1uF
C93
0.1uF
1
JP14JP14
2
3
1
4
5
J38
SMA-EDGE
J38
SMA-EDGE
1
2
R109
150
R109
150
1
JP7JP7
1
2
R108
150
R108
150
1
JP6JP6
1 2
R94 150R94 150
1
JP5JP5
1 2
R91 150R91 150
1 2
R103 150R103 150
1
JP4JP4
1 2
R90 150R90 150
C107
0.1uF
C107
0.1uF
2
3
1
4
5
J33
SMA-EDGE
J33
SMA-EDGE
1
JP13JP13
1 2
R95 150R95 150
C106
0.1uF
C106
0.1uF
1 2
R98 150R98 150
1 2
R97 150R97 150
1
JP3JP3
1 2
R100150R100150
1 2
R99 150R99 150
2
3
1
4
5
J32
SMA-EDGE
J32
SMA-EDGE
1
JP19JP19
2
3
1
4
5
J39
SMA-EDGE
J39
SMA-EDGE
1
2
R96
150
R96
150
1
2
R71
150
R71
150
1
JP18JP18
1
JP17JP17
1
JP16JP16
1 2
R93 150R93 150
C94
0.1uF
C94
0.1uF
1
JP15JP15
1 2
R92 150R92 150
1 2
R104150R104150
Schematics and Layout
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space
Figure 4. CDCLVP2108EVM—Schematic
6 Low Additive Phase Noise Clock Buffer Evaluation Board SCAU030 May 2009
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
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The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
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TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or
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Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
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FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of –0.5 V to 4.0 V and the output voltage range of 0 V to 3.6 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +120 ° C. The EVM is designed to operate
properly with certain components above +85 ° C as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
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Texas Instruments CDCLVP2108EVM User guide

Category
Security device components
Type
User guide

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