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Rev. 0.5 2/13 Copyright © 2013 by Silicon Laboratories SiM3L1xx
SiM3L1xx
SiM3L1XX REFERENCE MANUAL
This reference manual accompanies several documents to provide the complete description of SiM3L1xx devices,
part of the Silicon Laboratories 32-bit ARM Cortex-M3 family of microcontrollers.
This document provides a detailed description for all peripherals available on all SiM3L1xx devices. The peripheral
mix varies across different members of the device family. Refer to the device data sheet for details on the specific
peripherals available for each member of the device family. In the event that the device data sheet and this
document contain conflicting information, the device data sheet should be considered the authoritative source.
Voltage Supply
Monitor (VMON0)
Watchdog
Timer
(WDTIMER0)
ARM Cortex M3
Core
Debug /
Programming
Hardware
DMA
10-Channel Controller
Peripheral Crossbar
Power On Reset /
PMU
AHB
APB
Power
Memory
DMA support available for these peripherals
Clock Control
Clocking
Low Frequency Oscillator (LFOSC0)
Low Power Oscillator (LPOSC0)
Real-Time Clock Oscillator (RTC0OSC)
External Oscillator Control (EXTOSC0)
Phase-Locked Loop (PLL0OSC)
Peripheral Clock Control (CLKCTRL)
DC-DC Buck Converter (DCDC0)
Data Transfer Manager
DTM0 DTM1 DTM2
LDO0
Low Power Mode Charge Pump
Power Management Unit (PMU)
32/64/128/256 kB Flash
8/16/32 kB configurable
retention RAM
Digital
LDO
Memory
LDO
Analog
LDO
I/O
Standard 5 V
Tolerant I/O pins
Crossbar
Analog
Comparator 0 Comparator 1
IDAC0
SARADC0
Digital
USART0 UART0
I2C0
SPI1SPI0
EPCA0
Timer 0
Low Power Timer (LPTIMER0)
AES0
ENCDEC0
Advanced Capture Counter
(ACCTR0)
Timer 2Timer 1
4x40 Segment LCD Controller
ECRC0
SiM3L1xx
2 Rev. 0.5
Table of Contents
1. Related Documents and Conventions.............................................................................11
1.1. Related Documents......................................................................................................11
1.2. Conventions .................................................................................................................11
2. Memory Organization........................................................................................................12
2.1. Flash Region................................................................................................................13
2.2. RAM Region.................................................................................................................14
2.3. Peripheral Region.........................................................................................................15
2.4. Cortex-M3 Internal Peripherals ....................................................................................15
3. SiM3L1xx Register Memory Map......................................................................................16
4. Interrupts............................................................................................................................30
4.1. System Exceptions.......................................................................................................30
4.2. Interrupt Vector Table...................................................................................................31
4.3. Priorities .......................................................................................................................35
5. Clock Control (CLKCTRL0)...............................................................................................38
5.1. Clock Control Features.................................................................................................38
5.2. CLKCTRL0 Registers...................................................................................................39
5.3. CLKCTRL0 Register Memory Map...............................................................................48
6. System Configuration (SCONFIG0)..................................................................................50
6.1. System Configuration Features....................................................................................50
6.2. SCONFIG0 Registers...................................................................................................51
6.3. SCONFIG0 Register Memory Map...............................................................................52
7. Reset Sources (RSTSRC0)................................................................................................53
7.1. Reset Sources Features...............................................................................................53
7.2. Overview ......................................................................................................................54
7.3. Power-On Reset...........................................................................................................54
7.4. VBAT Monitor Power-Fail Reset ..................................................................................55
7.5. External Pin Reset........................................................................................................56
7.6. Missing Clock Detector Reset......................................................................................56
7.7. Comparator Reset........................................................................................................56
7.8. Watchdog Timer Reset.................................................................................................56
7.9. RTC Reset....................................................................................................................56
7.10.Software Reset ............................................................................................................56
7.11.Core Reset...................................................................................................................57
7.12.PMU Wake Reset Flag ................................................................................................57
7.13.RSTSRC0 Registers....................................................................................................58
7.14.RSTSRC0 Register Memory Map................................................................................62
8. Port I/O Configuration .......................................................................................................63
8.1. Port Bank Description...................................................................................................63
8.2. Crossbar.......................................................................................................................64
8.3. Port Bank Standard (PBSTD) and Port Bank General Purpose (PBGP) Features......68
8.4. Standard Modes of Operation......................................................................................69
8.5. Assigning Standard Port Bank Pins to Analog and Digital Functions...........................69
8.6. Port Match....................................................................................................................70
8.7. Pulse Generator...........................................................................................................70
SiM3L1xx
Rev. 0.5 3
8.8. Port Bank Security........................................................................................................71
8.9. Debugging Interfaces...................................................................................................72
8.10.External Interrupts........................................................................................................73
8.11.PBCFG0 Registers ......................................................................................................75
8.12.PBCFG0 Register Memory Map..................................................................................83
8.13.PBSTD0, PBSTD1, PBSTD2 and PBSTD3 Registers.................................................84
8.14.PBSTDn Register Memory Map...................................................................................94
8.15.PBGP4 Registers.........................................................................................................97
8.16.PBGP4 Register Memory Map...................................................................................104
9. Power................................................................................................................................106
9.1. Power Modes .............................................................................................................106
10.Power Management Unit (PMU0)....................................................................................110
10.1.Waking from Power Mode 8.......................................................................................111
10.2.Retention RAM Control..............................................................................................113
10.3.PMU0 Registers.........................................................................................................115
10.4.PMU0 Register Memory Map.....................................................................................128
11.Internal Voltage Regulator (LDO0).................................................................................130
11.1.Internal Voltage Regulator Features..........................................................................130
11.2.Functional Description ...............................................................................................131
11.3.LDO0 Registers .........................................................................................................132
11.4.LDO0 Register Memory Map.....................................................................................134
12.DC-DC Regulator (DCDC0)..............................................................................................135
12.1.DCDC Features .........................................................................................................135
12.2.Inductor Selection and Startup Behavior ...................................................................136
12.3.Synchronous/Asynchronous Modes ..........................................................................137
12.4.Power Switch Size.....................................................................................................138
12.5.Configuration Guidelines............................................................................................138
12.6.Optimizing Board Layout............................................................................................138
12.7.Clocking Options.....................................................................................................138
12.8.Bypass Mode.............................................................................................................139
12.9.Interrupts....................................................................................................................139
12.10.DCDC0 Registers ....................................................................................................140
12.11.DCDC0 Register Memory Map................................................................................145
13.Device Identification (DEVICEID0) and Universally Unique Identifier.........................146
13.1.Device ID Features....................................................................................................146
13.2.Device Identification Encoding...................................................................................146
13.3.Universally Unique Identifier (UUID)..........................................................................146
13.4.DEVICEID0 Registers................................................................................................147
13.5.DEVICEID0 Register Memory Map............................................................................151
14.Advanced Capture Counter (ACCTR0) ..........................................................................153
14.1.ACCTR Features .......................................................................................................153
14.2.External Pin Connections...........................................................................................155
14.3.Overview....................................................................................................................156
14.4.Analog Front End.......................................................................................................157
14.5.Analog Comparator Functions...................................................................................160
14.6.LC Counting/Conditioning..........................................................................................
161
SiM3L1xx
4 Rev. 0.5
14.7.Counting Modes.........................................................................................................164
14.8.Sample Rate..............................................................................................................166
14.9.Debounce...................................................................................................................166
14.10.Reset Behavior ........................................................................................................168
14.11.Wake up and Interrupt Sources...............................................................................168
14.12.Register Write Access..............................................................................................168
14.13.Debug Signals..........................................................................................................168
14.14.LC Resonant Setup Example...................................................................................169
14.15.ACCTR0 Registers ..................................................................................................171
14.16.ACCTR0 Register Memory Map..............................................................................197
15.Advanced Encryption Standard (AES0).........................................................................201
15.1.AES Features.............................................................................................................201
15.2.Overview....................................................................................................................202
15.3.Interrupts....................................................................................................................202
15.4.Debug Mode ..............................................................................................................202
15.5.DMA Configuration and Usage..................................................................................203
15.6.Using the AES Module for Electronic Codebook (ECB).............................................205
15.7.Using the AES Module for Cipher Block Chaining (CBC)..........................................208
15.8.Using the AES Module for Counter (CTR).................................................................215
15.9.Performing “In-Place” Ciphers ...................................................................................218
15.10.Using the AES Module in Software Mode................................................................219
15.11.AES0 Registers........................................................................................................220
15.12.AES0 Register Memory Map ...................................................................................240
16.Comparator (CMP0 and CMP1).......................................................................................244
16.1.Comparator Features.................................................................................................244
16.2.Input Multiplexer.........................................................................................................245
16.3.Output Signal Routing................................................................................................248
16.4.Overview....................................................................................................................248
16.5.Input Mode Selection.................................................................................................248
16.6.Output Configuration..................................................................................................251
16.7.Response Time..........................................................................................................252
16.8.Hysteresis..................................................................................................................252
16.9.Interrupts and Flags...................................................................................................252
16.10.CMP0 and CMP1 Registers.....................................................................................253
16.11.CMPn Register Memory Map...................................................................................258
17.DMA Controller (DMACTRL0) .........................................................................................259
17.1.DMA Controller Features...........................................................................................259
17.2.Overview....................................................................................................................260
17.3.Interrupts....................................................................................................................260
17.4.Configuring a DMA Channel......................................................................................260
17.5.DMA Channel Transfer Structures.............................................................................261
17.6.Transfer Types...........................................................................................................266
17.7.Masking Channels .....................................................................................................272
17.8.Errors.........................................................................................................................272
17.9.Arbitration...................................................................................................................273
17.10.Data Requests.........................................................................................................274
SiM3L1xx
Rev. 0.5 5
17.11.DMACTRL0 Registers .............................................................................................275
17.12.DMACTRL0 Register Memory Map.........................................................................305
18.DMA Crossbar (DMAXBAR0)..........................................................................................310
18.1.DMA Crossbar Features............................................................................................310
18.2.Channel Priority .........................................................................................................311
18.3.DMAXBAR0 Registers...............................................................................................312
18.4.DMAXBAR0 Register Memory Map...........................................................................318
19.Data Transfer Manager (DTM0, DTM1 and DTM2).........................................................319
19.1.DTM Features............................................................................................................319
19.2.Overview....................................................................................................................320
19.3.Counters ....................................................................................................................320
19.4.State Machine Control ...............................................................................................321
19.5.Configuring DTM States in Memory...........................................................................324
19.6.DTM0, DTM1 and DTM2 Registers ...........................................................................325
19.7.DTMn Register Memory Map.....................................................................................332
20.Enhanced Cyclic Redundancy Check (ECRC0) ............................................................334
20.1.ECRC Features..........................................................................................................334
20.2.Overview....................................................................................................................335
20.3.Polynomial Specification............................................................................................335
20.4.Automatic Seeding.....................................................................................................335
20.5.Peripheral Data Snooping..........................................................................................336
20.6.DMA Configuration and Usage..................................................................................337
20.7.Byte-Level Bit Reversal and Byte Reordering............................................................338
20.8.ECRC0 Registers.......................................................................................................341
20.9.ECRC0 Register Memory Map ..................................................................................349
21.Encoder/Decoder (ENCDEC0).........................................................................................351
21.1.ENCDEC Features.....................................................................................................351
21.2.Manchester Encoding................................................................................................352
21.3.Manchester Decoding................................................................................................353
21.4.Three-out-of-Six Encoding.........................................................................................354
21.5.Three-out-of-Six Decoding.........................................................................................
355
21.6.Interrupts and Error Conditions..................................................................................356
21.7.DMA Configuration and Usage..................................................................................357
21.8.ENCDEC0 Registers..................................................................................................359
21.9.ENCDEC0 Register Memory Map .............................................................................365
22.Enhanced Programmable Counter Array (EPCA0).......................................................367
22.1.Enhanced Programmable Counter Array Features....................................................367
22.2.Output Mapping .........................................................................................................369
22.3.Triggers......................................................................................................................369
22.4.Module Overview.......................................................................................................370
22.5.Interrupts....................................................................................................................370
22.6.Clocking.....................................................................................................................371
22.7.Output Modes ............................................................................................................372
22.8.Operational Modes.....................................................................................................374
22.9.DMA Configuration and Usage..................................................................................385
22.10.EPCA0 Registers.....................................................................................................387
SiM3L1xx
6 Rev. 0.5
22.11.EPCA0 Register Memory Map.................................................................................400
22.12.EPCA0_CH0-5 Registers.........................................................................................402
22.13.EPCAn_CHx Register Memory Map........................................................................408
23.External Oscillator (EXTOSC0).......................................................................................410
23.1.External Oscillator Features.......................................................................................410
23.2.External Pin Connections...........................................................................................411
23.3.External Crystal Oscillator..........................................................................................411
23.4.External CMOS Oscillator..........................................................................................412
23.5.External RC Oscillator................................................................................................413
23.6.External C Oscillator..................................................................................................415
23.7.EXTOSC0 Registers..................................................................................................417
23.8.EXTOSC0 Register Memory Map..............................................................................419
24.Flash Controller (FLASHCTRL0) ....................................................................................420
24.1.Flash Controller Features ..........................................................................................420
24.2.Overview....................................................................................................................421
24.3.Flash Read Control....................................................................................................421
24.4.Flash Write and Erase Control...................................................................................422
24.5.FLASHCTRL0 Registers............................................................................................425
24.6.FLASHCTRL0 Register Memory Map........................................................................431
25.Inter-Integrated Circuit Bus (I2C0) .................................................................................433
25.1.I2C Features..............................................................................................................433
25.2.Signal Routing............................................................................................................433
25.3.I2C Protocol...............................................................................................................434
25.4.Clocking.....................................................................................................................438
25.5.Operational Modes.....................................................................................................438
25.6.Error Handling............................................................................................................451
25.7.Additional Features....................................................................................................452
25.8.Debug Mode ..............................................................................................................453
25.9.DMA Configuration and Usage..................................................................................454
25.10.I2C0 Registers.........................................................................................................459
25.11.I2C0 Register Memory Map.....................................................................................475
26.Current Mode Digital-to-Analog Converter (IDAC0) .....................................................477
26.1.IDAC Features...........................................................................................................477
26.2.Output........................................................................................................................478
26.3.Conversion Triggers...................................................................................................478
26.4.IDAC Setup................................................................................................................479
26.5.Using the IDAC in On-Demand Mode........................................................................481
26.6.Using the IDAC in Periodic FIFO-Only Mode.............................................................481
26.7.Using the IDAC in Periodic FIFO Wrap Mode............................................................481
26.8.Using the IDAC in Periodic DMA Mode .....................................................................482
26.9.Adjusting the IDAC Output Current............................................................................482
26.10.Debug Mode ............................................................................................................482
26.11.IDAC0 Registers......................................................................................................483
26.12.IDAC0 Register Memory Map..................................................................................491
27.LCD Controller (LCD0).....................................................................................................
493
27.1.LCD Features.............................................................................................................493
SiM3L1xx
Rev. 0.5 7
27.2.Pin Assignment..........................................................................................................494
27.3.Configuring the Segment Driver.................................................................................496
27.4.Powering Down..........................................................................................................496
27.5.Mapping Data Registers to LCD Pins........................................................................497
27.6.Contrast Adjustment ..................................................................................................498
27.7.Adjusting the VBAT Monitor Threshold......................................................................500
27.8.Setting the Refresh Rate............................................................................................500
27.9.Blinking Segments.....................................................................................................500
27.10.LCD0 Registers........................................................................................................501
27.11.LCD0 Register Memory Map ...................................................................................517
28.Register Security (LOCK0)..............................................................................................520
28.1.Security Features.......................................................................................................520
28.2.LOCK0 Registers.......................................................................................................521
28.3.LOCK0 Register Memory Map...................................................................................527
29.Low Power Oscillator (LPOSC0).....................................................................................528
29.1.Low Power Oscillator Features..................................................................................528
29.2.Operation...................................................................................................................528
30.Low Power Timer (LPTIMER0)........................................................................................529
30.1.Low Power Timer Features........................................................................................529
30.2.Trigger Sources .........................................................................................................530
30.3.Output........................................................................................................................531
30.4.Clocking.....................................................................................................................531
30.5.Configuring the Timer ................................................................................................532
30.6.Interrupts....................................................................................................................533
30.7.Output Modes ............................................................................................................533
30.8.Automatic Reset.........................................................................................................533
30.9.Debug Mode ..............................................................................................................533
30.10.LPTIMER0 Registers...............................................................................................534
30.11.LPTIMER0 Register Memory Map...........................................................................540
31.Phase-Locked Loop (PLL0).............................................................................................541
31.1.PLL Features .............................................................................................................541
31.2.Overview....................................................................................................................542
31.3.Interrupts....................................................................................................................542
31.4.Output Modes ............................................................................................................542
31.5.Additional Features....................................................................................................547
31.6.Advanced Setup Examples........................................................................................549
31.7.PLL0 Registers ..........................................................................................................550
31.8.PLL0 Register Memory Map......................................................................................558
32.Process/Voltage/Temperature Oscillator (PVTOSC0) ..................................................559
32.1.PVTOSC Features.....................................................................................................559
32.2.PVTOSC Operation ...................................................................................................559
32.3.PVTOSC0 Registers..................................................................................................560
32.4.PVTOSC0 Register Memory Map..............................................................................561
33.Real Time Clock and Low Frequency Oscillator (RTC0)..............................................562
33.1.RTC Features ............................................................................................................562
33.2.RTC Clock Output......................................................................................................563
SiM3L1xx
8 Rev. 0.5
33.3.Overview....................................................................................................................563
33.4.Clocking.....................................................................................................................563
33.5.Accessing the Timer ..................................................................................................569
33.6.Alarms........................................................................................................................569
33.7.Interrupts....................................................................................................................570
33.8.Usage Modes.............................................................................................................570
33.9.RTC0 Registers .........................................................................................................571
33.10.RTC0 Register Memory Map...................................................................................580
34.SAR Analog-to-Digital Converter (SARADC0)...............................................................582
34.1.SARADC Features.....................................................................................................582
34.2.Input Multiplexer.........................................................................................................584
34.3.Tracking and Conversion Time..................................................................................586
34.4.Burst Mode.................................................................................................................588
34.5.Channel Sequencer...................................................................................................589
34.6.Voltage Reference Configuration...............................................................................590
34.7.Power Configuration ..................................................................................................591
34.8.Data Output................................................................................................................592
34.9.Output Data Window Comparator..............................................................................594
34.10.Interrupts..................................................................................................................596
34.11.DMA Configuration and Usage................................................................................597
34.12.SARADC0 Registers................................................................................................598
34.13.SARADC0 Register Memory Map............................................................................617
35.Serial Peripheral Interface (SPI0 and SPI1)...................................................................620
35.1.SPI Features..............................................................................................................620
35.2.External Signal Routing .............................................................................................621
35.3.Signal Descriptions....................................................................................................621
35.4.Clear to Send (CTS–SPI1 Only)................................................................................622
35.5.Clocking.....................................................................................................................623
35.6.Signal Format.............................................................................................................623
35.7.Master Mode Configurations and Data Transfer........................................................626
35.8.Slave Mode Configurations and Data Transfer..........................................................629
35.9.Special Operation Modes and Functions...................................................................631
35.10.Interrupts..................................................................................................................633
35.11.Debug Mode ............................................................................................................633
35.12.Module Reset...........................................................................................................633
35.13.DMA Configuration and Usage................................................................................634
35.14.SPI0 and SPI1 Registers.........................................................................................635
35.15.SPIn Register Memory Map.....................................................................................646
36.Timers (TIMER0, TIMER1 and TIMER2)..........................................................................648
36.1.Timer Features...........................................................................................................648
36.2.External Signal Routing .............................................................................................648
36.3.Clocking.....................................................................................................................649
36.4.Configuring Timer Interrupts
......................................................................................650
36.5.Start and Stop Synchronization .................................................................................651
36.6.EX Input Synchronization (TIMER0 and TIMER1).....................................................651
36.7.Mode Selection..........................................................................................................652
SiM3L1xx
Rev. 0.5 9
36.8.Auto-Reload Mode.....................................................................................................653
36.9.Up/Down Mode (TIMER0 and TIMER1) ....................................................................654
36.10.Edge Capture Mode (Rising or Falling)....................................................................655
36.11.Pulse Capture Mode (High or Low)..........................................................................656
36.12.Duty Cycle Capture Mode........................................................................................657
36.13.One Shot Mode........................................................................................................658
36.14.Square Wave Output Mode (TIMER0 and TIMER1)................................................659
36.15.Pulse Width Modulation (PWM) Mode (TIMER0 and TIMER1)...............................660
36.16.TIMER0, TIMER1 and TIMER2 Registers...............................................................662
36.17.TIMERn Register Memory Map ...............................................................................669
37.Universal Synchronous/Asynchronous Receiver/Transmitter (USART0)..................670
37.1.USART Features........................................................................................................670
37.2.External Signal Routing .............................................................................................672
37.3.Basic Data Format.....................................................................................................672
37.4.Baud Rate..................................................................................................................672
37.5.Interrupts....................................................................................................................673
37.6.Flow Control...............................................................................................................674
37.7.Debug Mode ..............................................................................................................674
37.8.Transmitting Data.......................................................................................................675
37.9.Receiving Data...........................................................................................................677
37.10.Synchronous Communication..................................................................................678
37.11.Additional Communication Support..........................................................................680
37.12.DMA Configuration and Usage................................................................................685
37.13.USART0 Registers...................................................................................................686
37.14.USART0 Register Memory Map ..............................................................................705
38.Universal Asynchronous Receiver/Transmitter (UART0) ............................................707
38.1.UART Features..........................................................................................................707
38.2.Pin Assignment..........................................................................................................709
38.3.UART Clocking ..........................................................................................................709
38.4.Basic Data Format.....................................................................................................710
38.5.Baud Rate..................................................................................................................710
38.6.Inter
rupts....................................................................................................................711
38.7.Inter-Packet Delay Generator....................................................................................712
38.8.Debug Mode ..............................................................................................................712
38.9.Transmitting Data.......................................................................................................713
38.10.Receiving Data.........................................................................................................715
38.11.Additional Communication Support..........................................................................716
38.12.UART0 Registers.....................................................................................................719
38.13.UART0 Register Memory Map.................................................................................737
39.Voltage Supply Monitor (VMON0)...................................................................................739
39.1.Voltage Supply Monitor Features...............................................................................739
39.2.VBAT Supply Monitoring............................................................................................740
39.3.VMON0 Registers......................................................................................................742
39.4.VMON0 Register Memory Map..................................................................................744
40.Voltage Reference and Temperature Sensor (VREF0).................................................745
40.1.Voltage Reference Features......................................................................................745
SiM3L1xx
10 Rev. 0.5
40.2.Functional Description ...............................................................................................746
40.3.VREF0 and Temperature Sensor Registers..............................................................747
40.4.VREF0 Register Memory Map...................................................................................748
41.Watchdog Timer (WDTIMER0) ........................................................................................749
41.1.Watchdog Timer Features .........................................................................................749
41.2.Overview....................................................................................................................750
41.3.Lock and Key Interface..............................................................................................750
41.4.Setting the Early Warning and Reset Thresholds......................................................751
41.5.Interrupts and Flags...................................................................................................751
41.6.Debug Mode ..............................................................................................................752
41.7.WDTIMER0 Registers................................................................................................753
41.8.WDTIMER0 Register Memory Map ...........................................................................758
Document Change List.........................................................................................................759
Contact Information..............................................................................................................760
SiM3L1xx
Rev. 0.5 11
Related Documents and Conventions
1. Related Documents and Conventions
1.1. Related Documents
1.1.1. SiM3L1xx Data Sheet
The Silicon Labs SiM3L1xx data sheet provides specific information for this device family, including electrical
characteristics, mechanical characteristics, and ordering information.
1.1.2. Hardware Access Layer (HAL) API Description
The Silicon Labs Hardware Access Layer (HAL) API provides functions to modify and read each bit in the
SiM3L1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual.
1.1.3. ARM Cortex-M3 Reference Manual
The ARM-specific features like the Nested Vector Interrupt Controller are described in the ARM Cortex-M3
reference documentation. The online reference manual can be found online at the following link:
http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3.
1.2. Conventions
The block diagrams in this document use the following formatting conventions:
Figure 1.1. Block Diagram Conventions
Internal Module
External Memory
Block
Output_Pin
External to MCU
Block
Input_Pin
Internal_Output_SignalInternal_Input_Signal
REGn_NAME / BIT_NAME
DMA Block Memory Block
Other Internal
Peripheral Block
Functional Block
SiM3L1xx
12 Rev. 0.5
Memory Organization
2. Memory Organization
The memory organization of the SiM3L1xx devices follows the standard ARM Cortex-M3 structure, shown in
Figure 2.1. There is one 32-bit memory space shared amongst the flash, RAM, SiM3L1xx peripherals, external
memory, and M3 peripherals. The unused memory addresses are reserved and should not be accessed.
Figure 2.1. SiM3L1xx Memory Map
Flash
0x00000000
0x0003_FFFF
0x0004_0000
0x1FFF_FFFF
Reserved
0x2000_8000
0x21FF_FFFF
0x2200_0000
RAM
Region
Flash
Region
Reserved
0x2000_7FFF
Configurable Retention RAM
0x2000_0000
RAM Bit-Band Alias
0x23FF_FFFF
0x2400_0000
0x3FFF_FFFF
Peripheral Bit-Band Alias
0x4200_0000
0x43FF_FFFF
0x4400_0000
0xDFFF_FFFF
0xE000_0000
0x4000_0000
SiM3L1xx Peripherals
Reserved
0x4004_4FFF
0x4004_5000
0x41FF_FFFF
Reserved
Reserved
0xE010_FFFF
Cortex-M3 Internal Peripherals
0xE011_0000
0xFFFF_FFFF
Reserved
Peripheral
Region
SiM3L1xx
Rev. 0.5 13
Memory Organization
2.1. Flash Region
The SiM3L1xx devices implement 256, 128, 64, or 32 kB of flash which is accessible starting at 0x00000000. The
flash can be read using standard ARM instructions. The FLASHCTRL0 module should be used to write and erase
flash from firmware.
The flash block can be locked from external access by writing to the lock word located at 0x0003FFFC. A value of
0xFFFFFFFF or 0x00000000 at this location will unlock the flash. Any other value written to this location will lock
the entire flash from external (debugger) writes or reads until:
An erase operation is initiated from firmware.
An erase operation is initiated through the debug port (SWD/JTAG).
Firmware writes 0x00000000 to the lock word.
The DMA can access all of flash.
Figure 2.2. SiM3L16x Flash Memory Map (256 kB)
Figure 2.3. SiM3L15x Flash Memory Map (128 kB)
Flash
0x00000000
0x0003FFFF
0x00040000
0x1FFFFFF
Reserved
Lock Word 0x0003FFFC
Flash
0x00000000
0x0003FFFF
0x00040000
0x1FFFFFF
Reserved
Lock Word 0x0003FFFC
Reserved
0x0001FFFF
SiM3L1xx
14 Rev. 0.5
Memory Organization
Figure 2.4. SiM3L14x Flash Memory Map (64 kB)
Figure 2.5. SiM3L13x Flash Memory Map (32 kB)
2.2. RAM Region
The RAM region consists of 32 kB (SiM3L16x and SiM3L15x), 16 kB (SiM3L14x), or 8 kB (SiM3L13x) and starts at
location 0x20000000. This RAM is configurable via firmware in 4 kB segments to act as standard RAM or retention
RAM in the PMU0 module. When a 4 kB block is configured as retention RAM, memory contents will be retained
during Power Mode 8 and 9 as long as the Supply Monitor has not caused a reset.
The RAM Bit-Band Alias region can be used to perform sets or clears of individual bits in the RAM. Each bit in the
RAM region is represented by the least-significant bit at the word-aligned bit-band alias address.
Flash
0x00000000
0x0003FFFF
0x00040000
0x1FFFFFF
Reserved
Lock Word 0x0003FFFC
Reserved
0x0000FFFF
Flash
0x00000000
0x0003FFFF
0x00040000
0x1FFFFFF
Reserved
Lock Word 0x0003FFFC
Reserved
0x00007FFF
SiM3L1xx
Rev. 0.5 15
Memory Organization
2.3. Peripheral Region
The SiM3L1xx peripheral registers are located starting at address 0x4000_0000. Registers for a specific module
are typically located together in the peripheral region of memory to facilitate structure access from firmware. Each
register may have up to four access methods, implemented as four separate locations in memory. The four
possible access methods are named ALL, SET, CLR, and MSK.
The register’s ALL access address is the primary access point for any register. Individual bits may be Read/Write
(RW), Read-Only (RO), or Write-Only (WO). The ALL access address is implemented for all registers, and where
absolute memory addresses are given in the documentation, they refer to the ALL address. For registers with write
access, the ALL address will directly write all bits of the register. A read of the ALL address will read the current
value in the register.
The SET and CLR addresses provide bit-wise, atomic write access to set and clear bits in the register without
colliding with hardware. Writing a 1 to a bit in the SET address will set the corresponding bit, and writing a 1 to a bit
in the CLR address will clear the corresponding bit. A write of 0 to either SET or CLR will have no effect on the
corresponding bit. For registers implementing SET and CLR access methods, the SET address is at offset 0x4,
and the CLR address is at offset 0x8 from the register’s ALL access address. SET and CLR access are not
implemented on every register.
The MSK address allows a write to a specific range of bits in the register. The upper 16 bits act as a mask for
writing a value in the lower 16 bits of the register. For example, a write of 0x0F000400 to the MASK address would
write a value of 4 to bits [11:8] of the register, while none of the rest of the bits are modified. For registers
implementing the MSK access method, the MSK address is at offset 0xC from the registers ALL access address.
MSK access is implemented for only a small set of registers which may require atomic, simultaneous writes of both
1’s and 0’s (such as port output registers).
Many control and status registers support the SET and CLR access methods. The Peripheral Bit-Band Alias region
can also be used to perform sets or clears of individual bits in the peripheral registers, which results in a read-
modify-write operation on the bus. Each bit in the registers region is represented by the least-significant bit at the
word-aligned bit-band alias address. When supported, it is recommended to use the SET and CLR registers
instead of the Bit-Band Alias region to change individual bits in a register. Bit-band accesses are not protected
against hardware conflicts.
Each peripheral is discussed in detail in the corresponding chapter. The register map for the SiM3L1xx devices can
be found in “3. SiM3L1xx Register Memory Map” . Detailed descriptions of each register and the bit fields within
can be found in the specific peripheral section for that register.
2.4. Cortex-M3 Internal Peripherals
The Cortex-M3 Internal Peripherals space includes standard M3 functions such as the NVIC and ETM. For more
information on these functions of the ARM core, consult the ARM Cortex-M3 Reference Manual.
SiM3L1xx
16 Rev. 0.5
SiM3L1xx Register Memory Map
3. SiM3L1xx Register Memory Map
This section details the register memory map for the SiM3L1xx devices. Registers are listed in address order,
beginning with 0x4000_0000.
Table 3.1. Register Memory Map
Register Name Title
Address
(ALL Access)
SET (+0x4)
CLR(+0x8)
MSK (+0xC)
USART0 Registers
USART0_CONFIG Module Configuration 0x4000_0000 Y Y
USART0_MODE Module Mode Select 0x4000_0010 Y Y
USART0_FLOWCN Flow Control 0x4000_0020 Y Y
USART0_CONTROL Module Control 0x4000_0030 Y Y
USART0_IPDELAY Inter-Packet Delay 0x4000_0040
USART0_BAUDRATE Transmit and Receive Baud Rate 0x4000_0050
USART0_FIFOCN FIFO Control 0x4000_0060 Y Y
USART0_DATA FIFO Input/Output Data 0x4000_0070
UART0 Registers
UART0_CONFIG Module Configuration 0x4000_1000 Y Y
UART0_MODE Module Mode Select 0x4000_1010 Y Y
UART0_FLOWCN Flow Control 0x4000_1020 Y Y
UART0_CONTROL Module Control 0x4000_1030 Y Y
UART0_IPDELAY Inter-Packet Delay 0x4000_1040
UART0_BAUDRATE Transmit and Receive Baud Rate 0x4000_1050
UART0_FIFOCN FIFO Control 0x4000_1060 Y Y
UART0_DATA FIFO Input/Output Data 0x4000_1070
UART0_CLKDIV Clock Divider 0x4000_1080
SiM3L1xx
Rev. 0.5 17
SiM3L1xx Register Memory Map
SPI0 Registers
SPI0_DATA Input/Output Data 0x4000_4000
SPI0_CONTROL Module Control 0x4000_4010 Y Y
SPI0_CONFIG Module Configuration 0x4000_4020 Y Y
SPI0_CLKRATE Module Clock Rate Control 0x4000_4030
SPI0_FSTATUS FIFO Status 0x4000_4040
SPI0_CONFIGMD Mode Configuration 0x4000_4050 Y Y
SPI1 Registers
SPI1_DATA Input/Output Data 0x4000_5000
SPI1_CONTROL Module Control 0x4000_5010 Y Y
SPI1_CONFIG Module Configuration 0x4000_5020 Y Y
SPI1_CLKRATE Module Clock Rate Control 0x4000_5030
SPI1_FSTATUS FIFO Status 0x4000_5040
SPI1_CONFIGMD Mode Configuration 0x4000_5050 Y Y
I2C0 Registers
I2C0_CONTROL Module Control 0x4000_9000 Y Y
I2C0_CONFIG Module Configuration 0x4000_9010 Y Y
I2C0_SADDRESS Slave Address 0x4000_9020
I2C0_SMASK Slave Address Mask 0x4000_9030
I2C0_DATA Data Buffer Access 0x4000_9040
I2C0_TIMER Timer Data 0x4000_9050
I2C0_TIMERRL Timer Reload Values 0x4000_9060
I2C0_SCONFIG SCL Signal Configuration 0x4000_9070
I2C0_I2CDMA DMA Configuration 0x4000_9080
Table 3.1. Register Memory Map
Register Name Title
Address
(ALL Access)
SET (+0x4)
CLR(+0x8)
MSK (+0xC)
SiM3L1xx
18 Rev. 0.5
SiM3L1xx Register Memory Map
EPCA0 Registers
EPCA0_CH0_MODE Channel Capture/Compare Mode 0x4000_E000
EPCA0_CH0_CONTROL Channel Capture/Compare Control 0x4000_E010 Y Y
EPCA0_CH0_CCAPV Channel Compare Value 0x4000_E020
EPCA0_CH0_CCAPVUPD Channel Compare Update Value 0x4000_E030
EPCA0_CH1_MODE Channel Capture/Compare Mode 0x4000_E040
EPCA0_CH1_CONTROL Channel Capture/Compare Control 0x4000_E050 Y Y
EPCA0_CH1_CCAPV Channel Compare Value 0x4000_E060
EPCA0_CH1_CCAPVUPD Channel Compare Update Value 0x4000_E070
EPCA0_CH2_MODE Channel Capture/Compare Mode 0x4000_E080
EPCA0_CH2_CONTROL Channel Capture/Compare Control 0x4000_E090 Y Y
EPCA0_CH2_CCAPV Channel Compare Value 0x4000_E0A0
EPCA0_CH2_CCAPVUPD Channel Compare Update Value 0x4000_E0B0
EPCA0_CH3_MODE Channel Capture/Compare Mode 0x4000_E0C0
EPCA0_CH3_CONTROL Channel Capture/Compare Control 0x4000_E0D0 Y Y
EPCA0_CH3_CCAPV Channel Compare Value 0x4000_E0E0
EPCA0_CH3_CCAPVUPD Channel Compare Update Value 0x4000_E0F0
EPCA0_CH4_MODE Channel Capture/Compare Mode 0x4000_E100
EPCA0_CH4_CONTROL Channel Capture/Compare Control 0x4000_E110 Y Y
EPCA0_CH4_CCAPV Channel Compare Value 0x4000_E120
EPCA0_CH4_CCAPVUPD Channel Compare Update Value 0x4000_E130
EPCA0_CH5_MODE Channel Capture/Compare Mode 0x4000_E140
EPCA0_CH5_CONTROL Channel Capture/Compare Control 0x4000_E150 Y Y
EPCA0_CH5_CCAPV Channel Compare Value 0x4000_E160
EPCA0_CH5_CCAPVUPD Channel Compare Update Value 0x4000_E170
EPCA0_MODE Module Operating Mode 0x4000_E180
EPCA0_CONTROL Module Control 0x4000_E190 Y Y
Table 3.1. Register Memory Map
Register Name Title
Address
(ALL Access)
SET (+0x4)
CLR(+0x8)
MSK (+0xC)
SiM3L1xx
Rev. 0.5 19
SiM3L1xx Register Memory Map
EPCA0_STATUS Module Status 0x4000_E1A0 Y Y
EPCA0_COUNTER Module Counter/Timer 0x4000_E1B0
EPCA0_LIMIT Module Upper Limit 0x4000_E1C0
EPCA0_LIMITUPD Module Upper Limit Update Value 0x4000_E1D0
EPCA0_DTIME Phase Delay Time 0x4000_E1E0
EPCA0_DTARGET DMA Transfer Target 0x4000_E200
TIMER0 Registers
TIMER0_CONFIG High and Low Timer Configuration 0x4001_4000 Y Y
TIMER0_CLKDIV Module Clock Divider Control 0x4001_4010
TIMER0_COUNT Timer Value 0x4001_4020
TIMER0_CAPTURE Timer Capture/Reload Value 0x4001_4030
TIMER1 Registers
TIMER1_CONFIG High and Low Timer Configuration 0x4001_5000 Y Y
TIMER1_CLKDIV Module Clock Divider Control 0x4001_5010
TIMER1_COUNT Timer Value 0x4001_5020
TIMER1_CAPTURE Timer Capture/Reload Value 0x4001_5030
TIMER2 Registers
TIMER2_CONFIG High and Low Timer Configuration 0x4001_6000 Y Y
TIMER2_CLKDIV Module Clock Divider Control 0x4001_6010
TIMER2_COUNT Timer Value 0x4001_6020
TIMER2_CAPTURE Timer Capture/Reload Value 0x4001_6030
SARADC0 Registers
SARADC0_CONFIG Module Configuration 0x4001_A000 Y Y
SARADC0_CONTROL Measurement Control 0x4001_A010 Y Y
SARADC0_SQ7654 Channel Sequencer Time Slots 4-7 Setup 0x4001_A020
SARADC0_SQ3210 Channel Sequencer Time Slots 0-3 Setup 0x4001_A030
SARADC0_CHAR32 Conversion Characteristic 2 and 3 Setup 0x4001_A040 Y Y
Table 3.1. Register Memory Map
Register Name Title
Address
(ALL Access)
SET (+0x4)
CLR(+0x8)
MSK (+0xC)
SiM3L1xx
20 Rev. 0.5
SiM3L1xx Register Memory Map
SARADC0_CHAR10 Conversion Characteristic 0 and 1 Setup 0x4001_A050 Y Y
SARADC0_DATA Output Data Word 0x4001_A060
SARADC0_WCLIMITS Window Comparator Limits 0x4001_A070
SARADC0_ACC Accumulator Initial Value 0x4001_A080
SARADC0_STATUS Module Status 0x4001_A090 Y Y
SARADC0_FIFOSTATUS FIFO Status 0x4001_A0A0
CMP0 Registers
CMP0_CONTROL Module Control 0x4001_F000 Y Y
CMP0_MODE Input and Module Mode 0x4001_F010 Y Y
CMP1 Registers
CMP1_CONTROL Module Control 0x4002_0000 Y Y
CMP1_MODE Input and Module Mode 0x4002_0010 Y Y
AES0 Registers
AES0_CONTROL Module Control 0x4002_7000 Y Y
AES0_XFRSIZE Number of Blocks 0x4002_7010
AES0_DATAFIFO Input/Output Data FIFO Access 0x4002_7020
AES0_XORFIFO XOR Data FIFO Access 0x4002_7030
AES0_HWKEY0 Hardware Key Word 0 0x4002_7040
AES0_HWKEY1 Hardware Key Word 1 0x4002_7050
AES0_HWKEY2 Hardware Key Word 2 0x4002_7060
AES0_HWKEY3 Hardware Key Word 3 0x4002_7070
AES0_HWKEY4 Hardware Key Word 4 0x4002_7080
AES0_HWKEY5 Hardware Key Word 5 0x4002_7090
AES0_HWKEY6 Hardware Key Word 6 0x4002_70A0
AES0_HWKEY7 Hardware Key Word 7 0x4002_70B0
AES0_HWCTR0 Hardware Counter Word 0 0x4002_70C0
AES0_HWCTR1 Hardware Counter Word 1 0x4002_70D0
Table 3.1. Register Memory Map
Register Name Title
Address
(ALL Access)
SET (+0x4)
CLR(+0x8)
MSK (+0xC)
/