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K20_100

NXP K20_100 Reference guide

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K20 Sub-Family Reference Manual
Supports: MK20DX128ZVLQ10, MK20DX128ZVMD10,
MK20DX256ZVLQ10, MK20DX256ZVMD10, MK20DN512ZVLQ10,
MK20DN512ZVMD10
Document Number: K20P144M100SF2RM
Rev. 6, Nov 2011
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Contents
Section Number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................53
1.1.1 Purpose.........................................................................................................................................................53
1.1.2 Audience......................................................................................................................................................53
1.2 Conventions..................................................................................................................................................................53
1.2.1 Numbering systems......................................................................................................................................53
1.2.2 Typographic notation...................................................................................................................................54
1.2.3 Special terms................................................................................................................................................54
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................55
2.2 K20 Family Introduction...............................................................................................................................................55
2.3 Module Functional Categories......................................................................................................................................55
2.3.1 ARM Cortex-M4 Core Modules..................................................................................................................57
2.3.2 System Modules...........................................................................................................................................57
2.3.3 Memories and Memory Interfaces...............................................................................................................58
2.3.4 Clocks...........................................................................................................................................................59
2.3.5 Security and Integrity modules....................................................................................................................59
2.3.6 Analog modules...........................................................................................................................................60
2.3.7 Timer modules.............................................................................................................................................60
2.3.8 Communication interfaces...........................................................................................................................62
2.3.9 Human-machine interfaces..........................................................................................................................62
2.4 Orderable part numbers.................................................................................................................................................63
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................65
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3.2 Core modules................................................................................................................................................................65
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................65
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................68
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................74
3.2.4 JTAG Controller Configuration...................................................................................................................75
3.3 System modules............................................................................................................................................................76
3.3.1 SIM Configuration.......................................................................................................................................76
3.3.2 Mode Controller Configuration...................................................................................................................77
3.3.3 PMC Configuration......................................................................................................................................77
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................78
3.3.5 MCM Configuration....................................................................................................................................80
3.3.6 Crossbar Switch Configuration....................................................................................................................80
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................83
3.3.8 Peripheral Bridge Configuration..................................................................................................................85
3.3.9 DMA request multiplexer configuration......................................................................................................87
3.3.10 DMA Controller Configuration...................................................................................................................90
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................91
3.3.12 Watchdog Configuration..............................................................................................................................92
3.4 Clock Modules..............................................................................................................................................................93
3.4.1 MCG Configuration.....................................................................................................................................93
3.4.2 OSC Configuration......................................................................................................................................94
3.4.3 RTC OSC configuration...............................................................................................................................95
3.5 Memories and Memory Interfaces................................................................................................................................95
3.5.1 Flash Memory Configuration.......................................................................................................................95
3.5.2 Flash Memory Controller Configuration.....................................................................................................99
3.5.3 SRAM Configuration...................................................................................................................................101
3.5.4 SRAM Controller Configuration.................................................................................................................104
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3.5.5 System Register File Configuration.............................................................................................................104
3.5.6 VBAT Register File Configuration..............................................................................................................105
3.5.7 EzPort Configuration...................................................................................................................................106
3.5.8 FlexBus Configuration.................................................................................................................................107
3.6 Security.........................................................................................................................................................................110
3.6.1 CRC Configuration......................................................................................................................................110
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3.7 Analog...........................................................................................................................................................................111
3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................111
3.7.2 CMP Configuration......................................................................................................................................118
3.7.3 12-bit DAC Configuration...........................................................................................................................120
3.7.4 VREF Configuration....................................................................................................................................121
3.8 Timers...........................................................................................................................................................................122
3.8.1 PDB Configuration......................................................................................................................................122
3.8.2 FlexTimer Configuration.............................................................................................................................125
3.8.3 PIT Configuration........................................................................................................................................129
3.8.4 Low-power timer configuration...................................................................................................................130
3.8.5 CMT Configuration......................................................................................................................................132
3.8.6 RTC configuration.......................................................................................................................................133
3.9 Communication interfaces............................................................................................................................................134
3.9.1 Universal Serial Bus (USB) Subsystem.......................................................................................................134
3.9.2 CAN Configuration......................................................................................................................................139
3.9.3 SPI configuration.........................................................................................................................................141
3.9.4 I2C Configuration........................................................................................................................................144
3.9.5 UART Configuration...................................................................................................................................145
3.9.6 SDHC Configuration....................................................................................................................................148
3.9.7 I2S configuration..........................................................................................................................................149
3.10 Human-machine interfaces (HMI)................................................................................................................................151
3.10.1 GPIO configuration......................................................................................................................................151
3.10.2 TSI Configuration........................................................................................................................................152
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................155
4.2 System memory map.....................................................................................................................................................155
4.2.1 Aliased bit-band regions..............................................................................................................................156
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4.3 Flash Memory Map.......................................................................................................................................................157
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................158
4.4 SRAM memory map.....................................................................................................................................................159
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................159
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................159
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................163
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................168
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................169
5.2 Programming model......................................................................................................................................................169
5.3 High-Level device clocking diagram............................................................................................................................169
5.4 Clock definitions...........................................................................................................................................................170
5.4.1 Device clock summary.................................................................................................................................171
5.5 Internal clocking requirements.....................................................................................................................................173
5.5.1 Clock divider values after reset....................................................................................................................174
5.5.2 VLPR mode clocking...................................................................................................................................174
5.6 Clock Gating.................................................................................................................................................................174
5.7 Module clocks...............................................................................................................................................................175
5.7.1 PMC 1-kHz LPO clock................................................................................................................................176
5.7.2 WDOG clocking..........................................................................................................................................177
5.7.3 Debug trace clock.........................................................................................................................................177
5.7.4 PORT digital filter clocking.........................................................................................................................177
5.7.5 LPTMR clocking..........................................................................................................................................178
5.7.6 USB FS OTG Controller clocking...............................................................................................................178
5.7.7 FlexCAN clocking.......................................................................................................................................179
5.7.8 UART clocking............................................................................................................................................179
5.7.9 SDHC clocking............................................................................................................................................180
5.7.10 I2S clocking.................................................................................................................................................180
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5.7.11 TSI clocking.................................................................................................................................................180
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................183
6.2 Reset..............................................................................................................................................................................183
6.2.1 Power-on reset (POR)..................................................................................................................................184
6.2.2 System resets................................................................................................................................................184
6.2.3 Debug resets.................................................................................................................................................187
6.3 Boot...............................................................................................................................................................................189
6.3.1 Boot sources.................................................................................................................................................189
6.3.2 Boot options.................................................................................................................................................189
6.3.3 FOPT boot options.......................................................................................................................................189
6.3.4 Boot sequence..............................................................................................................................................190
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................193
7.2 Power modes.................................................................................................................................................................193
7.3 Entering and exiting power modes...............................................................................................................................195
7.4 Power mode transitions.................................................................................................................................................196
7.5 Power modes shutdown sequencing.............................................................................................................................197
7.6 Module Operation in Low Power Modes......................................................................................................................197
7.7 Clock Gating.................................................................................................................................................................200
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................201
8.2 Flash Security...............................................................................................................................................................201
8.3 Security Interactions with other Modules.....................................................................................................................202
8.3.1 Security interactions with FlexBus..............................................................................................................202
8.3.2 Security Interactions with EzPort................................................................................................................202
8.3.3 Security Interactions with Debug.................................................................................................................202
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Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................205
9.1.1 References....................................................................................................................................................207
9.2 The Debug Port.............................................................................................................................................................207
9.2.1 JTAG-to-SWD change sequence.................................................................................................................208
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................208
9.3 Debug Port Pin Descriptions.........................................................................................................................................209
9.4 System TAP connection................................................................................................................................................209
9.4.1 IR Codes.......................................................................................................................................................209
9.5 JTAG status and control registers.................................................................................................................................210
9.5.1 MDM-AP Control Register..........................................................................................................................211
9.5.2 MDM-AP Status Register............................................................................................................................213
9.6 Debug Resets................................................................................................................................................................214
9.7 AHB-AP........................................................................................................................................................................215
9.8 ITM...............................................................................................................................................................................216
9.9 Core Trace Connectivity...............................................................................................................................................216
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................216
9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................217
9.11.1 Performance Profiling with the ETB...........................................................................................................217
9.11.2 ETB Counter Control...................................................................................................................................218
9.12 TPIU..............................................................................................................................................................................218
9.13 DWT.............................................................................................................................................................................218
9.14 Debug in Low Power Modes........................................................................................................................................219
9.14.1 Debug Module State in Low Power Modes.................................................................................................220
9.15 Debug & Security.........................................................................................................................................................220
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................221
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10.2 Signal Multiplexing Integration....................................................................................................................................221
10.2.1 Port control and interrupt module features..................................................................................................222
10.2.2 Clock gating.................................................................................................................................................222
10.2.3 Signal multiplexing constraints....................................................................................................................222
10.3 Pinout............................................................................................................................................................................222
10.3.1 K20 Signal Multiplexing and Pin Assignments...........................................................................................223
10.3.2 K20 Pinouts..................................................................................................................................................229
10.4 Module Signal Description Tables................................................................................................................................231
10.4.1 Core Modules...............................................................................................................................................231
10.4.2 System Modules...........................................................................................................................................232
10.4.3 Clock Modules.............................................................................................................................................233
10.4.4 Memories and Memory Interfaces...............................................................................................................233
10.4.5 Analog..........................................................................................................................................................234
10.4.6 Communication Interfaces...........................................................................................................................236
10.4.7 Human-Machine Interfaces (HMI)..............................................................................................................240
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................243
11.1.1 Overview......................................................................................................................................................243
11.1.2 Features........................................................................................................................................................243
11.1.3 Modes of operation......................................................................................................................................244
11.2 External signal description............................................................................................................................................245
11.3 Detailed signal descriptions..........................................................................................................................................245
11.4 Memory map and register definition.............................................................................................................................245
11.4.1 Pin Control Register n (PORTx_PCRn).......................................................................................................252
11.4.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................254
11.4.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................255
11.4.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................255
11.4.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................256
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11.4.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................257
11.4.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................257
11.5 Functional description...................................................................................................................................................258
11.5.1 Pin control....................................................................................................................................................258
11.5.2 Global pin control........................................................................................................................................258
11.5.3 External interrupts........................................................................................................................................259
11.5.4 Digital filter..................................................................................................................................................260
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................261
12.1.1 Features........................................................................................................................................................261
12.1.2 Modes of operation......................................................................................................................................261
12.1.3 SIM Signal Descriptions..............................................................................................................................262
12.2 Memory map and register definition.............................................................................................................................262
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................264
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................266
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................268
12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................271
12.2.5 System Options Register 6 (SIM_SOPT6)..................................................................................................272
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................273
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................275
12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................276
12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................277
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................278
12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................279
12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................282
12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................284
12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................286
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................287
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12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................290
12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................291
12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................293
12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................294
12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................295
12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................295
12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................296
12.3 Functional description...................................................................................................................................................296
Chapter 13
Mode Controller
13.1 Introduction...................................................................................................................................................................297
13.1.1 Features........................................................................................................................................................297
13.1.2 Modes of Operation.....................................................................................................................................297
13.1.3 MCU Reset...................................................................................................................................................308
13.2 Mode Control Memory Map/Register Definition.........................................................................................................311
13.2.1 System Reset Status Register High (MC_SRSH)........................................................................................312
13.2.2 System Reset Status Register Low (MC_SRSL).........................................................................................313
13.2.3 Power Mode Protection Register (MC_PMPROT).....................................................................................314
13.2.4 Power Mode Control Register (MC_PMCTRL)..........................................................................................316
Chapter 14
Power Management Controller
14.1 Introduction...................................................................................................................................................................319
14.2 Features.........................................................................................................................................................................319
14.3 Low-Voltage Detect (LVD) System.............................................................................................................................319
14.3.1 LVD Reset Operation...................................................................................................................................320
14.3.2 LVD Interrupt Operation.............................................................................................................................320
14.3.3 Low-Voltage Warning (LVW) Interrupt Operation.....................................................................................320
14.4 PMC Memory Map/Register Definition.......................................................................................................................321
14.4.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)........................................................321
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14.4.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)........................................................322
14.4.3 Regulator Status and Control Register (PMC_REGSC)..............................................................................324
Chapter 15
Low-leakage wake-up unit (LLWU)
15.1 Introduction...................................................................................................................................................................327
15.1.1 Features........................................................................................................................................................328
15.1.2 Modes of operation......................................................................................................................................328
15.1.3 Block diagram..............................................................................................................................................329
15.2 LLWU Signal Descriptions...........................................................................................................................................330
15.3 Memory map/register definition...................................................................................................................................331
15.3.1 LLWU Pin Enable 1 Register (LLWU_PE1)..............................................................................................331
15.3.2 LLWU Pin Enable 2 Register (LLWU_PE2)..............................................................................................332
15.3.3 LLWU Pin Enable 3 Register (LLWU_PE3)..............................................................................................334
15.3.4 LLWU Pin Enable 4 Register (LLWU_PE4)..............................................................................................335
15.3.5 LLWU Module Enable Register (LLWU_ME)...........................................................................................336
15.3.6 LLWU Flag 1 Register (LLWU_F1)...........................................................................................................337
15.3.7 LLWU Flag 2 Register (LLWU_F2)...........................................................................................................339
15.3.8 LLWU Flag 3 Register (LLWU_F3)...........................................................................................................341
15.3.9 LLWU Control and Status Register (LLWU_CS).......................................................................................342
15.4 Functional description...................................................................................................................................................343
15.4.1 LLS mode.....................................................................................................................................................344
15.4.2 VLLS modes................................................................................................................................................344
15.4.3 Initialization.................................................................................................................................................345
15.4.4 Low power mode recovery..........................................................................................................................345
Chapter 16
Miscellaneous Control Module (MCM)
16.1 Introduction...................................................................................................................................................................347
16.1.1 Features........................................................................................................................................................347
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16.2 Memory Map/Register Descriptions.............................................................................................................................347
16.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)..................................................................348
16.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)..............................................................348
16.2.3 SRAM arbitration and protection (MCM_SRAMAP).................................................................................349
16.2.4 Interrupt status register (MCM_ISR)...........................................................................................................350
16.2.5 ETB counter control register (MCM_ETBCC)...........................................................................................351
16.2.6 ETB reload register (MCM_ETBRL)..........................................................................................................352
16.2.7 ETB counter value register (MCM_ETBCNT)...........................................................................................353
16.3 Functional Description..................................................................................................................................................353
16.3.1 Interrupts......................................................................................................................................................353
Chapter 17
Crossbar Switch (AXBS)
17.1 Introduction...................................................................................................................................................................355
17.1.1 Features........................................................................................................................................................355
17.2 Memory Map / Register Definition...............................................................................................................................356
17.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................357
17.2.2 Control Register (AXBS_CRSn).................................................................................................................360
17.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................362
17.3 Functional Description..................................................................................................................................................363
17.3.1 General operation.........................................................................................................................................363
17.3.2 Register coherency.......................................................................................................................................364
17.3.3 Arbitration....................................................................................................................................................364
17.4 Initialization/application information...........................................................................................................................367
Chapter 18
Memory Protection Unit (MPU)
18.1 Introduction...................................................................................................................................................................369
18.2 Overview.......................................................................................................................................................................369
18.2.1 Block Diagram.............................................................................................................................................369
18.2.2 Features........................................................................................................................................................370
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18.3 Memory Map/Register Definition.................................................................................................................................371
18.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................374
18.3.2 Error Address Register, Slave Port n (MPU_EARn)...................................................................................376
18.3.3 Error Detail Register, Slave Port n (MPU_EDRn)......................................................................................377
18.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................378
18.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................379
18.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................379
18.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................382
18.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................383
18.4 Functional Description..................................................................................................................................................385
18.4.1 Access Evaluation Macro.............................................................................................................................385
18.4.2 Putting It All Together and Error Terminations...........................................................................................386
18.4.3 Power Management......................................................................................................................................387
18.5 Initialization Information..............................................................................................................................................387
18.6 Application Information................................................................................................................................................387
Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Introduction...................................................................................................................................................................391
19.1.1 Features........................................................................................................................................................391
19.1.2 General operation.........................................................................................................................................391
19.2 Memory map/register definition...................................................................................................................................392
19.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................393
19.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................397
19.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................402
19.3 Functional Description..................................................................................................................................................407
19.3.1 Access support.............................................................................................................................................407
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Chapter 20
Direct memory access multiplexer (DMAMUX)
20.1 Introduction...................................................................................................................................................................409
20.1.1 Overview......................................................................................................................................................409
20.1.2 Features........................................................................................................................................................410
20.1.3 Modes of operation......................................................................................................................................410
20.2 External signal description............................................................................................................................................411
20.3 Memory map/register definition...................................................................................................................................411
20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)...........................................................................412
20.4 Functional description...................................................................................................................................................413
20.4.1 DMA channels with periodic triggering capability......................................................................................413
20.4.2 DMA channels with no triggering capability...............................................................................................416
20.4.3 "Always enabled" DMA sources.................................................................................................................416
20.5 Initialization/application information...........................................................................................................................417
20.5.1 Reset.............................................................................................................................................................417
20.5.2 Enabling and configuring sources................................................................................................................417
Chapter 21
Direct Memory Access Controller (eDMA)
21.1 Introduction...................................................................................................................................................................421
21.1.1 Block diagram..............................................................................................................................................421
21.1.2 Block parts...................................................................................................................................................422
21.1.3 Features........................................................................................................................................................424
21.2 Modes of operation.......................................................................................................................................................425
21.3 Memory map/register definition...................................................................................................................................425
21.3.1 Control Register (DMA_CR).......................................................................................................................440
21.3.2 Error Status Register (DMA_ES)................................................................................................................442
21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................444
21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................446
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................448
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21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................449
21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................450
21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................451
21.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................452
21.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................453
21.3.11 Clear Error Register (DMA_CERR)............................................................................................................454
21.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................455
21.3.13 Interrupt Request Register (DMA_INT)......................................................................................................455
21.3.14 Error Register (DMA_ERR)........................................................................................................................458
21.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................460
21.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................462
21.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................463
21.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................464
21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................464
21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................465
21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................466
21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................467
21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................468
21.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................468
21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................469
21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................469
21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................470
21.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........471
21.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................472
21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................474
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21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................475
21.4 Functional description...................................................................................................................................................476
21.4.1 eDMA basic data flow.................................................................................................................................476
21.4.2 Error reporting and handling........................................................................................................................479
21.4.3 Channel preemption.....................................................................................................................................481
21.4.4 Performance.................................................................................................................................................481
21.5 Initialization/application information...........................................................................................................................485
21.5.1 eDMA initialization.....................................................................................................................................485
21.5.2 Programming errors.....................................................................................................................................487
21.5.3 Arbitration mode considerations..................................................................................................................488
21.5.4 Performing DMA transfers..........................................................................................................................488
21.5.5 Monitoring transfer descriptor status...........................................................................................................492
21.5.6 Dynamic programming................................................................................................................................494
Chapter 22
External Watchdog Monitor (EWM)
22.1 Introduction...................................................................................................................................................................497
22.1.1 Features........................................................................................................................................................497
22.1.2 Modes of Operation.....................................................................................................................................498
22.1.3 Block Diagram.............................................................................................................................................499
22.2 EWM Signal Descriptions............................................................................................................................................500
22.3 Memory Map/Register Definition.................................................................................................................................500
22.3.1 Control Register (EWM_CTRL).................................................................................................................500
22.3.2 Service Register (EWM_SERV)..................................................................................................................501
22.3.3 Compare Low Register (EWM_CMPL)......................................................................................................502
22.3.4 Compare High Register (EWM_CMPH).....................................................................................................502
22.4 Functional Description..................................................................................................................................................503
22.4.1 The EWM_out Signal..................................................................................................................................503
22.4.2 The EWM_in Signal....................................................................................................................................504
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22.4.3 EWM Counter..............................................................................................................................................504
22.4.4 EWM Compare Registers............................................................................................................................504
22.4.5 EWM Refresh Mechanism...........................................................................................................................505
Chapter 23
Watchdog Timer (WDOG)
23.1 Introduction...................................................................................................................................................................507
23.2 Features.........................................................................................................................................................................507
23.3 Functional Overview.....................................................................................................................................................509
23.3.1 Unlocking and Updating the Watchdog.......................................................................................................510
23.3.2 The Watchdog Configuration Time (WCT).................................................................................................511
23.3.3 Refreshing the Watchdog.............................................................................................................................512
23.3.4 Windowed Mode of Operation....................................................................................................................512
23.3.5 Watchdog Disabled Mode of Operation......................................................................................................512
23.3.6 Low Power Modes of Operation..................................................................................................................513
23.3.7 Debug Modes of Operation..........................................................................................................................513
23.4 Testing the Watchdog...................................................................................................................................................514
23.4.1 Quick Test....................................................................................................................................................514
23.4.2 Byte Test......................................................................................................................................................514
23.5 Backup Reset Generator...............................................................................................................................................516
23.6 Generated Resets and Interrupts...................................................................................................................................516
23.7 Memory Map and Register Definition..........................................................................................................................517
23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................518
23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................520
23.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................520
23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................521
23.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................521
23.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................522
23.7.7 Watchdog Refresh Register (WDOG_REFRESH)......................................................................................522
23.7.8 Watchdog Unlock Register (WDOG_UNLOCK).......................................................................................522
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23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................523
23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................523
23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT).................................................................................524
23.7.12 Watchdog Prescaler Register (WDOG_PRESC).........................................................................................524
23.8 Watchdog Operation with 8-bit access.........................................................................................................................524
23.8.1 General Guideline........................................................................................................................................524
23.8.2 Refresh and Unlock operations with 8-bit access........................................................................................525
23.9 Restrictions on Watchdog Operation............................................................................................................................526
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................529
24.1.1 Features........................................................................................................................................................529
24.1.2 Modes of Operation.....................................................................................................................................532
24.2 External Signal Description..........................................................................................................................................533
24.3 Memory Map/Register Definition.................................................................................................................................533
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................534
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................535
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................536
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................537
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................538
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................540
24.3.7 MCG Status Register (MCG_S)..................................................................................................................541
24.3.8 MCG Auto Trim Control Register (MCG_ATC)........................................................................................543
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................543
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................544
24.4 Functional Description..................................................................................................................................................544
24.4.1 MCG Mode State Diagram..........................................................................................................................544
24.4.2 Low Power Bit Usage..................................................................................................................................549
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