AKM AK4958EG Evaluation Board Manual

Brand: AKM

Model: AK4958EG

Type: Evaluation Board Manual

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GENERAL DESCRIPTION

The AKD4958EG-B is an evaluation board for the AK4958, a 24bit stereo CODEC with a microphone/ speaker/ video

amplifiers and LDO. The AKD4958EG-B is controlled via USB port, allowing simple evaluation. It features a USB

audio device therefore audio signals can be input through the USB port from a PC. The built-in digital audio interface

realizes interfacing to digital audio systems via optical connector. For analog connections, the AKD4958EG-B has a

Line output, Microphone input, and Headphone output terminals. In addition, it has a Flash Rom that enables a

stand-alone operation.

 Ordering Guide

AKD4958EG-B --- AK4958 Evaluation Board

(Control software and USB cable are included in this package. )

NCTION

• DIR/DIT with optical input/output

• With USB-Audio device

• Equipped with three digital audio interface

- Optical Input / Output

- USB Input

- 10-pin header for external interfaces

• Analog input / output circuit for Line output, Mic input and Headphone output, and

Micro-speaker

• USB port for board control

LineOut

Speaker

AK4371

USB

(Audio)

AK4118A

SPDIF

-OUT

Out

PCM

2902B

MicIn

SPDIF

-IN

for AK4371

3.3V

1.8V GND

LDO [ T1 ]

(+5V => +3.3V)

LDO [ T2 ]

(+5V => +3.3V)

LDO [ T3 ]

(+5V => +1.8V)

USB

(CTRL)

Flash

Rom

VOUT

VIN

PORT3

PIC18F4550

AK4958EG

Figure 1.AKD4958EG-B Block Diagram

AK4958EG Evaluation Board Rev.3

AKD4958EG-B

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 Operation Sequence

1) Set up the Power Supply Lines.

2) Setup the Audio I/F Evaluation Mode.

(1) Evaluation of A/D using DIT of AK4118A.

(1-1) Setting for External Slave Mode.

(1-2) Setting for External Master Mode.

(1-3) Setting for PLL Master Mode.

(2) Evaluation of D/A using DIR of AK4118A.

(2-1) Setting for External Slave Mode. < Default >

(2-2) Setting for External Master Mode.

(3) Evaluation of A/D, D/A using external clocks.

(3-1) Setting for External Slave Mode.

(3-2) Setting for External Master Mode.

(3-3) Setting for PLL Slave Mode (Reference: BICK).

3) Jumper pins and SW Setting.

(1) Setting of other jumper pins.

(2) Setting of SW.

4) Power on.

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1) Set up the Power Supply Lines.

(1-1) In case of using the U7 (CTRL) connector. < Default >

R42 and R43 must be “Short (0ohm)”.

JP9 JP10

Figure 2.Setting of jumper pins when using the U7 (CTRL) connector.

Name of Jack Reference No.

Default Setting

Using

CTRL U7 +5V

For regulator (T1, T2 and T3) and

AK4118A, AK4371 and Digital Logic.

3.3V TM1 Open

For AVDD and TVDD of AK4958

1.8V TM2 Open

For DVDD of AK4958

GND TM3 Open

For ground

Table 1.Set up of power supply lines

(1-2) In case of using the power supply pads.

R42 and R43 must be “Open”.

JP9 JP10

Figure 3.Setting of jumper pins when using the power supply connectors.

Name of Jack Reference No.

Default Setting

Using

CTRL U7 +5V

For regulator (T1, T2 and T3) and

AK4118A, AK4371 and Digital Logic.

3.3V TM1 +2.8V～+3.6V [ typ :+3.3V ]

For AVDD and TVDD of AK4958

1.8V TM2

+1.6V～+2.0V [ typ:+1.8V ]

For DVDD of AK4958

GND TM3 0V

For ground

Table 2.Set up of power supply lines (Note 1)

Note 1.Each supply line should be distributed from the power supply unit.

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2) Setup the Audio I/F Evaluation Mode.

In case of using the AK4118A when evaluating the AK4958, both the AK4958 and AK4118A’s audio interface

formats must be matched.

Refer to the datasheet for AK4958’s audio interface format, and AK4118A’s audio interface format (Table 4).

The AK4118A operates at sampling frequency of 32 kHz or more. If the sampling frequency is slower than 32

kHz, please use other mode.

In addition, MCLK of AK4118A supports 256fs and 512fs. When evaluating in a condition except above, please

use other mode.

Refer to the datasheet for register setting of the AK4958.

(1) Evaluation of A/D using DIT of AK4118A.

(1-1) Setting for External Slave Mode

X2 (X’tal) and PORT2 (SPDIF-OUT) are used. Nothing should be connected to PORT1 (SPDIF-IN) and

PORT3.MCKI, BICK and LRCK are supplied from the AK4118A, and SDTO of the AK4958 is output to the

AK4118A. In addition, registers of the AK4958 should be set to “External Slave Mode” and setting of

AK4118A should be set to “Master Mode”.

MCKO

JP6

XTI

MCKO

JP8

MCKI

Figure 4.Setting of jumper pins for External Slave Mode

(1-2) Setting for External Master Mode

X2 (X’tal) and PORT2 (SPDIF-OUT) are used. Nothing should be connected to PORT1 (SPDIF-IN) and

PORT3.MCKI is supplied from the AK4118A, and BICK, LRCK and SDTO of the AK4958 is output to the

AK4118A. In addition, registers of the AK4958 should be set to “External Master Mode” and setting of

AK4118A should be set to “Slave Mode”.

MCKO

JP6

XTI

MCKO

JP8

MCKI

Figure 5.Setting of jumper pins for External Master Mode

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(1-3) Setting for PLL Master Mode

A reference clock of PLL is selected among the input clocks supplied to MCKI pin. The required clock to the

AK4958 is generated by an internal PLL circuit.

PORT3 and PORT2 (SPDIF-OUT) are used. Nothing should be connected to PORT1 (SPDIF-IN). MCKI is

supplied from the PORT3, and MCKO, BICK, LRCK and SDTO of the AK4958 is output to the AK4118A.

In addition, registers of the AK4958 should be set to “PLL Master Mode” and setting of AK4118A should be

set to “Slave Mode”.

R46 must be “Open”.

MCKO

JP6

XTI

MCKO

JP8

MCKI

Figure 6.Setting of jumper pins for PLL Master Mode

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(2) Evaluation of D/A using DIR of AK4118A.

Setting for input signal of AK4118A.

When using USB audio device, connect cable with the U3 (Audio) on board and USB port of PC.

(a) Select Optical jack <Default> (b) Select USB Audio device

USB-IN

JP5

OPT-IN

USB-IN

JP5

OPT-IN

Figure 7.Setting of jumper pins for input signal of AK4118A

(2-1) Setting for External Slave Mode < Default >

PORT1 (SPDIF-IN) is used. Nothing should be connected to PORT2 (SPDIF-OUT) and PORT3.

MCKI, BICK, LRCK and SDTI are supplied from the AK4118A. In addition, registers of the AK4958 should

be set to “External Slave Mode” and setting of AK4118A should be set to “Master Mode”.

MCKO

JP6

XTI

MCKO

JP8

MCKI

Figure 8.Setting of jumper pins for External Slave Mode

(2-2) Setting for External Master Mode

PORT1 (SPDIF-IN) is used. Nothing should be connected to PORT2 (SPDIF-OUT) and PORT3.

MCKI and SDTI are supplied from the AK4118A, and BICK and LRCK of the AK4958 is output to the

AK4118A.In addition, registers of the AK4958 should be set to “External Master Mode” and setting of

AK4118A should be set to “Slave Mode”.

MCKO

JP6

XTI

MCKO

JP8

MCKI

Figure 9.Setting of jumper pins for External Master Mode

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(3) Evaluation of A/D, D/A using PORT3.

(3-1) Setting for External Slave Mode

Registers of the AK4958 should be set to “External Slave Mode”.

R45 and R46 must be “Open” and S1 (1-5) must be “HHLLL”.

AK4958

DSP or P

MCKI

BICK

LRCK

SDTO

SDTI

BCLK

LRCK

SDTI

SDTO

MCKO

1fs

 32fs

MCLK

256fs, 512fs or 1024fs

Figure 10.External Slave Mode

PORT3 is used. Nothing should be connected to PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT).

MCLK, BICK, LRCK, and SDTI are input from PORT3 and SDTO of the AK4958 is output to the PORT3.

MCKO

JP6

XTI

MCKO

JP8

MCKI

Figure 11.Setting of jumper pins for External Slave Mode

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(3-2) Setting for External Master Mode

Registers of the AK4958 should be set to “External Master Mode”.

R45 and R46 must be “Open” and S1 (1-5) must be “HHLLL”.

AK4958

DSP or P

MCKI

BICK

LRCK

SDTO

SDTI

BCLK

LRCK

SDTI

SDTO

MCKO

1fs

32fs or 64fs

MCLK

256fs, 512fs or 1024fs

Figure 12.External Master Mode

PORT3 is used. Nothing should be connected to PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT).

MCLK and SDTI are input from PORT3 and BICK, LRCK and SDTO of the AK4958 is output to the

PORT3.

MCKO

JP6

XTI

MCKO

JP8

MCKI

Figure 13.Setting of jumper pins for External Master Mode

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(3-3) Setting for PLL Slave Mode (Reference Clock: BICK pin)

Registers of the AK4958 should be set to “PLL Slave Mode” (Reference Clock: BICK pin).

R45 and R46 must be “Open” and S1 (1-5) must be “HHLLL”.

AK4958

DSP or P

MCKI

BICK

LRCK

SDTO

SDTI

BCLK

LRCK

SDTI

SDTO

MCKO

1fs

32fs, 64fs

Figure 14.PLL Slave Mode (PLL Reference Clock: BICK pin)

PORT3 is used. Nothing should be connected to PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT).

BICK, LRCK and SDTI are input from PORT3. SDTO of the AK4958 is output to the PORT3.

MCKO

JP6

XTI

MCKO

JP8

MCKI

Figure 15.Setting of jumper pins for PLL Slave Mode

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3) Jumper pins and SW Setting.

(1) Setting of other jumper pins.

[JP11]: Not to Use.

[JP20 (RIN)]: The selection of input signal from RIN pin.

RIN1 : Connect to RIN1 pin. < Default >

RIN2 : Connect to RIN2 pin.

[JP21 (MPWRR)]: The selection of MIC-power of RIN pin.

OPEN : MIC-power is not supplied. < Default >

SHORT : MIC-power is supplied.

[JP22 (MPWRL)]: The selection of MIC-power of LIN pin.

OPEN : MIC-power is not supplied. < Default >

SHORT : MIC-power is supplied.

[JP23 (LIN)]: The selection of input signal from LIN pin.

LIN1 : Connect to LIN1 pin. < Default >

LIN2 : Connect to LIN2 pin.

[JP24 (CIF)]: The selection of Serial Control I/F (Note 2)

1, 2 pin and 3, 4 pin SHORT : “3-wire Serial Control Mode” < Default >

1, 3 pin and 2, 4 pin SHORT : “I2C-bus Control Mode”

wire Serial Control Mode

I2C

busControl Mode

Figure 16.Setting of jumper pins with Serial Control I/F

[JP25 (SPN)]: The selection of micro-speaker (LS1).

Short : Connect to micro-speaker. < Default >

Open : No connected.

[JP26 (SPP)]: The selection of micro-speaker (LS1).

Short : Connect to micro-speaker. < Default >

Open : No connected.

Note 2. When using “3-wire Serial Control Mode”, R1 on the sub-board is “Open” and R2 on the sub-board is

“10kohm”. When using “I2C-bus Control Mode”, R1 on the sub-board is “10kohm” and R2 on the

sub-board is “Open”.

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(2) Setting of SW.

Upper-side is “ON(H)” and lower-side is “OFF(L)”.

[S1] (SW DIP-5): Mode setting for AK4118A.

No. Name ON (“H”) OFF (“L”) Default

1 DIF2

Audio I/F Format Setting for AK4118A

See Table 4

2 DIF1 OFF

3 DIF0 OFF

4 OCKS1

Master Clock setting for AK4118A

See Table 5

OFF

5 PDN AK4118A is Power-up. AK4118A is Power-down ON

Table 3. Mode Setting for AK4118A

Mode DIF2 DIF1 DIF0 DAUX SDTO

LRCK BICK

I/O I/O

0 L L L 24bit, Left justified 16bit, Right justified H/L O 64fs O

L L

H 24bit, Left justified 18bit, Right justified H/L O 64fs O

2 L H L 24bit, Left justified 20bit, Right justified H/L O 64fs O

3 L H H 24bit, Left justified 24bit, Right justified H/L O 64fs O

4 H L L 24bit, Left justified 24bit, Left justified H/L O 64fs O

Default

5 H L H 24bit, I

S 24bit, I

S L/H O 64fs O

6 H H L 24bit, Left justified 24bit, Left justified H/L I

-128fs

7 H H H 24bit, I

S 24bit, I

S L/H I

-128fs

Table 4.Audio I/F Format Setting for AK4118A

OCKS1 MCKO1

L 256fs

Default

H 512fs

Table 5.Master Clock setting for AK4118A

4) Power on.

After power-up, the AK4958 and the AK4118A should be reset once.

Reset and power-up sequence of the AK4118A.

1. S1 (5): OFF; power-down and reset.

2. S1 (5): ON; power-up.

Reset and power-up sequence of the AK4958.

1. To start the control software.

2. [PDN: H (L)] button is set to [PDN: L] (Power-down and Reset).

3. [PDN: H (L)] button is set to [PDN: H] (Power-up).

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 Indication for LED

[D1] (FLASH-ROM) : While the LED is turned on, Flash ROM is available.

 Control Port

It is possible to control AKD4958EG-B via general USB port. Connect cable with the U7 (CTRL) on board and PC.

Control software is packed with this board. The software operation sequence is included in the evaluation board

manual.

 Flash ROM

Using the included control software, you can save the configuration register on the evaluation board to Flash ROM

(Note 3).

In addition, the register settings loaded in Flash ROM can be loaded with the following steps in the evaluation

board.

1. To set the Bank Number using the switch S2.

2. The switch S3 is set to ON(“H”) side.

To save the configuration registers to Flash ROM is "Control Software Manual" for "FlashROM" please refer to the

section.

Note 3.When using Flash ROM function, "3-wire Serial Control Mode" must be selected.

[S2] (SW DIP-6): Setting for Bank Number.

There are a total of 32 Bank Number (No.0 ~ No.31), Bank Number sets in binary.

FSEL0 is LSB, and FSEL4 is MSB.

Upper-side is “ON(H)” and lower-side is “OFF(L)”.

No. Name ON (“H”) OFF (“L”) Default

1 FSEL0

Bank No.0 ～31

OFF

2 FSEL1 OFF

3 FSEL2 OFF

4 FSEL3 OFF

5 FSEL4 OFF

6 FSEL5

Not to use.

Fixed “OFF”.

OFF

Table 6. Setting for FLASH-ROM Bank Number

[S3] (Flash-Load): When loading the register setting from Flash ROM, switch S3 is set to ON(“H”) side.

When operating register setting by the enclosed control software, switch S3 should be set to OFF(“L”) side.

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■ Analog Input / Output Circuits

1) Input circuit

(1-1) MIC/LINE1, 2 input circuit (except for Digital-MIC circuit).

RIN1

RIN2

LIN1

LIN2

MPWR

MPWRR

JP21

MPWRL

JP22

LIN

JP23

RIN

JP20J3

MIC

2.2k 2.2k

Figure 17.Circuit diagram of MIC/LIN1, 2 input

Please select the input to use by JP23 (LIN) and JP20 (RIN).

(1-2) Video input circuit.

0.047u

J10

VIN

Figure 18.Circuit diagram of Video input

(1-3) BEEP input circuit.

TP20

MIN

01u

MIN

Figure 19.Circuit diagram of BEEP input

BEEP

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2) Output circuit

(2-1) LINE output circuit.

20k 20k

220

LINE

ROUT

LOUT

Figure 20.Circuit diagram of LINE output

(2-2) Video output circuit.

J11

VOUT

1 2

VOUT

Figure 21.Circuit diagram of Video output

(2-3) Speaker output circuit.

JP25 SPN

JP26 SPP

(open)

LS1

SPEAKER

SPN

SPP

Figure 22.Circuit diagram of Speaker output

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Control Software Manual

■ Evaluation Board and Control Software Settings

1.Set up the evaluation board as needed, according to the previous terms.

2.Connect the evaluation board and PC with a USB cable.

3.The USB control is recognized as HID (Human Interface Device) on the PC

4.Double-click the icon “akd4958eg-b.exe” to open the control program. (Note 5)

When the screen does not display “AKDUSBIF-B” at bottom left, reconnect the PC and the USB cable, and push

the [Port Reset] button.

5.Begin evaluation by following the procedure below.

Figure 23. Window of Control Soft

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■ Operation Overview

Function and Register map are controlled by this control software. These controls may be selected by the upper tabs.

Frequently used Buttons, such as the register initializing button “Write Default”, are located outside of the switching

tab window. Refer to the “■ Dialog Box” section for details of each dialog box setting.

1. [Port Reset]: Resets the connection to PC.

Click this button when connecting USB cable after the control software set up..

2. [Write Default]: Register Initialization.

When the device is reset by a hardware reset, use this button to initialize the registers.

3. [All Write]: Executes write commands for all registers displayed. (Note 4)

4. [All Read]: Executes read commands for all registers displayed. (Note 4)

5. [Save]: “Save Address of Register” dialog box pops up.

6. [Load]: Executes data write from a saved file.

7. [All Reg Write]: “All Reg Write” dialog box pops up.

8. [Sequence]: “Sequence” dialog box pops up.

9. [Sequence (File)]: “Sequence (File)” dialog box pops up.

10. [Read]: Reads current register settings and displays to the register area (on the right of the main window).

This is different from [All Read] button as it does not reflect to the register map. It only displays register

values in hexadecimal numbers.

11. [PDN: H (L)]: Setup of an input at PDN pin. (Note 5)

Note 4. After [All Write] or [All Read] are executed, “RBANK bit” is set to "1".

Note 5. After Power-up the evaluation board, put the “PDN” button to “L” and return to “H” to release the

power-down state. After “PDN” button becomes “H”, “Dummy Command” is executed.

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■ Tab Functions

1. [Function] Tab: Function Control

When a button in the “Function” frame is clicked, a sequential process is executed.

When other button is clicked, the setting dialog opens.

(Refer to the “■ Sequential process” section for details of each dialog box setting, or “■ Dialog Box” section for

details of each dialog box setting.)

Figure 24. [Function] Window

[Function] button : Executes a sequential process shown on each button. (Refer to 1- 1)

Setting dialog button : Opens a setting dialog. (Refer to 1- 2)

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1- 1. [Function] Button

Figure 25. [Function] Button

A function button executes the sequence process shown on the each button and updates several registers.

These functions are mainly for path settings.

Function Name

Description

Input

Output

Path

Rec_MIC+18dB_ALC MIC Input Recording

(Stereo)

LIN1(2),

RIN1(2)

SDTO LIN1(2),RIN1(2)→MIC-AMP(+18dB)→

ADC→Digital Filter→SDTO

Rec_D-MIC_ALC Digital MIC Input

Recording (Stereo)

DMDAT SDTO DMDAT→Digital Filter→SDTO

(When Digital MIC used, LIN1 changes to

DMDAT.)

Playback_Lineout Stereo Line Output SDTI LOUT,

ROUT

SDTI→Digital

Filter→DAC→LOUT,ROUT

Loopback_Lineout Loopback

(MIC Input Recording,

Stereo Line Output)

LIN1(2),

RIN1(2)

LOUT,

ROUT

LIN1(2),RIN1(2)→ADC→

Digital Filter→DAC→LOUT,ROUT

Playback_SPK

(Bass Boost ON)

SPK Output

(Bass Boost ON)

SDTI SPP,

SPN

SDTI→Digital Filter→Bass

Boost→DAC→SPP,SPN

Table 7. Sequence Process Setting

*The setting of MIC/Line Input, Clock mode and I/F mode are not changed. The default values are follows.

MIC / Line Input : LIN1/RIN1

Clock Mode : EXT mode (slave)

I/F mode : 24bit MSB Justified

Sampling Frequency : 48 kHz

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1- 2. Setting Dialog Button

Figure 26. Setting Dialog button

[MIC – ADC Setting] button : Opens “MIC_ADC Setting” dialog box.

[Digital MIC Setting] button : Opens “Digital MIC Setting” dialog box.

[System Clock Audio I/F] button : Opens “System Clock & Audio I/F” dialog box.

[ALC Setting] button : Opens “ALC Setting” dialog box.

[DAC Setting] button : Opens “DAC_LINE/SPK Setting” dialog box.

[Digital Filter] button : Opens “Programmable Digital Filter Setting” dialog box.

[BEEP Setting] button : Opens “BEEP Setting” dialog box.

[MIC Gain Adjustment] button : Opens “MIC Gain Adjustment” dialog box.

[Video Setting] button : Opens “Video Setting” dialog box.

[Bass Boost 3 Band DRC] button : Opens “Bass Boost & 3 Band DRC control” dialog box.

[AK4371 Setting] button : Opens “AK4371” dialog box.

[FlashRom Setting] button : Opens “FlashRom Setting” dialog box.

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2. [REG] [RBANK0] [RBANK1] Tab: Register Map

This tab is for register read and write.

Each bit on the register map is a push-button switch. The register is updated by mouse operation.

Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).

Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray)

Grayed out registers are Read-Only registers. They cannot be controlled.

The registers which are not defined on the datasheet are indicated as “---”.

Figure 27. [REG] Window

Note 6. “RBANK bit” is changed automatically at the time of each register Write/Read of BANK0 and

BANK1.

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AKM AK4958EG Evaluation Board Manual

AKM AK4958EG Evaluation Board Manual

AKM AK4958EG Evaluation Board Manual

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