Delta Tau Acc-77 Owner's manual

Brand: Delta Tau

Model: Acc-77

Type: Owner's manual

^1 USER MANUAL

1^ USER MANUAL

^2 Accessory 77

Preliminary Documentation

^3 64 Inputs Interface for SNAP I/O from Opto-22™

^4 3A0-603774-xUxx

^5 November 12, 2004

Single Source Machine Control Power // Flexibility // Ease of Use

21314 Lassen Street Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 // www.deltatau.com

This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are

unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained in

this manual may be updated from time-to-time due to product improvements, etc., and may not

conform in every respect to former issues.

To report errors or inconsistencies, call or email:

Delta Tau Data Systems, Inc. Technical Support

Phone: (818) 717-5656

Fax: (818) 998-7807

Email: support@deltatau.com

Website: http://www.deltatau.com

Operating Conditions

All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain

static sensitive components that can be damaged by incorrect handling. When installing or handling

Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials. Only

qualified personnel should be allowed to handle this equipment.

In the case of industrial applications, we expect our products to be protected from hazardous or

conductive materials and/or environments that could cause harm to the controller by damaging

components or causing electrical shorts. When our products are used in an industrial environment,

install them into an industrial electrical cabinet or industrial PC to protect them from excessive or

corrosive moisture, abnormal ambient temperatures, and conductive materials. If Delta Tau Data

Systems, Inc. products are directly exposed to hazardous or conductive materials and/or

environments, we cannot guarantee their operation.

Dispose in accordance with applicable regulations.

Accessory 77 User Manual – Preliminary Documentation 
Table of Contents  i 
Table of Contents 
INTRODUCTION ....................................................................................................................................................... 1 
Parity Checking ......................................................................................................................................................... 1 
Port Headers .............................................................................................................................................................. 1 
Interconnecting Cable Options .................................................................................................................................. 2 
Reference Documents................................................................................................................................................ 2 
INSTALLATION......................................................................................................................................................... 3 
Hardware ................................................................................................................................................................... 3 
Quick Setup Guide .................................................................................................................................................... 3 
ACC-77 LED indicators........................................................................................................................................ 4 
Internal Jumpers ................................................................................................................................................... 4 
SNAP I/O MODULES ................................................................................................................................................. 5 
Inputs .................................................................................................................................................................... 5 
I/O Map Inputs ...................................................................................................................................................... 6 
MULTIPLEX ADDRESS MAP ................................................................................................................................. 9 
JTHW Address Control (DIP Switch Setting, SW1) ................................................................................................. 9 
PROCESSING ACC-77 INPUTS ............................................................................................................................. 11 
When to Access ACC-77 ........................................................................................................................................ 11 
Software .................................................................................................................................................................. 11 
Development Tools ............................................................................................................................................. 11 
Quick Start .......................................................................................................................................................... 11 
Map the I/O Points to PMAC M-Variables ............................................................................................................. 12 
Things to Know: .................................................................................................................................................. 12 
ACC-77 SETUP ......................................................................................................................................................... 13 
Image Word Variables............................................................................................................................................. 13 
PMAC Location of Image Words............................................................................................................................ 13 
Open Memory — Standard PMAC ..................................................................................................................... 13 
DPRAM — Standard PMAC ............................................................................................................................... 13 
Turbo PMAC Location of Image Words ................................................................................................................. 14 
Open Memory Turbo PMAC ............................................................................................................................... 14 
DPRAM Standard Turbo PMAC ......................................................................................................................... 14 
Image Words ........................................................................................................................................................... 15 
Individual Pieces of Image Words .......................................................................................................................... 15 
PMAC Memory Locations .................................................................................................................................. 15 
PMAC Dual-Ported RAM Locations .................................................................................................................. 16 
Parity Error Bit ........................................................................................................................................................ 16 
Update the Inputs Using a PLCC ............................................................................................................................ 16 
M-Variable Assignments ......................................................................................................................................... 17 
CONNECTOR PINOUTS......................................................................................................................................... 19 
P1 and P2 (DB25-Pin Header) ........................................................................................................................... 19 
SNAP I/O COMPONENT INSTALLATION ......................................................................................................... 21 
Standard Panel Mounting ........................................................................................................................................ 21 
Preferred Method: Template .............................................................................................................................. 21 
Alternate Method: Prefabrication of Panels ....................................................................................................... 21 
Center-to-Center Length: All SNAP Rack Models .............................................................................................. 22 
Digital Input Modules ............................................................................................................................................. 22 
Features .............................................................................................................................................................. 23 
AC Input Modules Specifications ........................................................................................................................ 24 
DC Input Modules Specifications ....................................................................................................................... 25 
AC and DC Input Modules.................................................................................................................................. 26 

    Accessory 77 User Manual – Preliminary Documentation 
ii Table of Contents 
All Models except MA ......................................................................................................................................... 27 
All MA Modules .................................................................................................................................................. 28 
All Models ........................................................................................................................................................... 28 
SNAP Digital Module Mounted on SNAP Rack — All Models ........................................................................... 29 
SNAP-D64RS Rack ................................................................................................................................................ 29 
Specifications for All Models .............................................................................................................................. 30 
Operating Requirements ..................................................................................................................................... 30 
Dimensional Drawings for All Models ............................................................................................................... 30 
PREVENTING CONFLICTS .................................................................................................................................. 33 
 
 
 

Accessory 77 User Manual – Preliminary Documentation

Introduction 1

INTRODUCTION

PMAC’s ACC-77 is a brain module that plugs into the OPTO SNAP I/O rack (D64RS) in place of the

OPTO 22-brain module. This I/O Accessory connects the PMAC1 or PMAC2, Turbo or non-Turbo,

JTHW Port to the industry standard OPTO22 SNAP family of I/O racks. Each rack provides 64 input

digital I/O fixed per each interface module. One ACC-77 is required for each rack.

A three foot cable is included to connect between PMAC’s JTHW port and the ACC-77 (IDC26 to DB25

connectors). This module plugs into the OPTO22 SNAP-D64RS rack and is compatible with all SNAP

Digital I/O Modules.

ACC-77 is one of a series of I/O accessories for PMAC that connects to the OPTO SNAP I/O. The other

version is ACC-76 – the 64-bit SNAP I/O Interface board, DB25 connector.

All of the above accessories use the JTHW multiplex address scheme, and several of them may be daisy-

chained to a single PMAC.

Up to 32 ACC-77 may be connected to a single PMAC, which gives a possible 2048 input output lines in

addition to those available on the PMAC board and on the parallel I/O expansion boards (ACC-14).

ACC-77 communicates to PMAC via its JTHW connector through the supplied flat cable.

ACC-77 also supports a local watchdog timer feature independent of PMAC.

 Individual optical isolation of all Input points

 RC filter with 1 msec time constant on all inputs

 Parity checking on serial communications with PMAC

Parity Checking

Parity checking is done on all serial communications between the PMAC and the ACC-77. This requires

PMAC firmware version 1.16 or newer.

When PMAC sends data to the ACC-77 32-bit output word by writing to the TWS M-Variable pointing to

that word, the ACC-77 evaluates the parity bits sent with that word and compares them to the parity bits it

calculated itself. If there is a difference, the output word is ignored (the outputs stay in the state of the

last successful write) and PMAC is notified of a parity error. PMAC shows this error by setting bit 6 of

the global status register X:$0003 (X:$000006 in Turbo PMAC). The program can check this bit with an

M-Variable to see if the data must be sent again.

When the ACC-77 sends the 32-input word to PMAC, PMAC reads the TWS M-Variable pointing to that

word and the ACC-77 creates parity bits that are sent with the word. PMAC evaluates the parity bits sent

with that word and compares them to the parity bits it calculated itself. If there is a difference, PMAC

shows the error by setting this parity error bit. The program can check this bit with an M-Variable to see

if the data must be sent again.

Port Headers

The ACC-77 has two 25-pin DB headers (female), P1 and P2, that can be used for connection of boards to

the PMAC JTHW Multiplexer port. The identical signals are present on both connectors with a simple

pass-through on the board, so it is possible to use the second header to connect to the next accessory

board daisychained to the multiplexer port, instead of a multi-drop cable.

Accessory 77 User Manual – Preliminary Documentation

2 Introduction

Interconnecting Cable Options

Shielded Cable

MDI Part

Number

Part Number

For ACC-76 or ACC-77, shielded cable-30cm(12in) interconnecting

between multiple ACC-76 and ACC-77 modules

MDI-PBSC-030

200-603773-0120

For ACC-76 or ACC-77, shielded cable-60cm(24in) interconnecting

between multiple ACC-76 and ACC-77 modules

MDI-PBSC-060

200-603773-0240

For ACC-76 or ACC-77, shielded cable-90cm(36in) interconnecting

between multiple ACC-76 and ACC-77 modules

MDI-PBSC-090

200-603773-0360

For ACC-76 or ACC-77, shielded cable-180cm(72in) interconnecting

between multiple ACC-76 and ACC-77 modules

MDI-PBSC-180

200-603773-0720

Reference Documents

Have the following reference documentation available:

Non-Turbo

 PMAC User Manual and Software Reference Manual

 PMAC Hardware Reference Manual (use the Hardware reference of the board being used)

Turbo

 Turbo User manual and Software Reference Manual

 Turbo PMAC/UMAC/QMAC Hardware reference Manual (use the Hardware reference of the board

being used)

 Opto22’s SNAP I/O Reference Manuals

Accessory 77 User Manual – Preliminary Documentation

Introduction 3

INSTALLATION

Hardware

The following checklist provides a quick start for hardware installation. Refer to the appropriate PMAC

Hardware Reference manual and the appropriate Opto22 Snap I/O Hardware manual for more detailed

information.

 Install the backplane-mounting track on the panel.

 Install the Opto22 backplane in the track.

 Connect 5Vdc/0Vdc(Digital GND)/P.E. to the terminal block on the Opto22 rack.

 Set the address switches on ACC-77 (SW1).

 Install ACC-77 on the backplane.

 Install the Input Modules in slots 0 thru 15.

 Connect one end (DB) of the 25-conductor ribbon cable provided to ACC-77 (P1 is closer to the Dip

Switch).

 Connect one end (IDC) of the 25-conductor ribbon cable provided to PMAC’s JTHW port.

 Connect the field wiring to each I/O module as required.

The following interconnection diagram illustrates the connection of multiple ACC-77s to a PMAC. The

connection for a ACC-77 is the same except ACC-77 supports only inputs. The location of the JTHW

interface connector on PMAC varies depending on which PMAC is used. Refer to the appropriate PMAC

Hardware Reference manual to confirm the location and designation of the JTHW port on the PMAC.

ACC-77/76

Quick Setup Guide

Use the following procedure to begin the process of integrating ACC-77 into the application:

1. Remove all power from the system.

2. Install the SNAP I/O and ACC-77 interface.

3. Install the interconnecting cabling.

4. Set the Address of the ACC-77 interface to Board #1.

5. Disable all motors, drives, hydraulics or other devices that can cause motion.

6. Connect a PC to the PMAC either serially or via a bus connection.

7. Apply power to the PMAC and to the SNAP I/O rack.

8. Set I5=0 to disable all PLC programs.

9. Verify that Firmware version 1.16x or later is used. (Enter ver in the terminal window.)

Accessory 77 User Manual – Preliminary Documentation

4 Installation

10. There should be two green LEDs and one red LED illuminated on ACC-77.

11. Back-up the existing PMAC Setup and Programs.

12. Verify the back up.

13. Set up the ACC-77 (Use the manual and the examples that follow).

14. ACC-77 implements watchdog circuitry that turns all inputs off if PMAC fails to communicate to

ACC-77 for more than one second. This feature can be disabled by installing E18 jumper in ACC-77,

but it is not recommended.

The integration of the I/O into the application can begin.

ACC-77 LED indicators

LED

Description

+5Vdc (On the Left)

This green LED indicates the presence of 5Vdc from PMAC. ACC-77

provides optical isolation between PMAC and the logic side of the Opto22

SNAP modules. The 5V required for the PMAC side of the interface is

present on the 26-conductor ribbon cable connected to the JTHW port of

PMAC (Board #1).

+5Vdc (On the Right)

This green LED indicates the presence of 5Vdc from the Opto22

backplane. The system will not work without this connected.

5Vdc must be supplied to this terminal strip to power the logic side of the

SNAP I/O modules (Board #2).

Watchdog (On the Right)

The red/WD LED is illuminated if the watchdog is tripped (Board #2).

ACC-77 incorporates a watchdog circuit that turns the outputs off if

communication with PMAC is lost for more that one second. Installing

jumper E18, in ACC-77 can disable this feature, but it is not recommended.

Internal Jumpers

E Point

Default

Description

OFF

Connects ACC-76 data to PMAC DAT0 Line, SDI_2 Inputs 33-64

Connects ACC-76 data to PMAC DAT1 Line, SDI_2 Inputs 33-64

OFF

Connects ACC-76 data to PMAC DAT2 Line, SDI_2 Inputs 33-64

OFF

Connects ACC-76 data to PMAC DAT3 Line, SDI_2 Inputs 33-64

OFF

Connects ACC-76 data to PMAC DAT4 Line, SDI_2 Inputs 33-64

OFF

Connects ACC-76 data to PMAC DAT5 Line, SDI_2 Inputs 33-64

OFF

Connects ACC-76 data to PMAC DAT6 Line, SDI_2 Inputs 33-64

OFF

Connects ACC-76 data to PMAC DAT7 Line, SDI_2 Inputs 33-64

Connects ACC-76 data to PMAC DAT0 Line, SDI_0 Inputs 1-32

E10

OFF

Connects ACC-76 data to PMAC DAT1 Line, SDI_0 Inputs 1-32

E11

OFF

Connects ACC-76 data to PMAC DAT2 Line, SDI_0 Inputs 1-32

E12

OFF

Connects ACC-76 data to PMAC DAT3 Line, SDI_0 Inputs 1-32

E13

OFF

Connects ACC-76 data to PMAC DAT4 Line, SDI_0 Inputs 1-32

E14

OFF

Connects ACC-76 data to PMAC DAT5 Line, SDI_0 Inputs 1-32

E15

OFF

Connects ACC-76 data to PMAC DAT6 Line, SDI_0 Inputs 1-32

E16

OFF

Connects ACC-76 data to PMAC DAT7 Line, SDI_0 Inputs 1-32

E17

ON:1-2

Factory use only

E18

OFF

Install to disable ACC-76 watchdog circuitry

Note: Only one of the jumpers E1 thru E8 should be installed and only one of the jumpers

E9 to E16 should be installed.

The OEM should never have to adjust the E-point jumpers from their factory default

settings.

*All the jumpers are on Board #1, P/N 603771-10x

Accessory 77 User Manual – Preliminary Documentation

SNAP I/O Modules 5

SNAP I/O MODULES

Field wiring is connected to the terminals of the Opto22 SNAP I/O modules. The purpose of the SNAP

module is to isolate real world signals from PMAC. The isolation is achieved by using optical isolation

components in the SNAP module to separate PMAC’s ground from the I/O ground. In addition, the

SNAP modules provide the opportunity to condition the I/O signals. Typical I/O devices operate a 24Vdc

or 120VAC which is incompatible with PMAC, as well as most other electronic devices operating at

5VDC. A wide variety of SNAP modules are available to accommodate different I/O characteristics.

Each SNAP I/O module regardless of its output characteristics, conditions the I/O to a 5VDC signal.

These 5Vdc signals are communicated along the back plane to ACC-77.

ACC-77 interacts with the 5Vdc signals communicated along the backplane from the SNAP I/O modules

and communicates them to PMAC. Since many need to connect more I/O to PMAC than there are I/O

lines on PMAC, a multiplexed I/O interface (ACC-34 family of I/O devices) using the JTHW port of

PMAC was developed. ACC-77 emulates an ACC-34AA device, except that it supports inputs only.

The original use of the JTHW interface was to multiplex thumb-wheel switch data into PMAC using

address lines and an 8-bit data bus. A serial communication method was developed for this interface to

allow more I/O to be interfaced to PMAC. The TWS data format is used in PMAC programs to acquire

this serial thumb-wheel data. Refer to the PMAC Software Reference for more details on this format and

its usage.

ACC-77 implements the circuitry to do the serial to parallel and parallel to serial data conversion required

by the interface. In addition, ACC-77 implements error detection in the form of parity around the data

packets communicated to PMAC.

The JTHW connector provides the 5Vdc, powering the interface electronics providing optical isolation

between PMAC and ACC-77.

Inputs

ACC-77 adds a parity bit to the outgoing data. PMAC accepts the new input data and sets a bit in its

global status word indicating a parity error if there is one. The user (programmer) must decide if utilizing

this information is important. This bit be should be evaluated after each read from ACC-77. If a parity

error exists, the software should ignore the current input data and re-read the input until no parity exists.

If good input data is not received within a certain time or after a number of tries, a global fault flag should

be set indicating the existence of a fatal communication fault. An example of this technique is given in

the Software section of this manual.

Note:

Error detection was added to the serial data frames transmitted by the interface

hardware in Version 1.16 of the PMAC firmware. If the PROM version is not

version 1.16 or later, obtain an update.

Accessory 77 User Manual – Preliminary Documentation

6 SNAP I/O Modules

I/O Map Inputs

The following table summarizes the mapping of the inputs from the SNAP modules to ACC-77:

ACC-77

Input Bit

Backplane

Slot #

SNAP

Module

Channel

Name

Usage

In0

General Purpose Input

In1

General Purpose Input

In2

General Purpose Input

In3

General Purpose Input

In4

General Purpose Input

In5

General Purpose Input

In6

General Purpose Input

In7

General Purpose Input

In8

General Purpose Input

In9

General Purpose Input

In10

General Purpose Input

In11

General Purpose Input

In12

General Purpose Input

In13

General Purpose Input

In14

General Purpose Input

In15

General Purpose Input

In16

General Purpose Input

In17

General Purpose Input

In18

General Purpose Input

In19

General Purpose Input

In20

General Purpose Input

In21

General Purpose Input

In22

General Purpose Input

In23

General Purpose Input

In24

General Purpose Input

In25

General Purpose Input

In26

General Purpose Input

In27

General Purpose Input

In28

General Purpose Input

In29

General Purpose Input

In30

General Purpose Input

In31

General Purpose Input

In 33

General Purpose Input

In 34

General Purpose Input

In 35

General Purpose Input

In 36

General Purpose Input

In 37

General Purpose Input

In 38

General Purpose Input

In 39

General Purpose Input

Accessory 77 User Manual – Preliminary Documentation

SNAP I/O Modules 7

ACC-77

Input Bit

Backplane

Slot #

SNAP

Module

Channel

Name

Usage

In 40

General purpose Input

In 41

General purpose Input

In 42

General purpose Input

In 43

General purpose Input

In 44

General purpose Input

In 45

General purpose Input

In 46

General purpose Input

In 47

General purpose Input

In 48

General purpose Input

In 49

General purpose Input

In 50

General purpose Input

In 51

General purpose Input

In 52

General purpose Input

In 53

General purpose Input

In 54

General purpose Input

In 55

General purpose Input

In 56

General purpose Input

In 57

General purpose Input

In 58

General purpose Input

In 59

General purpose Input

In 60

General purpose Input

In 61

General purpose Input

In 62

General purpose Input

In 63

General purpose Input

In 64

General purpose Input

Accessory 77 User Manual – Preliminary Documentation

8 SNAP I/O Modules

Accessory 77 User Manual – Preliminary Documentation

Multiplex Address Map 9

MULTIPLEX ADDRESS MAP

Each ACC-77 occupies eight bytes of address space on the PMAC’s JTHW multiplex memory space.

This memory space is 8-bits wide which provides the ability to daisy chain 32 (256/8) ACC-34Xs

together (or a combination of ACC-76/77, ACC-34XS, ACC-18s and ACC-8D OPT7s). The 5-bit DIP-

switch, SW1, determines the address of each ACC-77 board on the allocated memory space. Port A

occupies the base address (i.e. bytes 0, 8, 16 etc.) and Port B occupies the base address plus 4 (i.e. bytes 4,

12, 20 etc.). The following table shows how SW1 should be set for one or more ACC-77 boards

connected to the same PMAC.

JTHW Address Control (DIP Switch Setting, SW1)

Each I/O device connected to the JTHW port must be set up at a specific base address. The following

table gives the valid switch settings and the corresponding M-Variable setup:

Board

Byte

(Port A &

Port B)

SW1 Dip Switch

Inputs 1 to 32

Inputs 33 to 64

0 & 4

Mxxx->TWS:1

Mxxx->TWS:3

8 & 12

OFF

Mxxx->TWS:9

Mxxx->TWS:11

16 & 20

OFF

Mxxx->TWS:17

Mxxx->TWS:19

24 & 28

OFF

Mxxx->TWS:25

Mxxx->TWS:27

32 & 36

OFF

Mxxx->TWS:33

Mxxx->TWS:35

40 & 44

OFF

Mxxx->TWS:41

Mxxx->TWS:43

48 & 52

OFF

Mxxx->TWS:49

Mxxx->TWS:51

56 & 60

OFF

Mxxx->TWS:57

Mxxx->TWS:59

64 &68

OFF

Mxxx->TWS:65

Mxxx->TWS:67

72 & 76

OFF

Mxxx->TWS:73

Mxxx->TWS:75

80 & 84

OFF

Mxxx->TWS:81

Mxxx->TWS:83

88 &92

OFF

Mxxx->TWS:89

Mxxx->TWS:91

96 & 100

OFF

Mxxx->TWS:97

Mxxx->TWS:99

104 & 108

OFF

Mxxx->TWS:105

Mxxx->TWS:107

112 & 116

OFF

Mxxx->TWS:113

Mxxx->TWS:115

120 & 124

OFF

Mxxx->TWS:121

Mxxx->TWS:123

128 & 132

OFF

Mxxx->TWS:129

Mxxx->TWS:131

136 & 140

OFF

Mxxx->TWS:137

Mxxx->TWS:139

144 & 148

OFF

Mxxx->TWS:145

Mxxx->TWS:147

152 & 156

OFF

Mxxx->TWS:153

Mxxx->TWS:155

160 & 164

OFF

Mxxx->TWS:161

Mxxx->TWS:163

168 & 172

OFF

Mxxx->TWS:169

Mxxx->TWS:171

176 & 180

OFF

Mxxx->TWS:177

Mxxx->TWS:179

184 &188

OFF

Mxxx->TWS:185

Mxxx->TWS:187

192 & 196

OFF

Mxxx->TWS:193

Mxxx->TWS:195

200 & 204

OFF

Mxxx->TWS:201

Mxxx->TWS:203

208 & 212

OFF

Mxxx->TWS:209

Mxxx->TWS:211

216 & 220

OFF

Mxxx->TWS:217

Mxxx->TWS:219

124 & 228

OFF

Mxxx->TWS:225

Mxxx->TWS:227

232 & 236

OFF

Mxxx->TWS:233

Mxxx->TWS:235

240 & 244

OFF

Mxxx->TWS:241

Mxxx->TWS:243

248 & 252

OFF

Mxxx->TWS:249

Mxxx->TWS:251

This table shows the daisy-chain board address relationship with respect to the 5-bit (SW1) DIP position

setting.

Note: ON=Closed, OFF=Open. To turn off a switch, push down on the open side. To turn on a switch, push

down on the numbered side.

Accessory 77 User Manual – Preliminary Documentation

10 Multiplex Address Map

Accessory 77 User Manual – Preliminary Documentation

Processing ACC-77 Inputs 11

PROCESSING ACC-77 INPUTS

Because the PMAC interface to the ACC-77 I/O board is by full 32-bit words transmitted serially (even

when access to only a single bit is desired), consider carefully how the interface is done and how

frequently. Care must be taken also to work efficiently with the data so that PMAC is not bogged down

with slow serial reads and writes and time-consuming logic to assemble and disassemble I/O words.

The recommended strategy is to keep images of each input or output word in PMAC’s internal memory,

or in the dual-ported RAM (DPR). The input words are copied into their image words, and the output

words are copied from their image words. Most program operations deal with these image words; this

way, slow transfer to or from an ACC-77 board is performed less frequently. During the act of copying,

bit inversion can be performed also with the exclusive-or function.

When to Access ACC-77

The actual reads and writes for an ACC-77 board can be done only in a background PLC program (PLC

1-31) or through on-line commands which are executed between PLC programs. Motion programs and

PLC 0 cannot directly access this I/O (they can work only with the image words). Reading an input word

from an ACC-77 is simply a question of using the TWS-form M-Variable for that word on the right side

of an equation. Usually, this operation simply copies the input word into its internal image variable.

Usually, ACC-77 I/O is treated the same way that a traditional PLC treats its I/O; all of the inputs are read

at the beginning of a PLC software scan. In between, all the processing of the variables is done while

working with the internal image words.

Software

The OEM is responsible for developing the software to access the SNAP I/O and to utilize this

information in a system. During the development and testing of the ACC-77, there are a number of

routines, which may be helpful in the development of the OEM software. These routines are provided for

informational purposes only. Delta Tau, Inc., does not accept any responsibility for the OEM application

or equipment. The OEM must review the software provided, decide how much is applicable to a specific

application, and develop the software appropriate to the application at hand.

Development Tools

The PMAC Executive (Pro or non-Pro) is required to communicate to the PMAC and to download

programs/settings to PMAC. In addition, program files may be edited with the PMAC Executive Editor

or with editors available from others.

Quick Start

The simplest way to illustrate how to use the I/O in a real application is to present the following example.

A few points to remember are:

1. Map the I/O points to PMAC M-Variables.

2. Use a PMAC PLC to read in the inputs, process them and write the outputs.

3. Do not read from ACC-77 more often than necessary.

4. Keep an image of the inputs.

5. Use the images in the programs.

6. Check the Parity Error bit on each read of the inputs.

Usually, ACC-77 I/O is treated the same way that a traditional PLC treats its I/O:

 The inputs are read at the beginning of a PLC software scan.

 The processing of the variables is done working with the internal image words (The logic is solved

based on the current input image).

Accessory 77 User Manual – Preliminary Documentation

12 Processing ACC-77 Inputs

Note:

The following examples are applicable to all PMACs. The specific memory

locations used are fine for all PMACs including PMAC PC, PMAC VME,

PMACLite, PMAC Universal Lite, and MiniPMAC. If using a PMAC2 or a Turbo

PMAC, consult the PMAC Manual for available memory locations.

In a typical PMAC application, PLCs are used as follows:

 PLC1 is used as a power-up PLC (runs once at power up)

 PLC2 can be used to read all the inputs.

 PLC3 thru 30 as required are used to process the inputs and perform other functions as required.

 PLC31 could be used to write the outputs.

Depending on the nature of the application, this approach may or may not be acceptable. An alternative

approach is to use PLCC1 to read the inputs, process them and write the outputs. Internal variables can

be used to communicate to and from other PLCs. The compiled PLC (PLCC1) will run in between the

other PLCs. thus updating the I/O more often than the previous method.

Map the I/O Points to PMAC M-Variables

Review the On-Line Command section of the PMAC Software Reference manual as a supplement to this

section.

Things to Know:

 ACC-77 works just like ACC-34C, except that it supports inputs only.

 TWS addresses should be setup as read only.

 Do not write to a read only variable.

 Only read the hardware when necessary.

 The individual bits of a TWS device like ACC-77 cannot be written to individually. Only 32-bit

words can be accessed.

Accessory 77 User Manual – Preliminary Documentation

ACC-77 Setup 13

ACC-77 SETUP

For the purpose of ACC-77 setup, the following example will demonstrate how to utilize all 64 inputs of

an ACC-77. The following three variables will be used during the ACC-77 I/O procedure:

Actual Word Variable

Variable which is read or written to by ACC-77 and PMAC

Image Word Variable

Variable assigned set equal to (Image) actual word variable

Image Bit Variable

Single bit of image word variable

Image Word Variables

It is best to use fixed-point M-Variables as the internal image variables for the I/O words. When this is

done, a single M-Variable representing the entire I/O word can be used for the copying operation. Then

separate M-Variables can be used to access individual bits or segments of the image word. Use of these

smaller M-Variables allows PMAC’s efficient firmware to do the masking and logic necessary to pick out

portions of the I/O word, rather than slower user program code.

PMAC Location of Image Words

The internal images reside in PMAC’s memory as follows:

Open Memory — Standard PMAC

For a standard PMAC with no DPRAM on board, the image word will be in an otherwise unused double

are set to zero automatically on power-up. There are 16 more open registers at PMAC addresses $07F0 to

$07FF, whose values are held when power is off. It is possible to use the registers of otherwise unused P

and Q-Variables for this purpose.

Access these registers with fixed-point M-Variables, not floating-point P or Q-Variables. A double fixed-

point register in PMAC’s internal memory is defined by the D format of M-Variable (e.g. M61-

>D:$07F0). This is a 48-bit register (only the low 32 bits will be used). The low 24 bits of the I/O will

be in the Y-memory, and the high eight bits of the I/O will be in the low eight bits of X-memory.

DPRAM — Standard PMAC

If the system has dual-ported RAM, use a 32-bit register in DPRAM. This way, the host computer always

has immediate access to the I/O. In fact, PMAC can be used just as a pass-through between the host

computer and the ACC-77 boards, letting the host computer do all the processing. A 32-bit fixed-point

variable occupies the low 16 bits (bits 0 to 15) of PMAC Y-memory, and the low 16 bits of PMAC X-

memory at the same address, with the less significant bits in Y-memory. It appears to the host computer

as two 16-bit registers at consecutive even addresses, with the less significant bits at the lower address.

Accessory 77 User Manual – Preliminary Documentation

14 ACC-77 Setup

Turbo PMAC Location of Image Words

Open Memory Turbo PMAC

For a Turbo PMAC with no DPRAM on board, the image word will be in an unused double register in

Turbo PMAC’s own memory. There are 16 open registers at Turbo PMAC addresses $0010F0 to

$0010FF that are set to zero automatically on power-up. Also, use the registers of otherwise unused P

and Q-Variables for this purpose.

Access these registers with fixed-point M-Variables, not floating-point P or Q-Variables. A double fixed-

point register in PMAC’s internal memory is defined by the D format of M-Variable (e.g., M80-

>D:$0010F0). This is a 48-bit register (only the low 32 bits will be used). The low 24 bits of the I/O will

be in the Y-memory, and the high eight bits of the I/O will be in the low eight bits of X-memory.

When using the ACC-77 I/O with fixed-point image variables, the only software overhead is the actual

copying between image and I/O. Including program interpretation time, this amounts to approximately

100 microseconds per 32-bit word. Aside from this, working with the I/O through the image words is at

least as fast as direct (parallel) PMAC I/O. There is a potential latency of a full PLC scan on the actual

I/O which must be respected. Many systems will have a few critical I/O points that cannot tolerate this

latency; typically, these use PMAC’s JOPTO port or ACC-14 I/O for these time-critical points, then use

ACC-77 for I/O that do not need to be so fast.

DPRAM Standard Turbo PMAC

If the system has dual-ported RAM (Option 2 is required), use a 32-bit register in DPRAM. This way, the

host computer always has immediate access to the I/O. In fact, PMAC can be used just as a pass-through

between the host computer and the ACC-77 boards, letting the host computer do all the processing. A 32-

bit fixed-point register in DPRAM is defined by the DP format of M-Variable (e.g. M80-> DP:$060000).

This type of variable occupies the low 16 bits (bits 0 to 15) of PMAC Y-memory and the low 16 bits of

PMAC X-memory at the same address, with the less significant bits in Y-memory. It appears to the host

computer as two 16-bit registers at consecutive even addresses, with the less significant bits at the lower

address.

The following example illustrates the method of working with ACC-77 I/O. It describes the procedure

for memory allocation, for the inputs (Image Word Variables) that will work with either dual-ported

RAM or PMAC memory locations.

Example: This example shows the image variables both in DPRAM and several places in internal

memory. In a real application, a single location range probably would be chosen.

Set-up and Definitions

Actual ACC-77 Input Words

M1000->TWS:1

First side of first ACC-77 board; an input here

Location is at port address 0; added 1 for read only

M1002->TWS:3

Second side of first ACC-77 board; an input here

Location is at secondary port address 0; added 3 for read

only

M1004->TWS:9

First side of second ACC-77 board; an input here

Location is at port address 8; added 1 for read only

M1006->TWS:11

Second side of second ACC-77 board; an input here

Location is at secondary port address 8; added 3 for read

only

Accessory 77 User Manual – Preliminary Documentation

ACC-77 Setup 15

Image Words

PMAC

Turbo PMAC

Comments

M1001->DP:$D800

M1001->DP:$060800

32-bit fixed-point DPRAM register

M1003->D:$0770

M1003->D:$0010F0

48-bit fixed-point register, set to zero on

power-up

M1005->D:$07F0

* Power-down hold

registers are not available

in Turbo PMAC

M1005->D:$0061F0

PMAC: 48-bit fixed-point register, value held

through power-down

Turbo PMAC: use this register for P-variable,

treated as 48-bit fixed point value

M1007->D:$13FF

M1007->D:$0063FF

value

* User Buffer Storage Space is same for the battery-backed Turbo PMAC.

Individual Pieces of Image Words

PMAC Memory Locations

Set up two M-Variables to contain the image of the I/O rack inputs (all 64 bits) and an M-Variable for

each bit. Typically, each bit of input is treated as a single bit, although other groupings make sense (e.g.,

four inputs treated as a binary value). Usually, the addresses D:$0770 and D:$0771 are available for use.

Check the application to make sure this memory location is available.

Port A Setup: Read Only

PMAC

Turbo PMAC

Comments

M1000->TWS:1

Port A (AIO 0-31)

M1001->D:$770

M1003->D:$0010F0

Image word for PLCs

M800->Y:$770,0

M800->Y:$0010F0,0

Bit0 (LSB)

M801->Y:$770,1

M801->Y:$0010F0,1

Bit1

M802->Y:$770,2

M802->Y:$0010F0,2

Bit2

M822->Y:$770,22

M822->Y:$0010F0,22

Bit22

M823->Y:$770,23

M823->Y:$0010F0,23

Bit23

M824->X:$770,0

M824->X:$0010F0,0

Bit24

M825->X:$770,1

M825->X:$0010F0,1

Bit25

M830->X:$770,6

M830->X:$0010F0,6

Bit30

M831->X:$770,7

M831->X:$0010F0,7

Bit31 (MSB)

Secondary Port Setup: Read Only

PMAC

Turbo PMAC

Comments

M1002->TWS:3

Port (IO 32-63)

M1003->D:$771

M1003->D:$0010F1

Image word for PLCs

M900->Y:$771,0

M900->Y:$0010F1,0

Bit00(LSB)

M901->Y:$771,1

M901->Y:$0010F1,1

Bit01

M902->Y:$771,2

M902->Y:$0010F1,2

Bit02

M922->Y:$771,22

M922->Y:$0010F1,22

Bit22

M923->Y:$771,23

M923->Y:$0010F1,23

Bit23

M924->X:$771,0

M924->X:$0010F1,0

Bit24

M925->X:$771,1

M925->X:$0010F1,1

Bit25

M930->X:$771,6

M930->X:$0010F1,6

Bit30

M931->X:$771,7

M931->X:$0010F1,7

Bit31 (MSB)

Accessory 77 User Manual – Preliminary Documentation

16 ACC-77 Setup

PMAC Dual-Ported RAM Locations

Port A Setup: Read Only

PMAC

Turbo PMAC

Comments

M1000->TWS:1

Port A (AIO 0-31)

M1001->DP:$D800

M1001->DP:$060800

Image word for PLCs

M800->Y:$D800,0

M800->Y:$060800,0

Bit0 (LSB)

M801->Y:$D800,1

M801->Y:$060800,1

Bit1

M802->Y:$D800,2

M802->Y:$060800,2

Bit2

M814->Y:$D800,14

M814->Y:$060800,14

Bit14

M815->Y:$D800,15

M815->Y:$060800,15

Bit15

M816->X:$D800,0

M816->X:$060800,0

Bit16

M817->X:$D800,1

M817->X:$060800,1

Bit17

M830->X:$D800,14

M830->X:$060800,14

Bit30

M831->X:$D800,15

M831->X:$060800,15

Bit31 (MSB)

Secondary Port Setup: Read Only

PMAC

Turbo PMAC

Comments

M1002->TWS:3

Port (IO 32-63)

M1003->DP:$D801

M1003->DP:$060801

Image word for PLCs

M900->Y:$D801,0

M900->Y:$060801,0

Bit0 (LSB)

M901->Y:$D801,1

M901->Y:$060801,1

Bit1

M902->Y:$D801,2

M902->Y:$060801,2

Bit2

M914->Y:$D801,14

M914->Y:$060801,14

Bit14

M915->Y:$D801,15

M915->Y:$060801,15

Bit15

M916->X:$D801,0

M916->X:$060801,0

Bit16

M917->X:$D801,1

M917->X:$060801,1

Bit17

M930->X:$D801,14

M930->X:$060801,14

Bit30

M931->X:$D801,15

M931->X:$060801,15

Bit31 (MSB)

Note:

The TWS:1 and TWS:3 addresses correspond to a ACC-77 with all the DIP

switches in the ON position. Refer to the table earlier in this manual for the

allowable address and corresponding switch settings.

Parity Error Bit

Set up an M-Variable to represent the TWS parity error bit in PMAC’s global status word.

M983->X:$0003,6 ; Parity Error Bit

Update the Inputs Using a PLCC

The simple compiled PLC listed below will update the input image and write the input image every time

it runs. The M-Variables mapped previously to individual bits can be used by other PMAC programs to

turn inputs on or off and to test inputs as required.

M1004->D:$0772 ; ACC-77 image word

M1005->D:$0773 ; ACC-77 image word

OPEN PLCC1 CLEAR

M1004=M1000 ; Get the first 32 inputs

IF(M983=0) ; Update the inputs if no parity error

M833=M1002 ; Save the Value at M833

ENDIF

M1005=m1002 ; Get the next 32 inputs

IF(M983=0) ; Update the inputs if no parity error

M933=M1005 ; Save the Value at M933

ENDIF

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Delta Tau Acc-77 Owner's manual

Delta Tau Acc-77 Owner's manual

Delta Tau Acc-77 Owner's manual

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