NXP MC92501 User guide

Brand: NXP

Model: MC92501

Type: User guide

NXP MC92501 is an ATM Cell Processor designed for use in Broadband Integrated Services Digital Network (B-ISDN) applications. It offers a range of capabilities, including cell processing, traffic management, and OAM functions. The device's key features include support for various ATM cell formats, traffic shaping and policing, and comprehensive OAM capabilities for fault detection and performance monitoring. With its advanced capabilities, the NXP MC92501 is suitable for use in high-speed ATM networks, providing efficient and reliable data transfer.

MOTOROLA MC92501 User’s Manual 7-11

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This read-only register contains the cell time of the most recent non-maintenance cycle.

This value may be used to find the most recent entries in the Dump Vector Table, which

is updated in a cyclical fashion.

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This read-only register contains the ATMC CFB Revision Number.

•ATMC CFB Major Revision (AMRV)—This field indicates the ATMC CFB Major

Revision Number.

•ATMC CFB Sub-Revision (ASRV)—This field indicates the ATMC CFB Sub-

Revision Number.

The following values of AMRV and ASRV are currently defined:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LCPT (MSB)

1514131211109876543210

LCPT (LSB)

Figure 7-6. Last Cell Processing Time Register (LCPTR) Fields

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0000000000000000

1514131211109876543210

0000 AMRV ASRV

Figure 7-7. ATMC CFB Revision Register (ARR) Fields

Table 7-2. Values of ATMC CFB Revision Fields

AMRV ASRV ATMC CFB Revision

000000 000000 Revision A0

000001 000000 Revision B0

000001 000001 Revision A

MC92501AD/D

(Motorola Order Number)

9/1999

REV. 0.1

This document contains information on a new product under development by Motorola. Motorola reserves the right to change or

discontinue this product without notice.

Addendum

MC92501 ATM Cell Processor User’s Manual

This technical update provides additional changes supported by the latest silicon revision

(MC92501GCA, Revision A) and clarifies some previously published information. The four

pages that are attached to this addendum (pages 4-29, 7-11, 9-12, and G-1) are

replacement pages that may be removed and placed in the MC92501 User’s Manual:

• Page 4-29, Figure 4-29: The MSEL

signal has been extended for one MCLK period

to indicate a one-wait state access, and a note has been added after the figure

indicating the wait state requirement.

• Page 7-11, Table 7-2: Revision A was added to the table.

• Page 9-12, Table 9-4: The following changes were made:

—I

Input leakage values:

–with pullup resistor—minimum changed from –50 to –720

–with pulldown resistor—maximum changed from 50 to 720

—I

minimum values for EACEN, EMWR, EMADDx, EMBSHx, and

EMBSLx

were changed from 24 mA to 20mA.

—Input Capacitance was changed from 8 pF to 10pF

• Page G-1: Old reference 15 was deleted.

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or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do

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MC92501AD/D

MOTOROLA MC92501 User’s Manual 4-29

Figure 4-42 shows a maintenance read/clear access. The write of zero to the External

Memory extends for three MCLK phases. The entire read/clear sequence requires four

MCLK cycles, which is the minimum length of the read access on the Microprocessor

Interface. Thus, the clear does not extend the read access from the system point of view.

NOTE: When performing a read/clear maintenance access, at least

one wait state is required for proper operation even if the

duration of an MCLK phase is longer than T

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Normal (non-maintenance) accesses to the External Address Compression (EAC) Device

have the same timing as normal External Memory accesses, except that EACEN is

asserted instead of the EM bank select signals. The MC92501 always drives EMADD

with all 1s when accessing the EAC Device. Maintenance accesses to the EAC Device

have the same timing as External Memory maintenance accesses, except that the EACEN

signal is asserted instead of the EM bank select signals. The value provided on MADD is

driven on EMADD, so 24 bits (16 MB) of External Address Compression Device address

space are available to the microprocessor. Figure 4-43 shows a possible implementation

of the EAC circuitry. Note that the MC92501 sees the EAC as one write register and one

read register. The microprocessor is free to use the same data path with other addresses

to control and/or program the address compression device during maintenance slots.

Figure 4-42. External Memory Maintenance Read/Clear Access

Figure 4-43. Example Implementation of External Address Compression

MCLK

EMDATA

EMWR

address

EMADD

RAM access time

EMBSH/L

RAM data zero

MSEL

mP data

External Address Compression Circuit

Address

Compression

Device

(e.g. CAM)

Wr_Reg

Rd_Reg

EAC_Wr

ADD = 11...11

EAC_Rd

ADD = 11...11

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MOTOROLA MC92501 User’s Manual G-1

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1.ANSI Recommendation I.361, “B-ISDN ATM Layer Specification”, November

1995

2.ITU-T Recommendation I.610, “B-ISDN Operation and Maintenance Principles

and Functions”, November, 1995

3.ATM Forum, “ATM User-Network Interface Specification”, Version 3.1,

September, 1994

4.ATM Forum, “BISDN Inter Carrier Interface (B-ICI) Specification”, Version 1.1,

September, 1994

5.ATM Forum, “BISDN Inter Carrier Interface (B-ICI) Specification”, Version 2.0

Letter Ballot, November, 1995

6.ATM Forum, “Traffic Management Specification”, Version 4.0, April, 1996.

7.ANSI T1S1.5/93-004R2, “Broadband ISDN - Operations and Maintenance

Principles and Functions”, January, 1994

8.Bellcore TA-NWT-01110, “Broadband ISDN Switching Systems Generic

requirements”, Issue 1, August, 1992

9.Bellcore GR-1113-CORE, “Asynchronous Transfer Mode (ATM) and ATM

Adaptation Layer (AAL) Protocols”, Issue 1, July, 1994

10.Bellcore GR-1248-CORE, “Generic Requirements for Operations of ATM Network

Elements”, Issue 1, August, 1994

11.Motorola, “MC68360 Quad Integrated Communications Controller User’s

Manual”, 1993

12.“UTOPIA, An ATM-PHY Interface Specification, Level 1, Version 2.01”, March 21,

1994.

13.“UTOPIA Level 2 Specification, Version 1.0”, June, 1995

14.Bellcore TA-TSV-001408, “Generic Requirements for Exchange PVC Cell Relay

Service”, Issue 1, August, 1993

15.P. Bardell, W. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom

Techniques, John Wiley & Sons, 1987.

9-12 MC92501 User’s Manual MOTOROLA

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Table 9-4. DC Electrical Characteristics

Symbol Parameter Condition Min. Max. Unit

TTL Inputs (5V Tolerant) —2.25.5V

TTL Inputs (5V Tolerant) — –0.3 0.8 V

Input Leakage Current,

No Pull Resistor

= V

or V

–5 5 µA

With Pullup Resistor * –720 –5

With Pulldown Resistor * 5 720

Output High Current,

LVTTL Output Type

Outputs:

EACEN, EMWR, EMADDx,

EMBSHx, EMBSLx

= Min,

Min = 0.8 V

–20 — mA

Output High Current,

LVTTL Output Type

Outputs:

All other outputs

–4 —

Output Low Current,

LVTTL Output Type

Outputs:

EACEN, EMWR, EMADDx,

EMBSHx, EMBSLx

= Min,

Max = 0.4 V

20 — mA

Output Low Current,

LVTTL Output Type

Outputs:

All other outputs

4—

Output Leakage Current,

Tri-State Output

Output = High Imped-

ance

OUT

= V

or V

–10 10 µA

DDQ

Max Quiescent Supply

Current

OUT

= 0 mA

= V

or V

10 µA

Max Dynamic Supply

Current

Nominal Load

Capacitance,

ACLK = 25.6 Mhz,

MCLK = 33 Mhz

300

Input Capacitance (TTL) —

—

10 pF

Notes:1.Under Typical Loca, 25 Mhz ACLK/MCLK

= –40°C to 85°C, V

=3.3 V ±0.3 V Guaranteed

3.Inputs may be modified to include pullup resistors at any time.

4.See Section 9.2 Signal Description for pin input/output type.

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NXP MC92501 User guide

NXP MC92501 User guide

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