NXP K51_100 Reference guide

K51 Sub-Family Reference Manual

Supports: MK51DN256ZCLQ10, MK51DN256ZCMD10,

MK51DN512ZCLQ10, MK51DN512ZCMD10

Document Number: K51P144M100SF2RM

Rev. 6, Nov 2011

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Contents

Section Number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................55

1.1.1 Purpose.........................................................................................................................................................55

1.1.2 Audience......................................................................................................................................................55

1.2 Conventions..................................................................................................................................................................55

1.2.1 Numbering systems......................................................................................................................................55

1.2.2 Typographic notation...................................................................................................................................56

1.2.3 Special terms................................................................................................................................................56

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................57

2.2 K50 Family Introduction...............................................................................................................................................57

2.3 Module Functional Categories......................................................................................................................................57

2.3.1 ARM Cortex-M4 Core Modules..................................................................................................................58

2.3.2 System Modules...........................................................................................................................................59

2.3.3 Memories and Memory Interfaces...............................................................................................................60

2.3.4 Clocks...........................................................................................................................................................61

2.3.5 Security and Integrity modules....................................................................................................................61

2.3.6 Analog modules...........................................................................................................................................61

2.3.7 Timer modules.............................................................................................................................................62

2.3.8 Communication interfaces...........................................................................................................................63

2.3.9 Human-machine interfaces..........................................................................................................................64

2.4 Orderable part numbers.................................................................................................................................................64

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................67

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3.2 Core modules................................................................................................................................................................67

3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................67

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................70

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................76

3.2.4 JTAG Controller Configuration...................................................................................................................77

3.3 System modules............................................................................................................................................................78

3.3.1 SIM Configuration.......................................................................................................................................78

3.3.2 Mode Controller Configuration...................................................................................................................79

3.3.3 PMC Configuration......................................................................................................................................79

3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................80

3.3.5 MCM Configuration....................................................................................................................................82

3.3.6 Crossbar Switch Configuration....................................................................................................................82

3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................85

3.3.8 Peripheral Bridge Configuration..................................................................................................................87

3.3.9 DMA request multiplexer configuration......................................................................................................89

3.3.10 DMA Controller Configuration...................................................................................................................92

3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................93

3.3.12 Watchdog Configuration..............................................................................................................................94

3.4 Clock Modules..............................................................................................................................................................95

3.4.1 MCG Configuration.....................................................................................................................................95

3.4.2 OSC Configuration......................................................................................................................................96

3.4.3 RTC OSC configuration...............................................................................................................................97

3.5 Memories and Memory Interfaces................................................................................................................................97

3.5.1 Flash Memory Configuration.......................................................................................................................97

3.5.2 Flash Memory Controller Configuration.....................................................................................................100

3.5.3 SRAM Configuration...................................................................................................................................101

3.5.4 SRAM Controller Configuration.................................................................................................................105

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3.5.5 System Register File Configuration.............................................................................................................105

3.5.6 VBAT Register File Configuration..............................................................................................................106

3.5.7 EzPort Configuration...................................................................................................................................107

3.5.8 FlexBus Configuration.................................................................................................................................108

3.6 Security.........................................................................................................................................................................111

3.6.1 CRC Configuration......................................................................................................................................111

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3.7 Analog...........................................................................................................................................................................112

3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................112

3.7.2 CMP Configuration......................................................................................................................................119

3.7.3 12-bit DAC Configuration...........................................................................................................................121

3.7.4 Op-amp Configuration.................................................................................................................................122

3.7.5 TRIAMP Configuration...............................................................................................................................124

3.7.6 VREF Configuration....................................................................................................................................125

3.8 Timers...........................................................................................................................................................................126

3.8.1 PDB Configuration......................................................................................................................................126

3.8.2 FlexTimer Configuration.............................................................................................................................130

3.8.3 PIT Configuration........................................................................................................................................133

3.8.4 Low-power timer configuration...................................................................................................................134

3.8.5 CMT Configuration......................................................................................................................................136

3.8.6 RTC configuration.......................................................................................................................................137

3.9 Communication interfaces............................................................................................................................................138

3.9.1 Universal Serial Bus (USB) Subsystem.......................................................................................................138

3.9.2 SPI configuration.........................................................................................................................................143

3.9.3 I2C Configuration........................................................................................................................................146

3.9.4 UART Configuration...................................................................................................................................147

3.9.5 SDHC Configuration....................................................................................................................................149

3.9.6 I2S configuration..........................................................................................................................................150

3.10 Human-machine interfaces (HMI)................................................................................................................................152

3.10.1 GPIO configuration......................................................................................................................................152

3.10.2 TSI Configuration........................................................................................................................................153

3.10.3 Segment LCD Configuration.......................................................................................................................156

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................159

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4.2 System memory map.....................................................................................................................................................159

4.2.1 Aliased bit-band regions..............................................................................................................................160

4.3 Flash Memory Map.......................................................................................................................................................161

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................162

4.4 SRAM memory map.....................................................................................................................................................162

4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................162

4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................163

4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................167

4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................171

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................173

5.2 Programming model......................................................................................................................................................173

5.3 High-Level device clocking diagram............................................................................................................................173

5.4 Clock definitions...........................................................................................................................................................174

5.4.1 Device clock summary.................................................................................................................................175

5.5 Internal clocking requirements.....................................................................................................................................177

5.5.1 Clock divider values after reset....................................................................................................................178

5.5.2 VLPR mode clocking...................................................................................................................................178

5.6 Clock Gating.................................................................................................................................................................178

5.7 Module clocks...............................................................................................................................................................179

5.7.1 PMC 1-kHz LPO clock................................................................................................................................180

5.7.2 WDOG clocking..........................................................................................................................................181

5.7.3 Debug trace clock.........................................................................................................................................181

5.7.4 PORT digital filter clocking.........................................................................................................................182

5.7.5 LPTMR clocking..........................................................................................................................................182

5.7.6 USB FS OTG Controller clocking...............................................................................................................183

5.7.7 UART clocking............................................................................................................................................183

5.7.8 SDHC clocking............................................................................................................................................183

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5.7.9 I2S clocking.................................................................................................................................................184

5.7.10 TSI clocking.................................................................................................................................................184

Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................187

6.2 Reset..............................................................................................................................................................................187

6.2.1 Power-on reset (POR)..................................................................................................................................188

6.2.2 System resets................................................................................................................................................188

6.2.3 Debug resets.................................................................................................................................................191

6.3 Boot...............................................................................................................................................................................193

6.3.1 Boot sources.................................................................................................................................................193

6.3.2 Boot options.................................................................................................................................................193

6.3.3 FOPT boot options.......................................................................................................................................193

6.3.4 Boot sequence..............................................................................................................................................194

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................197

7.2 Power modes.................................................................................................................................................................197

7.3 Entering and exiting power modes...............................................................................................................................199

7.4 Power mode transitions.................................................................................................................................................200

7.5 Power modes shutdown sequencing.............................................................................................................................201

7.6 Module Operation in Low Power Modes......................................................................................................................201

7.7 Clock Gating.................................................................................................................................................................204

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................205

8.2 Flash Security...............................................................................................................................................................205

8.3 Security Interactions with other Modules.....................................................................................................................206

8.3.1 Security interactions with FlexBus..............................................................................................................206

8.3.2 Security Interactions with EzPort................................................................................................................206

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8.3.3 Security Interactions with Debug.................................................................................................................206

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................209

9.1.1 References....................................................................................................................................................211

9.2 The Debug Port.............................................................................................................................................................211

9.2.1 JTAG-to-SWD change sequence.................................................................................................................212

9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................212

9.3 Debug Port Pin Descriptions.........................................................................................................................................213

9.4 System TAP connection................................................................................................................................................213

9.4.1 IR Codes.......................................................................................................................................................213

9.5 JTAG status and control registers.................................................................................................................................214

9.5.1 MDM-AP Control Register..........................................................................................................................215

9.5.2 MDM-AP Status Register............................................................................................................................217

9.6 Debug Resets................................................................................................................................................................218

9.7 AHB-AP........................................................................................................................................................................219

9.8 ITM...............................................................................................................................................................................220

9.9 Core Trace Connectivity...............................................................................................................................................220

9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................220

9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................221

9.11.1 Performance Profiling with the ETB...........................................................................................................221

9.11.2 ETB Counter Control...................................................................................................................................222

9.12 TPIU..............................................................................................................................................................................222

9.13 DWT.............................................................................................................................................................................222

9.14 Debug in Low Power Modes........................................................................................................................................223

9.14.1 Debug Module State in Low Power Modes.................................................................................................224

9.15 Debug & Security.........................................................................................................................................................224

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Chapter 10

Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................225

10.2 Signal Multiplexing Integration....................................................................................................................................225

10.2.1 Port control and interrupt module features..................................................................................................226

10.2.2 Clock gating.................................................................................................................................................226

10.2.3 Signal multiplexing constraints....................................................................................................................226

10.3 Pinout............................................................................................................................................................................227

10.3.1 K51 Signal Multiplexing and Pin Assignments...........................................................................................227

10.3.2 K51 Pinouts..................................................................................................................................................233

10.4 Module Signal Description Tables................................................................................................................................235

10.4.1 Core Modules...............................................................................................................................................235

10.4.2 System Modules...........................................................................................................................................236

10.4.3 Clock Modules.............................................................................................................................................237

10.4.4 Memories and Memory Interfaces...............................................................................................................237

10.4.5 Analog..........................................................................................................................................................238

10.4.6 Communication Interfaces...........................................................................................................................240

10.4.7 Human-Machine Interfaces (HMI)..............................................................................................................244

Chapter 11

Port control and interrupts (PORT)

11.1 Introduction...................................................................................................................................................................247

11.1.1 Overview......................................................................................................................................................247

11.1.2 Features........................................................................................................................................................247

11.1.3 Modes of operation......................................................................................................................................248

11.2 External signal description............................................................................................................................................249

11.3 Detailed signal descriptions..........................................................................................................................................249

11.4 Memory map and register definition.............................................................................................................................249

11.4.1 Pin Control Register n (PORTx_PCRn).......................................................................................................256

11.4.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................258

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11.4.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................259

11.4.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................259

11.4.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................260

11.4.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................261

11.4.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................261

11.5 Functional description...................................................................................................................................................262

11.5.1 Pin control....................................................................................................................................................262

11.5.2 Global pin control........................................................................................................................................262

11.5.3 External interrupts........................................................................................................................................263

11.5.4 Digital filter..................................................................................................................................................264

Chapter 12

System integration module (SIM)

12.1 Introduction...................................................................................................................................................................265

12.1.1 Features........................................................................................................................................................265

12.1.2 Modes of operation......................................................................................................................................265

12.1.3 SIM Signal Descriptions..............................................................................................................................266

12.2 Memory map and register definition.............................................................................................................................266

12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................268

12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................270

12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................272

12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................275

12.2.5 System Options Register 6 (SIM_SOPT6)..................................................................................................276

12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................277

12.2.7 System Device Identification Register (SIM_SDID)...................................................................................279

12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................280

12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................281

12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................282

12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................283

12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................286

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12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................288

12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................290

12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................291

12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................294

12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................295

12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................296

12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................297

12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................298

12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................298

12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................299

12.3 Functional description...................................................................................................................................................299

Chapter 13

Mode Controller

13.1 Introduction...................................................................................................................................................................301

13.1.1 Features........................................................................................................................................................301

13.1.2 Modes of Operation.....................................................................................................................................301

13.1.3 MCU Reset...................................................................................................................................................312

13.2 Mode Control Memory Map/Register Definition.........................................................................................................315

13.2.1 System Reset Status Register High (MC_SRSH)........................................................................................316

13.2.2 System Reset Status Register Low (MC_SRSL).........................................................................................317

13.2.3 Power Mode Protection Register (MC_PMPROT).....................................................................................318

13.2.4 Power Mode Control Register (MC_PMCTRL)..........................................................................................320

Chapter 14

Power Management Controller

14.1 Introduction...................................................................................................................................................................323

14.2 Features.........................................................................................................................................................................323

14.3 Low-Voltage Detect (LVD) System.............................................................................................................................323

14.3.1 LVD Reset Operation...................................................................................................................................324

14.3.2 LVD Interrupt Operation.............................................................................................................................324

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14.3.3 Low-Voltage Warning (LVW) Interrupt Operation.....................................................................................324

14.4 PMC Memory Map/Register Definition.......................................................................................................................325

14.4.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)........................................................325

14.4.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)........................................................326

14.4.3 Regulator Status and Control Register (PMC_REGSC)..............................................................................328

Chapter 15

Low-leakage wake-up unit (LLWU)

15.1 Introduction...................................................................................................................................................................329

15.1.1 Features........................................................................................................................................................330

15.1.2 Modes of operation......................................................................................................................................330

15.1.3 Block diagram..............................................................................................................................................331

15.2 LLWU Signal Descriptions...........................................................................................................................................332

15.3 Memory map/register definition...................................................................................................................................333

15.3.1 LLWU Pin Enable 1 Register (LLWU_PE1)..............................................................................................333

15.3.2 LLWU Pin Enable 2 Register (LLWU_PE2)..............................................................................................334

15.3.3 LLWU Pin Enable 3 Register (LLWU_PE3)..............................................................................................336

15.3.4 LLWU Pin Enable 4 Register (LLWU_PE4)..............................................................................................337

15.3.5 LLWU Module Enable Register (LLWU_ME)...........................................................................................338

15.3.6 LLWU Flag 1 Register (LLWU_F1)...........................................................................................................339

15.3.7 LLWU Flag 2 Register (LLWU_F2)...........................................................................................................341

15.3.8 LLWU Flag 3 Register (LLWU_F3)...........................................................................................................343

15.3.9 LLWU Control and Status Register (LLWU_CS).......................................................................................344

15.4 Functional description...................................................................................................................................................345

15.4.1 LLS mode.....................................................................................................................................................346

15.4.2 VLLS modes................................................................................................................................................346

15.4.3 Initialization.................................................................................................................................................347

15.4.4 Low power mode recovery..........................................................................................................................347

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Chapter 16

Miscellaneous Control Module (MCM)

16.1 Introduction...................................................................................................................................................................349

16.1.1 Features........................................................................................................................................................349

16.2 Memory Map/Register Descriptions.............................................................................................................................349

16.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)..................................................................350

16.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)..............................................................350

16.2.3 SRAM arbitration and protection (MCM_SRAMAP).................................................................................351

16.2.4 Interrupt status register (MCM_ISR)...........................................................................................................352

16.2.5 ETB counter control register (MCM_ETBCC)...........................................................................................353

16.2.6 ETB reload register (MCM_ETBRL)..........................................................................................................354

16.2.7 ETB counter value register (MCM_ETBCNT)...........................................................................................355

16.3 Functional Description..................................................................................................................................................355

16.3.1 Interrupts......................................................................................................................................................355

Chapter 17

Crossbar Switch (AXBS)

17.1 Introduction...................................................................................................................................................................357

17.1.1 Features........................................................................................................................................................357

17.2 Memory Map / Register Definition...............................................................................................................................358

17.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................359

17.2.2 Control Register (AXBS_CRSn).................................................................................................................362

17.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................364

17.3 Functional Description..................................................................................................................................................365

17.3.1 General operation.........................................................................................................................................365

17.3.2 Register coherency.......................................................................................................................................366

17.3.3 Arbitration....................................................................................................................................................366

17.4 Initialization/application information...........................................................................................................................369

Chapter 18

Memory Protection Unit (MPU)

18.1 Introduction...................................................................................................................................................................371

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18.2 Overview.......................................................................................................................................................................371

18.2.1 Block Diagram.............................................................................................................................................371

18.2.2 Features........................................................................................................................................................372

18.3 Memory Map/Register Definition.................................................................................................................................373

18.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................376

18.3.2 Error Address Register, Slave Port n (MPU_EARn)...................................................................................378

18.3.3 Error Detail Register, Slave Port n (MPU_EDRn)......................................................................................379

18.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................380

18.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................381

18.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................381

18.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................384

18.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................385

18.4 Functional Description..................................................................................................................................................387

18.4.1 Access Evaluation Macro.............................................................................................................................387

18.4.2 Putting It All Together and Error Terminations...........................................................................................388

18.4.3 Power Management......................................................................................................................................389

18.5 Initialization Information..............................................................................................................................................389

18.6 Application Information................................................................................................................................................389

Chapter 19

Peripheral Bridge (AIPS-Lite)

19.1 Introduction...................................................................................................................................................................393

19.1.1 Features........................................................................................................................................................393

19.1.2 General operation.........................................................................................................................................393

19.2 Memory map/register definition...................................................................................................................................394

19.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................395

19.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................399

19.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................404

19.3 Functional Description..................................................................................................................................................409

19.3.1 Access support.............................................................................................................................................409

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Chapter 20

Direct memory access multiplexer (DMAMUX)

20.1 Introduction...................................................................................................................................................................411

20.1.1 Overview......................................................................................................................................................411

20.1.2 Features........................................................................................................................................................412

20.1.3 Modes of operation......................................................................................................................................412

20.2 External signal description............................................................................................................................................413

20.3 Memory map/register definition...................................................................................................................................413

20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)...........................................................................414

20.4 Functional description...................................................................................................................................................415

20.4.1 DMA channels with periodic triggering capability......................................................................................415

20.4.2 DMA channels with no triggering capability...............................................................................................418

20.4.3 "Always enabled" DMA sources.................................................................................................................418

20.5 Initialization/application information...........................................................................................................................419

20.5.1 Reset.............................................................................................................................................................419

20.5.2 Enabling and configuring sources................................................................................................................419

Chapter 21

Direct Memory Access Controller (eDMA)

21.1 Introduction...................................................................................................................................................................423

21.1.1 Block diagram..............................................................................................................................................423

21.1.2 Block parts...................................................................................................................................................424

21.1.3 Features........................................................................................................................................................426

21.2 Modes of operation.......................................................................................................................................................427

21.3 Memory map/register definition...................................................................................................................................427

21.3.1 Control Register (DMA_CR).......................................................................................................................442

21.3.2 Error Status Register (DMA_ES)................................................................................................................444

21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................446

21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................448

21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................450

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21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................451

21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................452

21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................453

21.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................454

21.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................455

21.3.11 Clear Error Register (DMA_CERR)............................................................................................................456

21.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................457

21.3.13 Interrupt Request Register (DMA_INT)......................................................................................................457

21.3.14 Error Register (DMA_ERR)........................................................................................................................460

21.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................462

21.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................464

21.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................465

21.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................466

21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................466

21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................467

21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)

(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................468

21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)

(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................469

21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................470

21.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................470

21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................471

21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_CITER_ELINKYES)...........................................................................................................471

21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_CITER_ELINKNO)............................................................................................................472

21.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........473

21.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................474

21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_BITER_ELINKYES)...........................................................................................................476

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21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_BITER_ELINKNO)............................................................................................................477

21.4 Functional description...................................................................................................................................................478

21.4.1 eDMA basic data flow.................................................................................................................................478

21.4.2 Error reporting and handling........................................................................................................................481

21.4.3 Channel preemption.....................................................................................................................................483

21.4.4 Performance.................................................................................................................................................483

21.5 Initialization/application information...........................................................................................................................488

21.5.1 eDMA initialization.....................................................................................................................................488

21.5.2 Programming errors.....................................................................................................................................490

21.5.3 Arbitration mode considerations..................................................................................................................490

21.5.4 Performing DMA transfers..........................................................................................................................491

21.5.5 Monitoring transfer descriptor status...........................................................................................................495

21.5.6 Channel Linking...........................................................................................................................................496

21.5.7 Dynamic programming................................................................................................................................498

Chapter 22

External Watchdog Monitor (EWM)

22.1 Introduction...................................................................................................................................................................501

22.1.1 Features........................................................................................................................................................501

22.1.2 Modes of Operation.....................................................................................................................................502

22.1.3 Block Diagram.............................................................................................................................................503

22.2 EWM Signal Descriptions............................................................................................................................................504

22.3 Memory Map/Register Definition.................................................................................................................................504

22.3.1 Control Register (EWM_CTRL).................................................................................................................504

22.3.2 Service Register (EWM_SERV)..................................................................................................................505

22.3.3 Compare Low Register (EWM_CMPL)......................................................................................................506

22.3.4 Compare High Register (EWM_CMPH).....................................................................................................506

22.4 Functional Description..................................................................................................................................................507

22.4.1 The EWM_out Signal..................................................................................................................................507

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22.4.2 The EWM_in Signal....................................................................................................................................508

22.4.3 EWM Counter..............................................................................................................................................508

22.4.4 EWM Compare Registers............................................................................................................................508

22.4.5 EWM Refresh Mechanism...........................................................................................................................509

Chapter 23

Watchdog Timer (WDOG)

23.1 Introduction...................................................................................................................................................................511

23.2 Features.........................................................................................................................................................................511

23.3 Functional Overview.....................................................................................................................................................513

23.3.1 Unlocking and Updating the Watchdog.......................................................................................................514

23.3.2 The Watchdog Configuration Time (WCT).................................................................................................515

23.3.3 Refreshing the Watchdog.............................................................................................................................516

23.3.4 Windowed Mode of Operation....................................................................................................................516

23.3.5 Watchdog Disabled Mode of Operation......................................................................................................516

23.3.6 Low Power Modes of Operation..................................................................................................................517

23.3.7 Debug Modes of Operation..........................................................................................................................517

23.4 Testing the Watchdog...................................................................................................................................................518

23.4.1 Quick Test....................................................................................................................................................518

23.4.2 Byte Test......................................................................................................................................................518

23.5 Backup Reset Generator...............................................................................................................................................520

23.6 Generated Resets and Interrupts...................................................................................................................................520

23.7 Memory Map and Register Definition..........................................................................................................................521

23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................522

23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................524

23.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................524

23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................525

23.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................525

23.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................526

23.7.7 Watchdog Refresh Register (WDOG_REFRESH)......................................................................................526

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23.7.8 Watchdog Unlock Register (WDOG_UNLOCK).......................................................................................526

23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................527

23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................527

23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT).................................................................................528

23.7.12 Watchdog Prescaler Register (WDOG_PRESC).........................................................................................528

23.8 Watchdog Operation with 8-bit access.........................................................................................................................528

23.8.1 General Guideline........................................................................................................................................528

23.8.2 Refresh and Unlock operations with 8-bit access........................................................................................529

23.9 Restrictions on Watchdog Operation............................................................................................................................530

Chapter 24

Multipurpose Clock Generator (MCG)

24.1 Introduction...................................................................................................................................................................533

24.1.1 Features........................................................................................................................................................533

24.1.2 Modes of Operation.....................................................................................................................................536

24.2 External Signal Description..........................................................................................................................................537

24.3 Memory Map/Register Definition.................................................................................................................................537

24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................538

24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................539

24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................540

24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................541

24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................542

24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................544

24.3.7 MCG Status Register (MCG_S)..................................................................................................................545

24.3.8 MCG Auto Trim Control Register (MCG_ATC)........................................................................................547

24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................547

24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................548

24.4 Functional Description..................................................................................................................................................548

24.4.1 MCG Mode State Diagram..........................................................................................................................548

24.4.2 Low Power Bit Usage..................................................................................................................................553

K51 Sub-Family Reference Manual, Rev. 6, Nov 2011

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