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Circuit Description
(5) UHF Bands Reception (1000 MHz ~ 1300 MHz)
Received signals between 1000 and 1300 MHz pass through
the Triplexer circuit, low-pass filter/high-pass filter circuit,
UHF ANT switch circuit and protector diode D1082
(HVC131) before additional filtering by a band-pass filter
prior to application to RF amplifier Q1111 (MT3S36FS).
The amplified RF signal is pass through the band-pass fil-
ter, RF amplifier Q1112 (MT3S36FS) and band-pass filter
to first mixer Q1113 (MT3S36FS). Meanwhile, UHF out-
put from the VCO-UNIT is amplified by Q1056 (2SC5374)
and applied through diode ANT switch D1074 (1SS400G)
to mixer Q1113 (MT3S36FS) as the first local signal.
The 47.25 MHz intermediate frequency product of the mixer
is delivered to the IF circuit.
The TUNE voltage from the CPU is amplified by DC am-
plifier Q1025 (NJU7007F3) and applied to varactors D1083
and D1084 (all HVC3558) in the variable frequency band-
pass filters. By changing the electrostatic capacitance of the
varactors, optimum filter characteristics are provided for
each specific operating frequency.
(6) 47.25-MHz First Intermediate Frequency
The 47.25 MHz first intermediate frequency from first mix-
ers is delivered from the first mixer to IF circuit. On the
MAIN-UNIT, the IF for AM and FM-narrow signals is
passed through diode switch D1030 (DAP222M) and 47.25
MHz monolithic crystal filter (MCF) XF1001 to narrow IF
amplifier Q1030 (2SC4915) for input to IF IC Q1047
(NJM2552V) after amplitude limiting by D1033 (DA221M).
Meanwhile, a portion of the output of 11.7 MHz crystal
X1001 is multiplied fourfold by Q1035 and Q1037 (both
2SC4915) to provide the 46.8 MHz second local signal, ap-
plied to the Narrow IF IC. Within the IC, this signal is mixed
with the 47.25 MHz first intermediate frequency signal to
produce the 450 kHz second intermediate frequency.
This second IF is filtered by ceramic filter CF1002 and am-
plified by the limiting amplifier within the Narrow IF IC
before quadrate detection by ceramic discriminator
CD1001.
Demodulated audio is output from pin 11 of the Narrow
IF IC through narrow mute analog switch Q1068 (2SJ364).
The resulting audio is amplified by AF amplifier Q1005
(NJM2151AV), and output through EAR jack J1001 to in-
ternal speaker SP1001 or an external earphone.
PLL Frequency Synthesizer
PLL IC Q1041 (MB15A01PFV1) on the MAIN-UNIT con-
sists of a data shift register, reference frequency divider,
phase comparator, charge pump, intermittent operation
circuit, and band selector switch. Serial PLL data from the
CPU is converted into parallel data by the shift register in
the PLL IC and is latched into the comparative frequency
divider and reference frequency divider to set a frequency
dividing ratio for each. An 11.7 MHz reference signal pro-
duced by X1001 is input to REF pin 1 of the PLL IC. The
internal reference frequency divider divides the 11.7 MHz
reference by 2,050 (or 1,640) to obtain a reference frequen-
cy of 5 kHz (or 6.25 kHz), which is applied to the phase
comparator. Meanwhile, a sample of the output of VHF
VCO Q4004 or UHF VCO Q4002 on the VCO-UNIT, buff-
ered by Q4006, is input to the PLL IC, where it is frequen-
cy-divided by the internal comparative frequency divider
to produce a comparative frequency also applied to the
phase comparator. The phase comparator compares the
phase between the reference frequency and comparative
frequency to output a pulse corresponding to the phase
difference between them. This pulse is input to the charge
pump, and the output from the charge pump passes
through a loop filter composed of R1280, R1281, R1170 and
either C1185, C1187 and R1170, C1186, C1188 and C1189,
which convert the pulse into a corresponding smoothed
varactor control voltage (VCV). The VCV is applied to var-
actor D4007 (1SV325) in the MW ~ 76 MHz VCO tank
circuit, or to varactor D4001 (HVC355B) in the UHF VCO
tank circuit, to varactor D4004 and D4013 (both 1SV325)
in the VHF VCO tank circuit, or to varactor D4001
(HVC355B) in the UHF VCO tank circuit, or to varactor
D4021 (HVC355B) in the 1200MHz VCO tank circuit, to
eliminate phase difference between the reference frequen-
cy and comparative frequency, and so locking the VCO os-
cillation frequency to the reference crystal. The VCO fre-
quency is determined by the frequency-dividing ratio sent
from the CPU to the PLL IC. During receiver power save
operation, the PLL circuit operates intermittently to reduce
current consumption, for which the intermittent operation
control circuit reduces the lock-up time.