Freescale Semiconductor ColdFire MCF5213 Reference guide

MCF5213 ColdFire

®

Integrated

Microcontroller Reference Manual

Devices Supported:

MCF5211

MCF5212

MCF5213

Document Number: MCF5213RM

Rev. 3

03/2007

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Document Number: MCF5213RM

Rev. 3

03/2007

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Overview

Signal Descriptions

ColdFire Core

Multiply-Accumulate Unit (MAC)

Static RAM (SRAM)

Clock Module

Power Management

Chip Configuration Module (CCM)

Reset Controller Module

System Control Module (SCM)

General Purpose I/O Module

Interrupt Controller Module

Edge Port Module (EPORT)

DMA Controller Module

ColdFire Flash Module (CFM)

EzPort

Programmable Interrupt Timers (PIT0–PIT1)

General Purpose Timer Module (GPT)

DMA Timers (DTIM0–DTIM3)

Queued Serial Peripheral Interface (QSPI)

UART Modules

I

2

C Interface

Analog-to-Digital Converter (ADC)

Pulse-Width Modulation (PWM) Module

FlexCAN

Debug Module

IEEE 1149.1 Test Access Port (JTAG)

Register Memory Map Quick Reference

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Overview

Signal Descriptions

ColdFire Core

Multiply-Accumulate Unit (MAC)

Static RAM (SRAM)

Clock Module

Power Management

Chip Configuration Module (CCM)

Reset Controller Module

System Control Module (SCM)

General Purpose I/O Module

Interrupt Controller Module

Edge Port Module (EPORT)

DMA Controller Module

ColdFire Flash Module (CFM)

EzPort

Programmable Interrupt Timers (PIT0–PIT1)

General Purpose Timer Module (GPT)

DMA Timers (DTIM0–DTIM3)

Queued Serial Peripheral Interface (QSPI)

UART Modules

I

2

C Interface

Analog-to-Digital Converter (ADC)

Pulse-Width Modulation (PWM) Module

FlexCAN

Debug Module

IEEE 1149.1 Test Access Port (JTAG)

Register Memory Map Quick Reference

MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3

Freescale Semiconductor v

Contents

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Title

Page

Number

About This Book

Audience ...................................................................................................................... xxvii

Organization ................................................................................................................. xxvii

Conventions .................................................................................................................. xxix

Register Figure Conventions ......................................................................................xxx

Acronyms and Abbreviations ....................................................................................... xxxi

Terminology Conventions ............................................................................................ xxxii

Chapter 1

Overview

1.1 MCF5213 Family Configurations ................................................................................... 1-2

1.2 Block Diagram ................................................................................................................ 1-3

1.3 Part Numbers and Packaging .......................................................................................... 1-3

1.4 Features ........................................................................................................................... 1-4

1.4.1 V2 Core Overview ...................................................................................................... 1-8

1.4.2 Integrated Debug Module ........................................................................................... 1-9

1.4.3 JTAG ........................................................................................................................... 1-9

1.4.4 On-Chip Memories ...................................................................................................1-10

1.4.4.1 SRAM ................................................................................................................... 1-10

1.4.4.2 Flash Memory ....................................................................................................... 1-10

1.4.5 Power Management .................................................................................................. 1-10

1.4.6 FlexCAN ...................................................................................................................1-10

1.4.7 UARTs ...................................................................................................................... 1-11

1.4.8 I

2

C Bus ...................................................................................................................... 1-11

1.4.9 QSPI .......................................................................................................................... 1-11

1.4.10 Fast ADC .................................................................................................................. 1-11

1.4.11 DMA Timers (DTIM0–DTIM3) ............................................................................... 1-11

1.4.12 General Purpose Timer (GPT) .................................................................................. 1-12

1.4.13 Periodic Interrupt Timers (PIT0 and PIT1) .............................................................. 1-12

1.4.14 Pulse-Width Modulation (PWM) Timers ................................................................. 1-12

1.4.15 Software Watchdog Timer ........................................................................................ 1-12

1.4.16 Phase-Locked Loop (PLL) ........................................................................................ 1-12

1.4.17 Interrupt Controller (INTC) ...................................................................................... 1-13

1.4.18 DMA Controller ........................................................................................................ 1-13

1.4.19 Reset .......................................................................................................................... 1-13

1.4.20 GPIO ......................................................................................................................... 1-13

Contents

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Contents

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Number

Chapter 2

Signal Descriptions

2.1 Introduction ..................................................................................................................... 2-1

2.2 Overview ......................................................................................................................... 2-1

2.3 Reset Signals ................................................................................................................... 2-7

2.4 PLL and Clock Signals ................................................................................................... 2-7

2.5 Mode Selection ............................................................................................................... 2-7

2.6 External Interrupt Signals ............................................................................................... 2-8

2.7 Queued Serial Peripheral Interface (QSPI) ..................................................................... 2-8

2.8 I

2

C I/O Signals ................................................................................................................ 2-9

2.9 UART Module Signals ................................................................................................... 2-9

2.10 DMA Timer Signals ........................................................................................................ 2-9

2.11 ADC Signals ................................................................................................................. 2-10

2.12 General Purpose Timer Signals .................................................................................... 2-10

2.13 Pulse-Width Modulator Signals .................................................................................... 2-10

2.14 Debug Support Signals ................................................................................................. 2-10

2.15 EzPort Signal Descriptions ........................................................................................... 2-12

2.16 Power and Ground Pins ................................................................................................ 2-12

Chapter 3

ColdFire Core

3.1 Processor Pipelines .........................................................................................................3-1

3.2 Memory Map/Register Description ................................................................................ 3-2

3.2.1 Data Registers (D0–D7) .............................................................................................. 3-4

3.2.2 Address Registers (A0–A6) ........................................................................................ 3-4

3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) .............................................. 3-4

3.2.4 Condition Code Register (CCR) ................................................................................. 3-5

3.2.5 Program Counter (PC) ................................................................................................ 3-6

3.2.6 Vector Base Register (VBR) ....................................................................................... 3-6

3.2.7 Status Register (SR) .................................................................................................... 3-7

3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR) .................................... 3-8

3.3 Instruction Set Architecture (ISA_A+) ........................................................................... 3-8

3.4 Exception Processing Overview ..................................................................................... 3-9

3.4.1 Exception Stack Frame Definition ............................................................................ 3-10

3.5 Processor Exceptions .................................................................................................... 3-12

3.5.1 Access Error Exception ............................................................................................ 3-12

3.5.2 Address Error Exception ........................................................................................... 3-12

3.5.3 Illegal Instruction Exception ..................................................................................... 3-12

3.5.4 Divide-By-Zero ......................................................................................................... 3-13

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3.5.5 Privilege Violation .................................................................................................... 3-14

3.5.6 Trace Exception ........................................................................................................ 3-14

3.5.7 Unimplemented Line-A Opcode ............................................................................... 3-14

3.5.8 Unimplemented Line-F Opcode ............................................................................... 3-14

3.5.9 Debug Interrupt ......................................................................................................... 3-15

3.5.10 RTE and Format Error Exception ............................................................................. 3-15

3.5.11 TRAP Instruction Exception ..................................................................................... 3-15

3.5.12 Interrupt Exception ................................................................................................... 3-15

3.5.13 Fault-on-Fault Halt ................................................................................................... 3-15

3.5.14 Reset Exception ........................................................................................................ 3-15

3.6 Instruction Execution Timing ....................................................................................... 3-19

3.6.1 Timing Assumptions .................................................................................................3-19

3.6.2 MOVE Instruction Execution Times ........................................................................3-20

3.6.3 Standard One Operand Instruction Execution Times ............................................... 3-21

3.6.4 Standard Two Operand Instruction Execution Times ............................................... 3-22

3.6.5 Miscellaneous Instruction Execution Times ............................................................. 3-23

3.6.6 MAC Instruction Execution Times ...........................................................................3-24

3.6.7 Branch Instruction Execution Times ........................................................................ 3-25

Chapter 4

Multiply-Accumulate Unit (MAC)

4.1 Multiply-Accumulate Unit ..............................................................................................4-1

4.2 Introduction to the MAC ................................................................................................. 4-1

4.3 General Operation ...........................................................................................................4-2

4.4 Memory Map/Register Definition .................................................................................. 4-3

4.4.1 MAC Status Register (MACSR) ................................................................................. 4-3

4.4.1.1 Fractional Operation Mode ..................................................................................... 4-5

4.4.1.1.1 Rounding ............................................................................................................ 4-5

4.4.1.1.2 Saving and Restoring the MAC Programming Model ....................................... 4-6

4.4.1.1.3 MULS/MULU .................................................................................................... 4-6

4.4.1.1.4 Scale Factor in MAC or MSAC Instructions ...................................................... 4-6

4.4.2 Mask Register (MASK) .............................................................................................. 4-7

4.4.3 Accumulator Register (ACC) ..................................................................................... 4-8

4.5 MAC Instruction Set Summary ...................................................................................... 4-8

4.5.1 MAC Instruction Execution Times .............................................................................4-9

4.5.2 Data Representation .................................................................................................... 4-9

4.5.3 MAC Opcodes ............................................................................................................ 4-9

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Chapter 5

Static RAM (SRAM)

5.1 Introduction ..................................................................................................................... 5-1

5.1.1 Overview ..................................................................................................................... 5-1

5.1.2 Features ....................................................................................................................... 5-1

5.2 Memory Map/Register Description ................................................................................ 5-1

5.2.1 SRAM Base Address Register (RAMBAR) ............................................................... 5-2

5.3 Initialization/Application Information ............................................................................ 5-3

5.3.1 SRAM Initialization Code .......................................................................................... 5-4

5.3.2 Power Management .................................................................................................... 5-4

Chapter 6

Clock Module

6.1 Introduction ..................................................................................................................... 6-1

6.2 Features ........................................................................................................................... 6-1

6.3 Modes of Operation ........................................................................................................ 6-1

6.3.1 Normal PLL Mode ...................................................................................................... 6-1

6.3.2 1:1 PLL Mode ............................................................................................................. 6-2

6.3.3 External Clock Mode .................................................................................................. 6-2

6.4 Low-Power Mode Operation .......................................................................................... 6-2

6.5 Block Diagram ................................................................................................................ 6-2

6.6 Signal Descriptions .........................................................................................................6-4

6.6.1 EXTAL ....................................................................................................................... 6-4

6.6.2 XTAL .......................................................................................................................... 6-4

6.6.3 CLKOUT ....................................................................................................................6-4

6.6.4 CLKMOD[1:0] ........................................................................................................... 6-4

6.6.5 RSTO .......................................................................................................................... 6-5

6.7 Memory Map and Registers ............................................................................................ 6-5

6.7.1 Register Descriptions .................................................................................................. 6-5

6.7.1.1 Synthesizer Control Register (SYNCR) ................................................................. 6-5

6.7.1.2 Synthesizer Status Register (SYNSR) .................................................................... 6-7

6.7.1.3 Low-Power Divider Register (LPDR) .................................................................... 6-9

6.8 Functional Description .................................................................................................. 6-10

6.8.1 System Clock Modes ................................................................................................ 6-10

6.8.2 Clock Operation During Reset .................................................................................. 6-10

6.8.3 System Clock Generation ......................................................................................... 6-11

6.8.4 PLL Operation .......................................................................................................... 6-11

6.8.4.1 Phase and Frequency Detector (PFD) ................................................................... 6-12

6.8.4.2 Charge Pump/Loop Filter ..................................................................................... 6-12

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6.8.4.3 Voltage Control Output (VCO) ............................................................................ 6-13

6.8.4.4 Multiplication Factor Divider (MFD) ................................................................... 6-13

6.8.4.5 PLL Lock Detection ............................................................................................. 6-13

6.8.4.6 PLL Loss of Lock Conditions ............................................................................... 6-14

6.8.4.7 PLL Loss of Lock Reset ....................................................................................... 6-14

6.8.4.8 Loss of Clock Detection ....................................................................................... 6-15

6.8.4.9 Loss of Clock Reset .............................................................................................. 6-15

6.8.4.10 Alternate Clock Selection ..................................................................................... 6-15

6.8.4.11 Loss of Clock in Stop Mode ................................................................................. 6-16

Chapter 7

Power Management

7.1 Introduction ..................................................................................................................... 7-1

7.1.1 Features ....................................................................................................................... 7-1

7.2 Memory Map/Register Definition .................................................................................. 7-1

7.2.1 Peripheral Power Management Registers (PPMRH, PPMRL) ................................... 7-2

7.2.1.1 Peripheral Power Management Register Low (PPMRL) ....................................... 7-4

7.2.2 Low-Power Interrupt Control Register (LPICR) ........................................................ 7-5

7.2.3 Peripheral Power Management Set Register (PPMRS) .............................................. 7-7

7.2.4 Peripheral Power Management Clear Register (PPMRC) .......................................... 7-7

7.2.5 Low-Power Control Register (LPCR) ........................................................................ 7-8

7.3 IPS Bus Timeout Monitor ............................................................................................... 7-9

7.4 Functional Description .................................................................................................. 7-10

7.4.1 Low-Power Modes .................................................................................................... 7-10

7.4.1.1 Run Mode ............................................................................................................. 7-11

7.4.1.2 Wait Mode ............................................................................................................ 7-11

7.4.1.3 Doze Mode ............................................................................................................ 7-11

7.4.1.4 Stop Mode ............................................................................................................. 7-11

7.4.1.5 Peripheral Shut Down ........................................................................................... 7-11

7.4.2 Peripheral Behavior in Low-Power Modes .............................................................. 7-12

7.4.2.1 ColdFire Core ....................................................................................................... 7-12

7.4.2.2 Static Random-Access Memory (SRAM) ............................................................ 7-12

7.4.2.3 Flash ...................................................................................................................... 7-12

7.4.2.4 System Control Module (SCM) ............................................................................ 7-12

7.4.2.5 DMA Controller (DMA0–DMA3) ....................................................................... 7-12

7.4.2.6 UART Modules (UART0, UART1, and UART2) ............................................... 7-12

7.4.2.7 I2C Module ........................................................................................................... 7-13

7.4.2.8 Queued Serial Peripheral Interface (QSPI) ........................................................... 7-13

7.4.2.9 DMA Timers (DTIM0–DTIM3) ........................................................................... 7-13

7.4.2.10 Interrupt Controllers (INTC0, INTC1) ................................................................. 7-13

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7.4.2.11 I/O Ports ................................................................................................................ 7-14

7.4.2.12 Reset Controller .................................................................................................... 7-14

7.4.2.13 Chip Configuration Module .................................................................................. 7-14

7.4.2.14 Clock Module ....................................................................................................... 7-14

7.4.2.15 Edge Port ..............................................................................................................7-15

7.4.2.16 Programmable Interrupt Timers (PIT0–PIT1) ..................................................... 7-15

7.4.2.17 FlexCAN ............................................................................................................... 7-15

7.4.2.18 PWM Module ....................................................................................................... 7-17

7.4.2.19 BDM ..................................................................................................................... 7-17

7.4.2.20 JTAG ..................................................................................................................... 7-17

7.4.3 Summary of Peripheral State During Low-Power Modes ........................................ 7-17

Chapter 8

Chip Configuration Module (CCM)

8.1 Introduction ..................................................................................................................... 8-1

8.1.1 Features ....................................................................................................................... 8-1

8.2 External Signal Descriptions .......................................................................................... 8-1

8.2.1 RCON ......................................................................................................................... 8-2

8.2.2 CLKMOD[1:0] ........................................................................................................... 8-2

8.2.3 JTAG_EN ...................................................................................................................8-2

8.2.4 TEST ........................................................................................................................... 8-2

8.3 Memory Map/Register Definition .................................................................................. 8-2

8.3.1 Programming Model ................................................................................................... 8-2

8.3.2 Memory Map .............................................................................................................. 8-3

8.3.3 Register Descriptions .................................................................................................. 8-3

8.3.3.1 Chip Configuration Register (CCR) ....................................................................... 8-3

8.3.3.2 Reset Configuration Register (RCON) ................................................................... 8-4

8.3.3.3 Chip Identification Register (CIR) ......................................................................... 8-4

Chapter 9

Reset Controller Module

9.1 Introduction ..................................................................................................................... 9-1

9.2 Features ........................................................................................................................... 9-1

9.3 Block Diagram ................................................................................................................ 9-1

9.4 Signals ............................................................................................................................. 9-2

9.4.1 RSTI ............................................................................................................................ 9-2

9.4.2 RSTO

.......................................................................................................................... 9-2

9.5 Memory Map and Registers ............................................................................................ 9-2

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9.5.1 Reset Control Register (RCR) .................................................................................... 9-3

9.5.2 Reset Status Register (RSR) ....................................................................................... 9-4

9.6 Functional Description .................................................................................................... 9-5

9.6.1 Reset Sources .............................................................................................................. 9-5

9.6.1.1 Power-On Reset ...................................................................................................... 9-6

9.6.1.2 External Reset ......................................................................................................... 9-6

9.6.1.3 Loss-of-Clock Reset ............................................................................................... 9-6

9.6.1.4 Loss-of-Lock Reset ................................................................................................. 9-6

9.6.1.5 Software Reset ........................................................................................................ 9-6

9.6.1.6 LVD Reset .............................................................................................................. 9-6

9.6.2 Reset Control Flow ..................................................................................................... 9-6

9.6.2.1 Synchronous Reset Requests .................................................................................. 9-8

9.6.2.2 Internal Reset Request ............................................................................................ 9-8

9.6.2.3 Power-On Reset/Low-Voltage Detect Reset .......................................................... 9-8

9.6.3 Concurrent Resets ....................................................................................................... 9-8

9.6.3.1 Reset Flow ..............................................................................................................9-8

9.6.3.2 Reset Status Flags ................................................................................................... 9-9

Chapter 10

System Control Module (SCM)

10.1 Introduction ................................................................................................................... 10-1

10.2 Overview ....................................................................................................................... 10-1

10.3 Features ......................................................................................................................... 10-1

10.4 Memory Map and Register Definition .......................................................................... 10-2

10.5 Register Descriptions .................................................................................................... 10-3

10.5.1 Internal Peripheral System Base Address Register (IPSBAR) ................................. 10-3

10.5.2 Memory Base Address Register (RAMBAR) .......................................................... 10-4

10.5.3 Core Reset Status Register (CRSR) ..........................................................................10-6

10.5.4 Core Watchdog Control Register (CWCR) .............................................................. 10-7

10.5.5 Core Watchdog Service Register (CWSR) ............................................................... 10-8

10.6 Internal Bus Arbitration ................................................................................................ 10-9

10.6.1 Overview ................................................................................................................... 10-9

10.6.2 Arbitration Algorithms ........................................................................................... 10-10

10.6.2.1 Round-Robin Mode ............................................................................................ 10-10

10.6.2.2 Fixed Mode ......................................................................................................... 10-10

10.6.3 Bus Master Park Register (MPARK) ...................................................................... 10-10

10.7 System Access Control Unit (SACU) .........................................................................10-12

10.7.1 Overview ................................................................................................................. 10-12

10.7.2 Features ................................................................................................................... 10-12

10.7.3 Memory Map/Register Definition ..........................................................................10-13

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10.7.3.1 Master Privilege Register (MPR) ....................................................................... 10-14

10.7.3.2 Peripheral Access Control Registers (PACR0–PACR8) .................................... 10-14

10.7.3.3 Grouped Peripheral Access Control Registers (GPACR0 & GPACR1) ............ 10-16

Chapter 11

General Purpose I/O Module

11.1 Introduction ................................................................................................................... 11-1

11.2 Overview ....................................................................................................................... 11-2

11.3 Features ......................................................................................................................... 11-2

11.4 Signal Descriptions ....................................................................................................... 11-2

11.5 Memory Map/Register Definition ................................................................................ 11-2

11.5.1 Ports Memory Map ................................................................................................... 11-2

11.6 Register Descriptions .................................................................................................... 11-4

11.6.1 Port Output Data Registers (PORTn) ....................................................................... 11-4

11.6.2 Port Data Direction Registers (DDRn) ..................................................................... 11-5

11.6.3 Port Pin Data/Set Data Registers (PORTnP/SETn) .................................................. 11-7

11.6.4 Port Clear Output Data Registers (CLRn) ................................................................ 11-9

11.6.5 Pin Assignment Registers ....................................................................................... 11-10

11.6.5.1 Dual-Function Pin Assignment Registers ........................................................... 11-11

11.6.5.2 Quad Function Pin Assignment Registers .......................................................... 11-11

11.6.5.3 Port NQ Pin Assignment Register (PNQPAR) ................................................... 11-13

11.6.6 Pad Control Registers .............................................................................................11-13

11.6.6.1 Pin Slew Rate Register (PSRR) .......................................................................... 11-13

11.6.6.2 Pin Drive Strength Register (PDSR) .................................................................. 11-15

11.7 Ports Interrupts ............................................................................................................ 11-15

Chapter 12

Interrupt Controller Module

12.1 68K/ColdFire Interrupt Architecture Overview ........................................................... 12-1

12.1.1 Interrupt Controller Theory of Operation ................................................................. 12-2

12.1.1.1 Interrupt Recognition ............................................................................................ 12-3

12.1.1.2 Interrupt Prioritization .......................................................................................... 12-3

12.1.1.3 Interrupt Vector Determination ............................................................................ 12-3

12.2 Memory Map ................................................................................................................ 12-4

12.3 Register Descriptions .................................................................................................... 12-6

12.3.1 Interrupt Pending Registers (IPRHn, IPRLn) ........................................................... 12-6

12.3.2 Interrupt Mask Register (IMRHn, IMRLn) .............................................................. 12-7

12.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) ............................................... 12-9

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12.3.4 Interrupt Request Level Register (IRLRn) ............................................................. 12-10

12.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) ........................ 12-11

12.3.6 Interrupt Control Registers (ICRnx) ....................................................................... 12-11

12.3.6.1 Interrupt Sources ................................................................................................. 12-13

12.3.7 Software and Level m IACK Registers (SWIACKn, LmIACKn) .......................... 12-15

12.3.8 Global Software and Level m IACK Registers (GSWIACK, GLmIACK) ............ 12-16

12.4 Low-Power Wakeup Operation .................................................................................. 12-17

Chapter 13

Edge Port Module (EPORT)

13.1 Introduction ................................................................................................................... 13-1

13.2 Low-Power Mode Operation ........................................................................................ 13-1

13.3 Interrupt/General-Purpose I/O Pin Descriptions ........................................................... 13-2

13.4 Memory Map and Registers .......................................................................................... 13-3

13.4.1 Memory Map ............................................................................................................ 13-3

13.4.2 Registers .................................................................................................................... 13-3

13.4.2.1 EPORT Pin Assignment Register (EPPAR) ......................................................... 13-4

13.4.2.2 EPORT Data Direction Register (EPDDR) .......................................................... 13-4

13.4.2.3 Edge Port Interrupt Enable Register (EPIER) ...................................................... 13-5

13.4.2.4 Edge Port Data Register (EPDR) .......................................................................... 13-5

13.4.2.5 Edge Port Pin Data Register (EPPDR) ................................................................. 13-6

13.4.2.6 Edge Port Flag Register (EPFR) ........................................................................... 13-6

Chapter 14

DMA Controller Module

14.1 Introduction ................................................................................................................... 14-1

14.1.1 Overview ................................................................................................................... 14-1

14.1.2 Features ..................................................................................................................... 14-2

14.2 DMA Transfer Overview .............................................................................................. 14-3

14.3 Memory Map/Register Definition ................................................................................ 14-3

14.3.1 DMA Request Control (DMAREQC) ...................................................................... 14-4

14.3.2 Source Address Registers (SARn) ............................................................................ 14-5

14.3.3 Destination Address Registers (DARn) .................................................................... 14-5

14.3.4 Byte Count Registers (BCRn) and DMA Status Registers (DSRn) ......................... 14-6

14.3.5 DMA Control Registers (DCRn) .............................................................................. 14-8

14.4 Functional Description ................................................................................................ 14-11

14.4.1 Transfer Requests (Cycle-Steal and Continuous Modes) ....................................... 14-12

14.4.2 Dual-Address Data Transfer Mode ......................................................................... 14-12

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14.4.3 Channel Initialization and Startup .......................................................................... 14-13

14.4.3.1 Channel Prioritization ......................................................................................... 14-13

14.4.3.2 Programming the DMA Controller Module ....................................................... 14-13

14.4.4 Data Transfer .......................................................................................................... 14-14

14.4.4.1 Auto-Alignment .................................................................................................. 14-14

14.4.4.2 Bandwidth Control .............................................................................................. 14-14

14.4.5 Termination ............................................................................................................. 14-15

14.5 Document Revision History ........................................................................................ 14-15

Chapter 15

ColdFire Flash Module (CFM)

15.1 Introduction ................................................................................................................... 15-1

15.1.1 Overview ................................................................................................................... 15-1

15.1.2 Features ..................................................................................................................... 15-2

15.2 External Signal Description .......................................................................................... 15-3

15.3 Memory Map and Register Definition .......................................................................... 15-3

15.3.1 Memory Map ............................................................................................................ 15-3

15.3.2 Flash Base Address Register (FLASHBAR) ............................................................ 15-4

15.3.3 Register Descriptions ................................................................................................ 15-7

15.3.3.1 CFMMCR — CFM Module Configuration Register ........................................... 15-7

15.3.3.2 CFMCLKD — CFM Clock Divider Register ...................................................... 15-8

15.3.3.3 CFMSEC — CFM Security Register ................................................................... 15-9

15.3.3.4 CFMPROT — CFM Protection Register ...........................................................15-10

15.3.3.5 CFMSACC — CFM Supervisor Access Register .............................................. 15-12

15.3.3.6 CFMDACC — CFM Data Access Register ....................................................... 15-13

15.3.3.7 CFMUSTAT — CFM User Status Register ....................................................... 15-13

15.3.3.8 CFMCMD — CFM Command Register ............................................................ 15-15

15.3.3.9 CFMCLKSEL — CFM Clock Select Register ................................................... 15-16

15.4 Functional Description ................................................................................................ 15-16

15.4.1 General .................................................................................................................... 15-16

15.4.2 Flash Normal Mode ................................................................................................ 15-17

15.4.2.1 Read Operation ................................................................................................... 15-17

15.4.2.2 Write Operation .................................................................................................. 15-17

15.4.2.3 Program, Erase, and Verify Operations .............................................................. 15-17

15.4.2.3.1 Writing the CFMCLKD Register ................................................................... 15-17

15.4.2.3.2 Command Write Sequence ............................................................................. 15-18

15.4.2.3.3 Bus Arbitration During Write Operations ...................................................... 15-19

15.4.2.3.4 Flash Normal Mode Commands ..................................................................... 15-19

15.4.2.3.4.1 Blank Check ................................................................................................ 15-19

15.4.2.3.4.2 Page Erase Verify........................................................................................ 15-21

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15.4.2.3.4.3 Program ....................................................................................................... 15-23

15.4.2.3.4.4 Page Erase ................................................................................................... 15-24

15.4.2.3.4.5 Mass Erase...................................................................................................15-26

15.4.2.3.5 Flash Normal Mode Illegal Operations .......................................................... 15-29

15.4.2.4 Stop Mode ........................................................................................................... 15-29

15.4.3 Flash Security Operation ........................................................................................ 15-30

15.4.3.1 Backdoor Access Sequence ................................................................................ 15-30

15.4.3.2 Blank Check ........................................................................................................ 15-31

15.4.3.3 JTAG Lockout Recovery .................................................................................... 15-31

Chapter 16

EzPort

16.1 Features ......................................................................................................................... 16-1

16.2 Modes of Operation ...................................................................................................... 16-1

16.3 External Signal Description .......................................................................................... 16-2

16.3.1 Overview ................................................................................................................... 16-2

16.3.2 Detailed Signal Descriptions .................................................................................... 16-2

16.3.2.1 EZPCK — EzPort Clock ...................................................................................... 16-2

16.3.2.2 EZPCS — EzPort Chip Select .............................................................................. 16-3

16.3.2.3 EZPD — EzPort Serial Data In ............................................................................ 16-3

16.3.2.4 EZPQ — EzPort Serial Data Out .......................................................................... 16-3

16.4 Command Definition .................................................................................................... 16-3

16.4.1 Command Descriptions ............................................................................................. 16-4

16.4.1.1 Write Enable ......................................................................................................... 16-4

16.4.1.2 Write Disable ........................................................................................................ 16-4

16.4.1.3 Read Status Register ............................................................................................. 16-4

16.4.1.4 Write Configuration Register ............................................................................... 16-5

16.4.1.5 Read Data .............................................................................................................. 16-6

16.4.1.6 Read Data at High Speed ...................................................................................... 16-6

16.4.1.7 Page Program ........................................................................................................ 16-6

16.4.1.8 Sector Erase .......................................................................................................... 16-7

16.4.1.9 Bulk Erase ............................................................................................................. 16-7

16.4.1.10 Reset Chip ............................................................................................................. 16-7

16.5 Functional Description .................................................................................................. 16-7

16.6 Initialization/Application Information .......................................................................... 16-8

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Chapter 17

Programmable Interrupt Timers (PIT0–PIT1)

17.1 Introduction ................................................................................................................... 17-1

17.1.1 Overview ................................................................................................................... 17-1

17.1.2 Block Diagram .......................................................................................................... 17-1

17.1.3 Low-Power Mode Operation .................................................................................... 17-1

17.2 Memory Map/Register Definition ................................................................................ 17-2

17.2.1 PIT Control and Status Register (PCSRn) ................................................................ 17-3

17.2.2 PIT Modulus Register (PMRn) ................................................................................. 17-4

17.2.3 PIT Count Register (PCNTRn) ................................................................................. 17-5

17.3 Functional Description .................................................................................................. 17-5

17.3.1 Set-and-Forget Timer Operation ............................................................................... 17-5

17.3.2 Free-Running Timer Operation ................................................................................ 17-6

17.3.3 Timeout Specifications ............................................................................................. 17-6

17.3.4 Interrupt Operation ................................................................................................... 17-6

Chapter 18

General Purpose Timer Module (GPT)

18.1 Introduction ................................................................................................................... 18-1

18.2 Features ......................................................................................................................... 18-1

18.3 Block Diagram .............................................................................................................. 18-2

18.4 Low-Power Mode Operation ........................................................................................ 18-3

18.5 Signal Description ......................................................................................................... 18-3

18.5.1 GPT[2:0] ................................................................................................................... 18-3

18.5.2 GPT3 ......................................................................................................................... 18-3

18.5.3 SYNCn ...................................................................................................................... 18-4

18.6 Memory Map and Registers .......................................................................................... 18-4

18.6.1 GPT Input Capture/Output Compare Select Register (GPTIOS) ............................. 18-5

18.6.2 GPT Compare Force Register (GPCFORC) ............................................................. 18-6

18.6.3 GPT Output Compare 3 Mask Register (GPTOC3M) .............................................. 18-6

18.6.4 GPT Output Compare 3 Data Register (GPTOC3D) ................................................ 18-7

18.6.5 GPT Counter Register (GPTCNT) ........................................................................... 18-7

18.6.6 GPT System Control Register 1 (GPTSCR1) ........................................................... 18-8

18.6.7 GPT Toggle-On-Overflow Register (GPTTOV) ...................................................... 18-9

18.6.8 GPT Control Register 1 (GPTCTL1) ........................................................................ 18-9

18.6.9 GPT Control Register 2 (GPTCTL2) ...................................................................... 18-10

18.6.10 GPT Interrupt Enable Register (GPTIE) ................................................................ 18-10

18.6.11 GPT System Control Register 2 (GPTSCR2) ......................................................... 18-11

18.6.12 GPT Flag Register 1 (GPTFLG1) ........................................................................... 18-12

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18.6.13 GPT Flag Register 2 (GPTFLG2) ........................................................................... 18-12

18.6.14 GPT Channel Registers (GPTCn) ........................................................................... 18-13

18.6.15 Pulse Accumulator Control Register (GPTPACTL) .............................................. 18-13

18.6.16 Pulse Accumulator Flag Register (GPTPAFLG) .................................................... 18-14

18.6.17 Pulse Accumulator Counter Register (GPTPACNT) ............................................. 18-15

18.6.18 GPT Port Data Register (GPTPORT) ..................................................................... 18-16

18.6.19 GPT Port Data Direction Register (GPTDDR) ....................................................... 18-16

18.7 Functional Description ................................................................................................ 18-16

18.7.1 Prescaler .................................................................................................................. 18-17

18.7.2 Input Capture .......................................................................................................... 18-17

18.7.3 Output Compare ...................................................................................................... 18-17

18.7.4 Pulse Accumulator .................................................................................................. 18-18

18.7.5 Event Counter Mode ............................................................................................... 18-18

18.7.6 Gated Time Accumulation Mode ........................................................................... 18-18

18.7.7 General-Purpose I/O Ports ...................................................................................... 18-19

18.8 Reset ............................................................................................................................ 18-21

18.9 Interrupts ..................................................................................................................... 18-21

18.9.1 GPT Channel Interrupts (CnF) ............................................................................... 18-21

18.9.2 Pulse Accumulator Overflow (PAOVF) .................................................................18-21

18.9.3 Pulse Accumulator Input (PAIF) ............................................................................ 18-22

18.9.4 Timer Overflow (TOF) ........................................................................................... 18-22

Chapter 19

DMA Timers (DTIM0–DTIM3)

19.1 Introduction ................................................................................................................... 19-1

19.1.1 Overview ................................................................................................................... 19-1

19.1.2 Features ..................................................................................................................... 19-2

19.2 Memory Map/Register Definition ................................................................................ 19-2

19.2.1 DMA Timer Mode Registers (DTMRn) ................................................................... 19-3

19.2.2 DMA Timer Extended Mode Registers (DTXMRn) ................................................ 19-4

19.2.3 DMA Timer Event Registers (DTERn) .................................................................... 19-5

19.2.4 DMA Timer Reference Registers (DTRRn) ............................................................. 19-6

19.2.5 DMA Timer Capture Registers (DTCRn) ................................................................ 19-7

19.2.6 DMA Timer Counters (DTCNn) .............................................................................. 19-7

19.3 Functional Description .................................................................................................. 19-8

19.3.1 Prescaler .................................................................................................................... 19-8

19.3.2 Capture Mode ........................................................................................................... 19-8

19.3.3 Reference Compare ................................................................................................... 19-8

19.3.4 Output Mode ............................................................................................................. 19-8

19.4 Initialization/Application Information .......................................................................... 19-9

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19.4.1 Code Example ........................................................................................................... 19-9

19.4.2 Calculating Time-Out Values ................................................................................. 19-10

Chapter 20

Queued Serial Peripheral Interface (QSPI)

20.1 Introduction ................................................................................................................... 20-1

20.1.1 Block Diagram .......................................................................................................... 20-1

20.1.2 Overview ................................................................................................................... 20-2

20.1.3 Features ..................................................................................................................... 20-2

20.1.4 Modes of Operation .................................................................................................. 20-2

20.2 External Signal Description .......................................................................................... 20-2

20.3 Memory Map/Register Definition ................................................................................ 20-3

20.3.1 QSPI Mode Register (QMR) .................................................................................... 20-3

20.3.2 QSPI Delay Register (QDLYR) ............................................................................... 20-5

20.3.3 QSPI Wrap Register (QWR) ..................................................................................... 20-6

20.3.4 QSPI Interrupt Register (QIR) .................................................................................. 20-6

20.3.5 QSPI Address Register (QAR) ................................................................................. 20-7

20.3.6 QSPI Data Register (QDR) .......................................................................................20-8

20.3.7 Command RAM Registers (QCR0–QCR15) ............................................................ 20-8

20.4 Functional Description .................................................................................................. 20-9

20.4.1 QSPI RAM .............................................................................................................. 20-11

20.4.1.1 Receive RAM ..................................................................................................... 20-11

20.4.1.2 Transmit RAM .................................................................................................... 20-12

20.4.1.3 Command RAM .................................................................................................. 20-12

20.4.2 Baud Rate Selection ................................................................................................ 20-12

20.4.3 Transfer Delays ....................................................................................................... 20-13

20.4.4 Transfer Length ....................................................................................................... 20-14

20.4.5 Data Transfer .......................................................................................................... 20-14

20.5 Initialization/Application Information ........................................................................ 20-15

Chapter 21

UART Modules

21.1 Introduction ................................................................................................................... 21-1

21.1.1 Overview ................................................................................................................... 21-1

21.1.2 Features ..................................................................................................................... 21-2

21.2 External Signal Description .......................................................................................... 21-2

21.3 Memory Map/Register Definition ................................................................................ 21-3

21.3.1 UART Mode Registers 1 (UMR1n) .......................................................................... 21-5

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21.3.2 UART Mode Register 2 (UMR2n) ........................................................................... 21-6

21.3.3 UART Status Registers (USRn) ............................................................................... 21-7

21.3.4 UART Clock Select Registers (UCSRn) .................................................................. 21-9

21.3.5 UART Command Registers (UCRn) ........................................................................ 21-9

21.3.6 UART Receive Buffers (URBn) ............................................................................. 21-11

21.3.7 UART Transmit Buffers (UTBn) ........................................................................... 21-12

21.3.8 UART Input Port Change Registers (UIPCRn) ...................................................... 21-12

21.3.9 UART Auxiliary Control Register (UACRn) ......................................................... 21-13

21.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn) ...................................... 21-13

21.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) ..................................... 21-15

21.3.12 UART Input Port Register (UIPn) .......................................................................... 21-15

21.3.13 UART Output Port Command Registers (UOP1n/UOP0n) ................................... 21-16

21.4 Functional Description ................................................................................................ 21-16

21.4.1 Transmitter/Receiver Clock Source ........................................................................21-16

21.4.1.1 Programmable Divider ........................................................................................ 21-17

21.4.1.2 Calculating Baud Rates ....................................................................................... 21-17

21.4.1.2.1 Internal Bus Clock Baud Rates ....................................................................... 21-17

21.4.1.2.2 External Clock ................................................................................................ 21-17

21.4.2 Transmitter and Receiver Operating Modes ........................................................... 21-17

21.4.2.1 Transmitter .......................................................................................................... 21-18

21.4.2.2 Receiver .............................................................................................................. 21-19

21.4.2.3 FIFO .................................................................................................................... 21-21

21.4.3 Looping Modes ....................................................................................................... 21-22

21.4.3.1 Automatic Echo Mode ........................................................................................ 21-22

21.4.3.2 Local Loop-Back Mode ...................................................................................... 21-22

21.4.3.3 Remote Loop-Back Mode ................................................................................... 21-23

21.4.4 Multidrop Mode ...................................................................................................... 21-23

21.4.5 Bus Operation ......................................................................................................... 21-25

21.4.5.1 Read Cycles ........................................................................................................ 21-25

21.4.5.2 Write Cycles ....................................................................................................... 21-25

21.5 Initialization/Application Information ........................................................................ 21-25

21.5.1 Interrupt and DMA Request Initialization .............................................................. 21-25

21.5.1.1 Setting up the UART to Generate Core Interrupts ............................................. 21-25

21.5.1.2 Setting up the UART to Request DMA Service ................................................. 21-26

21.5.2 UART Module Initialization Sequence .................................................................. 21-27

Chapter 22

I

2

C Interface

22.1 Introduction ................................................................................................................... 22-1

22.1.1 Overview ................................................................................................................... 22-1

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22.1.2 Features ..................................................................................................................... 22-2

22.2 Memory Map/Register Definition ................................................................................ 22-3

22.2.1 I

2

C Address Register (I2ADR) ................................................................................. 22-3

22.2.2 I

2

C Frequency Divider Register (I2FDR) ................................................................. 22-4

22.2.3 I

2

C Control Register (I2CR) ..................................................................................... 22-5

22.2.4 I

2

C Status Register (I2SR) ........................................................................................ 22-5

22.2.5 I

2

C Data I/O Register (I2DR) ................................................................................... 22-7

22.3 Functional Description .................................................................................................. 22-7

22.3.1 START Signal ........................................................................................................... 22-7

22.3.2 Slave Address Transmission ..................................................................................... 22-8

22.3.3 Data Transfer ............................................................................................................ 22-8

22.3.4 Acknowledge ............................................................................................................ 22-9

22.3.5 STOP Signal ............................................................................................................. 22-9

22.3.6 Repeated START ...................................................................................................... 22-9

22.3.7 Clock Synchronization and Arbitration .................................................................. 22-11

22.3.8 Handshaking and Clock Stretching ......................................................................... 22-12

22.4 Initialization/Application Information ........................................................................ 22-12

22.4.1 Initialization Sequence ............................................................................................ 22-12

22.4.2 Generation of START ............................................................................................. 22-12

22.4.3 Post-Transfer Software Response ........................................................................... 22-13

22.4.4 Generation of STOP ................................................................................................ 22-13

22.4.5 Generation of Repeated START ............................................................................. 22-14

22.4.6 Slave Mode ............................................................................................................. 22-14

22.4.7 Arbitration Lost ....................................................................................................... 22-14

Chapter 23

Analog-to-Digital Converter (ADC)

23.1 Introduction ................................................................................................................... 23-1

23.2 Features ......................................................................................................................... 23-1

23.3 Block Diagram .............................................................................................................. 23-2

23.4 Memory Map and Register Definition .......................................................................... 23-2

23.4.1 Control 1 Register (CTRL1) ..................................................................................... 23-3

23.4.2 Control 2 Register (CTRL2) ..................................................................................... 23-5

23.4.2.1 CTRL2 Under Sequential Scan Modes ................................................................. 23-5

23.4.2.2 CTRL2 Under Parallel Scan Modes ..................................................................... 23-6

23.4.3 Zero Crossing Control Register (ADZCC) ............................................................... 23-8

23.4.4 Channel List 1 and 2 Registers (ADLST1 and ADLST2) ........................................ 23-8

23.4.5 Sample Disable Register (ADSDIS) ....................................................................... 23-10

23.4.6 Status Register (ADSTAT) ..................................................................................... 23-11

23.4.7 Limit Status Register (ADLSTAT) ......................................................................... 23-13

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