MINIDISC CHANGER
US Model
Canadian Model
AEP Model
UK Model
E Model
SERVICE MANUAL
MDX-61
SPECIFICATIONS
– Continued on next page –
Model Name Using Similar Mechanism MDX-60
Base Mechanism Type MG-798-133
Optical Pick-Up Name KMS-193C/J2N
This set is automatic electrical adjustment.
System Mini disc digital audio system
Laser Diode Properties
Material: GaAlAs
Wavelength: 780nm
Emission Duration: Continuous
Laser out-put Power: Less than 44.6µW*
* This output is the value measured at a distance
of 200 mm from the objective lens surface on
the Optical Pick-up Block.
Frequency response
20–20,000 Hz
Wow and flutter
Below measurable limit
Signal-to-noise ratio
95 dB
Output Bus control output (8 PIN)
Analog audio output (RCA PIN)
Current drain
300 mA (MD playback)
600 mA (during loading or ejecting a disc)
Dimensions Approx. 176×83.5×125 mm
(7×3
3
/8×5 in.) (w/h/d)
not incl. projecting parts and controls
Mass Approx. 1.1 kg (2 lb. 7 oz.)
Power requirement
12 V DC car battery
(negative ground)
Supplied accessories
Mounting hard ware (1 set)
Bus cable 5.5 m (1)
RCA pin cord 5.5 m (1)
• U.S. and foreign patents licensed from Dolby Laboratories
Licensing Corporation.
• Design and specifications subject to change without notice.
9-925-528-12 Sony Corporation
2001H0500-1 e Vehicle Company
C 2001.8 Shinagawa Tec Service Manual Production Group
Ver 1.1 2001.08
– 2 –
ATTENTION AU COMPOSANT AYANT RAPPORT
À LA SÉCURITÉ!
LES COMPOSANTS IDENTIFIÉS PAR UNE MARQUE !
SUR LES DIAGRAMMES SCHÉMATIQUES ET LA LISTE
DES PIÈCES SONT CRITIQUES POUR LA SÉCURITÉ
DE FONCTIONNEMENT. NE REMPLACER CES COM-
POSANTS QUE PAR DES PIÈCES SONY DONT LES
NUMÉROS SONT DONNÉS DANS CE MANUEL OU
DANS LES SUPPLÉMENTS PUBLIÉS PAR SONY.
TABLE OF CONTENTS
1. GENERAL ..................................................................... 3
2. DISASSEMBLY............................................................ 7
3. DIAGRAMS
3-1. Block Diagram................................................................... 11
3-2. Printed Wiring Boards - Servo Section –........................... 13
3-3. Schematic Diagram – Servo Section – .............................. 15
3-4. Schematic Diagram – Main Section – ............................... 20
3-5. Printed Wiring Boards – Main Section – ........................... 23
3-6. Schematic Diagram – Power Section – ............................. 26
3-7. Printed Wiring Board – Power Section –........................... 29
3-8. IC Pin Function Description .............................................. 33
4. EXPLODED VIEWS ................................................... 41
5. ELECTRICAL PARTS LIST .................................... 45
SERVICING NOTE
[To place this set in the play mode]
This set does not have the key control function, and
therefore it cannot activate the play mode by itself.
Also, the key control to this set is done through a
serial communication with the master unit (SONY Bus
System compatible car audio, TV tuner, source
selector, etc.). Accordingly, if repairing this set,
connect as shown below:
MDX-61
Master unit
(MDX-C150/
C150RDS, etc.)
Bus control
input terminal
Bus control
output terminal
SAFETY-RELATED COMPONENT WARNING!!
COMPONENTS IDENTIFIED BY MARK ! OR DOTTED
LINE WITH MARK ! ON THE SCHEMATIC DIAGRAMS
AND IN THE PARTS LIST ARE CRITICAL TO SAFE
OPERATION. REPLACE THESE COMPONENTS WITH
SONY PARTS WHOSE PART NUMBERS APPEAR AS
SHOWN IN THIS MANUAL OR IN SUPPLEMENTS PUB-
LISHED BY SONY.
CAUTION
Use of controls or adjustments or performance of pro-
cedures other than those specified herein may result
in hazardous radiation exposure.
– 3 –
SECTION 1
GENERAL
This section is extracted
from instruction manual.
– 4 –
– 5 –
– 6 –
– 7 –
Note: Follow the disassembly procedure in the numerical order given.
FRONT PANEL ASS’Y, CASE (UPPER)
SECTION 2
DISASSEMBLY
REAR PANEL ASS’Y, MD SECTION
1
two screws (B2.6
×
6)
2
claw
3
front panel ass’y
4
connector (CN620)
5
case (upper)
1
two screws
(B2.6
×
6)
2
claw
4
two dampers
6
two springs
6
two springs
7
1
two screws (B2.6
×
8)
2
rear panel ass’y
3
flexible board
(CN800)
4
two dampers
5
two springs
– 8 –
CHASSIS (GEAR) ASS’Y, MAIN BOARD
CHASSIS (BASE) ASS’Y, CHASSIS (OP) ASS’Y
4
flexible board (CN500)
5
connector (CN602)
1
three screws (P1.7
×
1.8)
2
chassis (gear) ass’y
3
special flat screw (1.7
×
3)
3
two special flat screws
(1.7
×
3)
6
flexible board (CN610)
7
three connectors
(CN603, 700, 701)
8
MAIN board
3
worm wheel (LD)
1
screw (P1.7
×
1.8)
A
1
screw (P1.7
×
1.8)
4
chassis (base) ass’y
2
feed screw (ELV) ass’y
1
four screws (P1.7
×
1.8)
5
Pull up the chassis (OP) ass’y
in the arrow
A
direction.
– 9 –
SERVO BOARD
OPTICAL PICK-UP (KMS-193C/J2N)
1
flexible board (CN200)
2
three special head screws (M1.7
×
2)
6
servo board
3
flexible board (CN100)
5
connector (CN301)
4
flexible board (CN400)
2
optical pick-up
(KMS-193C/J2N)
1
two screw (K1.7
×
3.5)
– 10 –
• Circuit Boards Location
SECTION 3
DIAGRAMS
SW board
POWER board
SERVO board
LAMP board
MAIN board
– 11 –
– 12 –
MDX-61
3-1. BLOCK DIAGRAM
+9V
(LINE AMP)
DCS6
DCS1
11
FOCUS
8
DRIVER
CONTROL
5
6
IC300
SLED/SPINDLE MOTOR DRIVE,
FOCUS/TRACKING COIL DRIVE
26
TRACKING
29
DRIVER
CONTROL
32
31
24
M902
SLED
22
DRIVER
CONTROL
19
20
M
15
M901
SPINDLE
13
DRIVER
CONTROL
17
18
M
5
2
4
7
14
AAPC
10
PD
LD
AUTOMATIC
POWER CONTROL
Q100
IC100
RF AMP
XRST
SWDT
SCLK
RFO
44
AGCI
43
DETECTOR
JI
F
E
A
BC
D
IC500
SHOCK PROOF MEMORY CONTROLLER
ATRAC ENCODER/DECODER
XOE
XCAS
61
62
A09
XRAS
66
65
69
·
68
·
70
·
71
1
·
2
·
24
·
25
22
DE
23
CAS
5
AB
4
RAS
D4
D0
AO8
D3
D0
A8
IC501
RAM
IC700
ELEVATOR MOTOR DRIVE
7
M904
(ELEVATOR)
9
DRIVER
CONTROL
4
2
M
IC701
LOADING MOTOR DRIVE
7
M903
(LOADING)
9
DRIVER
CONTROL
4
2
M
9
12
2
10
8
4
5
3
3
48
6
47
F
C
B
J
A
D
E
I
PD
XRST
SWDT
SCLK
XLAT
XLAT
20
18
17
19
RF
41
TE
SE
ADFG
33
26
29
AUX
FE
BOTM
38
34
35
PEAK
ABCD
39
37
82
ADFG
76
SE
77
TE
58
RFI
78
AUX2
68
AUX1
PEAK HOLD
Q200
IC200
DIGITAL SIGNAL PROCESSOR
DIGITAL SERVO SIGNAL PROCESSOR,
EFM/ACIRC ENCODER/DECODER
64
PEAK
65
BOTM
67
FE
66
ABCD
4 2 84
LDDRAPC REF
11
IC201
INVERTER
87
FFDR
89
FRDR
86
TFDR
85
TRDR
93
SPRD
94
SPFD
91
SRDR
92
SFDR
XLAT
XLAT
10
4
XLAT
SCLK
SCLK
9
3
SCK
SWDT
SWDT
8
2
SWDT
XRST
XRST
16
17
XRST
SENS
SENS
12
6
SENS
SRDT
SRDT
11
5
SRDT
SQSY
SQSY
14
FOK
FOK
2
DTO
30
DTI
DFCT
C2PO
31
29
3
BCK
LRCK
XTAI
35
32
33
92
C2PO
97
MIN
93
DATA
91
BCK
87
SPO
90
LRCK
OSCI
OSC O
37
36
X500
45.1584MHz
55
ı
52
·
56
ı
60
9
ı
12
·
14
ı
18
AO0
A0
XWE
67 3
WE
XRST
XLAT
SWDT
SCLK
SENS
43 54
SENS
SRDT
65 52
MD-SI
SQSY
89 62
SQSY
FOK
1011 64
FOK
21 55
CC-XINT
59
MD-RST
58
MD-LAT
45
MD-SO
51
MD-CKO
IC602
LEVEL SHIFT
X INT
9
SERIAL
INPUT
DAC
DAC
LPF
LPF
IC550
D/A CONVERTER
1
3
D OUT
41
ALRCK
44
8
5
R-CH
4
6
M1
7
M1
8
M2
9
M2
S901
(HOME POSITION DET)
13
HOME
S902
(LES)
11
LES
S620
DOOR OPEN
/CLOSE DET
57
DOOR-SW
S611-616
(EJECT)
S400
(LIMIT DET)
56
LIMIT-SW
RV901
ELEVATOR HIGHTER
POSITION DET(EHS)
40
EHS
S903
(SES)
12
SES
14
ı
19
MDMON
10
78
411
69
10
213
IC900
BUS INTERFACE
RESET
SW
SW
RST
30
UNICKI
48
UNISO
50
UNISI
49
BUS-ON
61
IC601
RESET
+
–
3
IC800
LINE AMP
1
2
MUTING
Q810, 820
64
8
31 2
5
CNP1
(L)
(R)
A-MUT
67
R-CH
BU-IN
60
BATTERY DET
Q920, 921
LINE
OUTPUT
+9V REG.
Q940, 941
+3.3V REG.
Q931
+3.3V
(D/A CONV)
+5V
(PULL UP)
+5V
(MOTOR DRIVE)
ERROR
AMP
COMP OUT
4
3
7
ERROR
AMP
COMP OUT
13
14
10
+5V REG.
Q952
+5V REG.
Q954
+3.3V REG.
Q953
+3.3V
LAMP DRIVE
Q600, 601
7
Q500, 501
SWITCHING
IC950
REGULATOR CONTROL
PL620
ILLUMINATION
LAMP
35
34
X601
32.768kHz
31
32
X600
10MHz
XTAL
EXTAL
TX
TEX
63
STR-SW
S600
(STOP)
21
ILL ON
IC600
SYSTEM CONTROLLER
• R-CH : Same as L-ch
• SIGNAL PATH
: PLAY
(BUS CONTROL CONNECTOR)
(SHASSIS)
OPTICAL PICK-UP BLOCK
(KMS-193C/J2N)
MUTING
SWITCH
Q560, 561
MUTING
CONTROL
SWITCH
Q800
Q950
B+ SWITCH
+5V
(SYSTEM CONTROLLER)
+6V REG.
Q910, 911
– 31 –
– 32 –
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
1413
12
11
21
22
23
24
25
26
A0–A9
SENSE REFRESH AMP
INPUT/OUTPUT CONTROL SWITCH
(4) INPUT
BUFFER
(4) OUTPUT
BUFFER
CLOCK OSC
COLUMN DECODER
MEMORY CELL
(4194204 BIT)
A0–A9
ROW DECODER
GND
D4
D3
XCAS
XOE
NC
NC
NC
A8
A7
A6
A5
A4VDD
A3
A2
A1
A0
A9
NC
NC
NC
XRAS
XWE
D2
D1
ADDRESS BUFFER
IC550 CS4330-KSR-H IC700, 701 LB1638M
DE-EMPHASIS
VOLTAGE REFERENCE
INTERPOLATOR
DELTA-SIGMA
MODULATOR
ANALOG
LOW-PASS
FILTER
DAC
SERIAL INPUT
INTERFACE
1
2
3
4
5
6
7
8
SDATAI
D
EM/SCLK
LRCK
MCLK
AOUT L
VA+
AGND
AOUT R
1
2
3
4
5 6
7
8
9
10
GND
IN1
VCC
IN2
GND
N.C.
OUT2
VS
OUT1
N.C.
CONTROL LOGIC
– POWER section –
IC900 MM1284XFFE IC950 TL1451ACDB-E20
RESET
SW
SW
SW
1
2
3
4
5
6
7 8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
RESET
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON INPUT
BUS ON OUT
REFERENCE
VOLTAGE
LATCH
TRIANGLE
OSCILLATOR
VERF.
+2.5V
+2.5V
+
–
U.V.L.O
–
+
+
–
1
2 3
4
5 6 7 8
9
10
16 15 14 13 12
11
PWM
COMPA-
RATOR2
OUTPUT2
OUTPUT1
GND
PWM
COMPA-
RATOR1
VERF
SR R
VERF
VERF
ERROR
AMP2
ERROR
AMP1
VREF/2
SHORT
CIRCUIT
PROTECTION
COMPARATOR
VCC
+
REF
OUT
S.C.P
NON-INV-
INPUT2
INV-
INPUT2
FEED
BACK2
DEAD
TIME
CONTROL2
OUT2
VCC
GND
OUT1
RT
NON-INV-
INPUT1
INV-
INPUT1
FEED
BACK1
DEAD
TIME
CONTROL1
CT
• IC Block Diagrams
– SERVO section –
– MAIN section –
IC501 HM51W4400TT6-8
IC200 CXD2535CR-1
SHCK
4
DFCT
3
FOK
2
TEOK
1
75 70 69 68 67 66 65 63 62 61 60 59 58 57 56 55 54 53 52 51
50
DVSS
DIPO
TEST2
MVC1
RAOF
EFMO
49
48
46
45
GFS
43
GTOP
42
RFCK
40
WDCK
39
DVDD
38
XBCK
37
MCLK
36
XTAI
35
XTAO
34
LRCK
33
BCK
32
C2PO
31
DTO
30
DTI
DIDT
28
DODT
27
DOVF
26
WFCK
41
XPLCK
44
74 73 72 71
AVSS
ADRB
ADRT
AVDD
BIA2
ADIO
VC
AUX
FE
ABCD
BOTM
PEAK
FILO
FILI
PCO
CLTV
AVSS
DVDD
DIFO
DIFI
DICV
RFI
BIAS
ASYI
ASYO
DVSS
25
REC
ADER
23
FMCK
22
DOUT
20
SBIOT
SBODT
18
SBOCK
XRST
DQSY
15
SQSY
14
ADSY
13
SENS
12
SRDT
11
XLAT
10
SCLK
9
SWDT
8
DIRC
7
WRPWR
SSTOP
DVSS
100
COUT
99
OFTRK
98
XDCL
97
DCLI
96
DCLO
95
SPFD
94
SPRD
93
SFDR
92
SRDR
91
FS4
90
FRDR
89
DVDD
88
FFDR 87
TFDR
86
TRDR
85
LDDR
84
TS25
83
ADFG
TEST1
81
APC
80
MID
79
TENV
78
TE
77
SE
76
DIN
ANALOG MUX
34 MHz
PLL
A/D
CONVERTER
OP AMP
SERVO DSP
PWM GENERATOR
DIGITAL
CLV
PROCESSOR
OFTRK/DFCT/
FOK/C OUT/
SHCK/TEOK
PROCESSOR
SERVO
CONTROL
CPU I/F
SENS
CONTROL
SERVO AUTO
SEQUENCER
APC COMP./
FILTER
APC PWM
GENERATOR
DIN PLL
(22 MHz)
COMP
ECC
ENCODER/
DECODER
REGISTER
32K RAM
REGISTER
AUDIO
DATA
CONTROL
EFM
MODULATOR
TIMING
GENERATOR
EFM
DIGITAL PLL
EFM SYNC
DETECTOR/
PROTECTOR
TIMING GENERATOR
DIGITAL
AUDIO
IN/OUT
PEAK
DETECT
64
47
EFM
DEMODULATOR
CLOCK
GENERATOR
29
242119
SUBCODE
P~W
PROCESSOR
17
16
ADIP
DEMODULATOR
ADIP
DECODER
65
82
TRACKING PWM
FOCUS PWM
SLED PWM
TRACKING SERVO
FOCUS SERVO
SLED SERVO
SUBCODE Q
READER/
GENERATOR
VC
VC
VC
VC
VC
VC
VC
VC
36 7
VG
VD
12
VD
16
VD
8
FO1
11
RO1
9
PGND
10
PGND
15
FO2
13
RO2
14
PGND
21
VD
25
VD
30
VD
29
FO3
26
RO3
27
PGND
28
PGND
22
FO4
24
RO4
23
PGND
2
VC
3
CLK
34
PS
6
FI1
5
RI1
33
OE
17
FI2
18
RI2
31
FI3
32
RI3
20
F/R4
19
PI4
4
GND
35
GND
1
G
VC
VC
CLOCK
DC/DC
CONVERTER
CLK
DETECTOR
DRIVER
PRE-DRIVER
CONTROL
DRIVER
PRE-DRIVER
CONTROL
DRIVER
PRE-DRIVER
CONTROL
DRIVER
PRE-DRIVER
CONTROL
IC300 MPC17A38ZVMEL
– 33 –
Pin No. Pin Name I/O Function
3-8. IC PIN FUNCTION DESCRIPTION
SERVO BOARD IC100 CXA1981AR (RF AMP)
1 VC O Output terminal for the center point voltage (1/2 VCC) generated
2-7 A-F I Signal input from detector circuit in the optical pick-up block
8 FI I Signal input of the operational amplifier for F signal
9 FO O Signal output of the operational amplifier for F signal
10 PD I Front monitor Connected to the photo diode
11 APCREF I Input terminal for the setting of laser power
12 TEMPI I Terminal for the connection to temperature sensor Not used this set (OPEN)
13 GND – Ground terminal
14 AAPC O LD amplifier output terminal of APC circuit
15 DAPC O Not used (OPEN)
16 TEMPR O Output terminal of the reference voltage for temperature sensor Not used this set (OPEN)
17 XRST I Reset signal input from the system controller (IC600) When reset : “L”
18 SWDT I Write data signal input from the system controller (IC600)
19 SCLK I Clock signal input from the system controller (IC600)
20 XLAT I Latch signal input from the system controller (IC600)
21 VREF O Reference voltage output Not used this set (OPEN)
22 TENV O Not used (OPEN)
23 THLD I Not used (OPEN)
24 VCC – Power supply terminal (+3.3V)
25 TFIL I Not used (OPEN)
26 TE O Tracking error signal output to CXD2535CR (IC200)
27 TLB I Input terminal of the adder signal to tracking error Not used this set (OPEN)
28 CSLED I Terminal for the sled error lowpass filter
29 SE O Sled error signal output to CXD2535CR (IC200)
30 ADFM O FM signal output terminal of the ADIP
31 ADIN I Input terminal by AC coupling is FM signal of the ADIP
32 ADAGC I External capacitor connect terminal for AGC of the ADIP
33 ADFG O ADIP double turned FM signal output to CXD2535CR (IC200) (22.05kHz ± 1kHz)
34 AUX O Sub signal output to CXD2535CR (IC200)
35 FE O Focus error signal output to CXD2535CR (IC200)
36 FLB I Input terminal of the adder signal to focus error Not used this set (OPEN)
37 ABCD O Light amount signal output to CXD2535CR (IC200)
38 BOTM O Light amount bottom hold signal output to CXD2535CR (IC200)
39 PEAK O Light amount peak hold signal output to CXD2535CR (IC200)
40 PFAGC I External capacitor connect terminal of AGC circuit for the RF
41 RF O Playback EFM RF signal output to CXD2535CR (IC200)
42 ISET I Setting terminal for the internal circuit constant 22kHz, BPF center frequency
43 AGCI I Input terminal by AC coupling is RF signal
44 RFO O RF signal output terminal
45 MORFI I Input terminal by AC coupling is RF signal of the MO
46 MORFO O RF signal output terminal of the MO
47, 48 I, J I Signal input from detector circuit in the optical pick-up block
– 34 –
Pin No. Pin Name I/O Function
1 FS256 O 11.2896MHz clock signal output (MCLK system) Not used this set (OPEN)
2 FOK O Focus OK signal output to the system controller (IC600) “H” is output when the focus is applied
3 DFCT O Defect ON/OFF selection signal output to CXD2536CR (IC500)
4 SHCK O Track jump detection signal output to the system controller Not used this set (OPEN)
5 SHCKEN I Track jump detection enable input Not used this set (Fixed at “L”)
6 WRPWR I Laser power selection signal input from the system controller Not used this set (Fixed at “L”)
7 DIRC I Not used this set (Fixed at “H”)
8 SWDT I Write data signal input from the system controller (IC600)
9 SCLK I Serial clock signal input from the system controller (IC600)
10 XLAT I Serial latch signal input from the system controller (IC600)
11 SRDT O Read data signal output to the system controller (IC600)
12 SENS O (3) Internal status (SENS) output to the system controller (IC600)
13 ADSY O ADIP sync signal output Not used this set (OPEN)
14 SQSY O
Sub-code Q sync (SCOR) output to the system controller (IC600)
“L” every 13.3msec, Almost “H”
15 DQSY O
Digital in U-bit CD format sub-code Q sync (SCOR) output to the system controller (IC600)
“L” every 13.3msec, Almost “H”
16 XRST I Reset sigmal input from the system controller (IC600) When reset “L”
17 TEST4 I Test input terminal (Fixed at “L”)
18 CLVSCK O Not used this set (OPEN)
19 TEST5 I Test input terminal (Fixed at “L”)
20 DOUT O Output terminal of the digital audio signal (for optical out) Not used this set (OPEN)
21 DIN I Input terminal of the digital audio signal (for optical out) Not used this set (Fixed at “L”)
22 FMCK O FM modulation clock signal output of the ADIP Not used this set (OPEN)
23 ATER O ADIP CRC flag output When error “H” Not used this set (OPEN)
24 REC I
Record/playback selection signal input
When recording :“H”, when playback :“L” (Fixed at “L”)
25 DVSS – Ground terminal (Digital system)
26 DOVF I Validity flag input terminal for the digital audio out Not used this set (Fixed at “L”)
27 DODT I Input terminal of 16-bit data signal for the digital audio out Not used this set (Fixed at “L”)
28 DIDT O Output terminal of 16-bit data signal for the digital audio in Not used this set (OPEN)
29 DTI I Record audio data signal input from CXD2536CR (IC500)
30 DTO O (3) Plyback audio data signal output to CXD2536CR (IC500)
31 C2PO O
C2PO (indicate the error state of the data) signal output to CXD2536AR (IC500)
Playback : C2PO (“H”), Digital recording : D. In-Vflag, Analog recording : “L”
32 BCK O Bit clock (2.8224MHz) signal output to CXD2536CR (IC500) (MCLK system)
33 LRCK O L/R clock (44.1kHz) signal output to CXD2536CR (IC500) (MCLK system)
34 XTAO O System clock (512Fs=22.5792MHz) signal output Not used this set (OPEN)
35 XTAI I System clock (512Fs=22.5792MHz) signal input from CXD2536CR (IC500)
36 MCLK O MCLK clock (22.5792MHz) signal output Not used this set (OPEN)
37 XBCK O BCK (pin #™) inverted output Not used this set (OPEN)
38 DVDDO – Power supply terminal (+3.3V) (Digital system)
39 WDCK O WDCK clock (88.2kHz) signal output (MCLK system) Not used this set (OPEN)
40 RFCK O RFCK clock (7.35kHz) signal output (MCLK system) Not used this set (OPEN)
SERVO BOARD IC200 CDX2535CR-1 (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC
ENCODER/DECODER)
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