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Introduction
The Rockwell RS56-PCI (SoftK56) Host Software
Processed V.90/K56flex
Modem Device Family supports
high speed analog data, 14.4 kbps fax, voice/TAM, and
speakerphone (optional) operation. The modem operates
with PSTN telephone lines in the U.S. and world-wide.
Models are available in different packages with or without
speakerphone support (see Table 1).
The SoftK56 modem family is available in three forms:
1.
A single 144-pin thin quad flat pack (TQFP) that
combines the PCI Bus Interface (BIF) and Line Codec
(LC). This is the lowest cost device option. This
device set also supports data/fax/voice/TAM with
optional speakerphone using the Line/Voice Codec
(LVC).
2.
A 2-device set plug-compatible with Rockwell’s
RC56HCF-PCI host-controlled modem family. The
two devices are the PCI Bus Interface in 176-pin
TQFP and LVC in 144-pin TQFP. This device set
supports data/fax/voice/TAM with optional
speakerphone.
3.
A 2-device set with a Line Codec (LC) in the smallest
device footprint. The two devices are the PCI Bus
Interface in 176-pin TQFP and LC in 32-pin TQFP.
This device set supports data/fax/voice/TAM.
This device set is intended for application in PCI-based
embedded motherboards, system boards, or plug-in cards
designed for desktop use. Typical application block
diagrams are illustrated in Figure 1.
Modem data pump and controller functions, traditionally
enabled using dedicated hardware, are processed in a
Pentium MMX-compatible CPU using host-signal
processing modem software.
In ITU-T V.90/K56flex data mode, the modem can receive
data at speeds up to 56 kbps from a digitally connected
V.90 or K56flex-compatible central site modem. A
V.90/K56flexmodem takes advantage of the PSTN which
is primarily digital except for the client modem to central
office local loop and are ideal for applications such as
remote access to an Internet Service Provider (ISP), on-
line service, or corporate site. In this mode, the modem
can transmit data at speeds up to V.34 rates.
In V.34 data mode, the modem operates at line speeds up
to 33.6 kbps. When applicable, error correction
(V.42/MNP 2-4) and data compression (V.42 bis/MNP 5)
maximize data transfer integrity and boost average data
throughput. Non-error-correcting mode is also supported.
All models support remote audio recording and remote
audio playback over the telephone line interface using A-
Law,
µ
-Law, or linear coding at 8000 or 7200 Hz sample
rate to support applications such as digital telephone
answering machine (TAM) and voice annotation.
SP models support position independent, full-duplex
speakerphone (FDSP).
Fax Group 3 send and receive rates are supported up to
14.4 kbps with T.30 protocol.
V.80 synchronous access mode supports host-controlled
communication protocols, e. g., H.324 video conferencing.
Reference design kits are available to minimize
application design time and costs.
Features
•
Data modem
−
ITU-T V.90, K56flex, V.34 (33.6 kbps), V.32 bis, V.32,
V.22 bis, V.22, V.23, and V.21; Bell 212A and 103
−
V.42 LAPM and MNP 2-4 error correction
−
V.42 bis and MNP 5 data compression
−
V.250 (ex V.25 ter) and V.251 (ex V.25 ter Annex A)
commands
•
Fax modem send and receive rates up to 14.4 kbps
−
ITU-T V.17, V.29, V.27 ter, and V.21 channel 2
−
EIA/TIA 578 Class 1 and T.31 Class 1.0 commands
•
Voice, telephony, TAM
−
V.253 commands
−
8-bit
µ
-Law/A-Law coding (G.711)
−
8-bit/16-bit linear coding
−
8000/7200 Hz sample rate
−
Music on hold from host or analog hardware input
−
TAM support with concurrent DTMF detect, ring detect
and caller ID
•
V.80 synchronous access mode supports host-controlled
communication protocols
−
H.324 interface support
•
V.8/V.8bis and V.251 (ex V.25 ter Annex A) commands
•
Speakerphone model (optional)
−
Telephone handset interface
−
External microphone and speaker interface
•
Full-duplex Speakerphone (FDSP) Mode (SP model)
−
Microphone gain and muting
−
Speaker volume control and muting
−
Adaptive acoustic, line, and handset echo cancellation
−
Loop gain control, transmit and receive path AGC
−
Switching to/from data and fax
•
Data/Fax/Voice call discrimination
•
Multiple country support
−
Call progress, blacklisting
•
Single profile stored in host
•
Modem and audio paths concurrent across PCI bus
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Features (Continued)
•
System compatibilities
−
Windows 95, Windows 95 OSR2, Windows 98,
Windows NT 4.0, Windows NT 5.0 operating systems
−
Microsoft's PC 98 Design Initiative compliant
−
Unimodem/V compliant
•
32-bit PCI Local Bus interface
−
Conforms to the PCI Local Bus Specification,
Production Version, Revision 2.1
−
PCI Bus Mastering interface to the LVC
−
33 MHz PCI clock support
•
Supports PCI Bus Power Management
−
Conforms to PCI Bus Power Management
Specification, Rev. 1.1
−
ACPI Power Management Registers
−
PME# and APM support
•
Device packages:
−
BIF and LVC in a single 144-pin TQFP
−
BIF in 176-pin TQFP and LC in 32-pin TQFP
−
BIF in 176-pin TQFP and LVC in 144-pin TQFP
•
+3.3V operation with +5V tolerant digital inputs
•
+5V (recommended) or +3.3V analog operation
Table 1. Modem Models and Functions
K56flex is a trademark of Rockwell International and Lucent Technologies.
MNP is a trademark of Compaq Computer Corporation.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
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MD231F1 BD
TELEPHONE
LINE
RS56/SP-PCI 2-DEVICE
(RC56HCF-PCI PIN COMPATIBLE)
PCI BUS
INTERFACE
[11235;
176-PIN TQFP]
HANDSET (OPTIONAL)
[TAM AND SP MODELS]
b. Typical Application Block Diagram for RS56-PCI 176-TQFP BIF and 32-TQFP LC Device Set
TELEPHONE LINE/
TELEPHONE HANDSET/
MIC AND SPEAKER
INTERFACE CIRCUIT
PCI BUS
SPEAKER (OPTIONAL)
MIC (OPTIONAL)
[SP MODELS]
LINE CODEC
(LC)
[20437:
32-PIN TQFP]
PCI BUS
INTERFACE
[11235;
176-PIN TQFP]
LINE/VOICE
CODEC
(LVC)
[20410:
144-PIN TQFP]
RS56-PCI SINGLE DEVICE
COMBINED PCI BUS
INTERFACE AND LINE/VOICE
CODEC
(LVC)
[R6793;
144-PIN TQFP]
RS56-PCI 2-DEVICE
TELEPHONE
LINE
HANDSET (OPTIONAL)
[TAM AND SP MODELS]
TELEPHONE LINE/
TELEPHONE HANDSET/
MIC AND SPEAKER
INTERFACE CIRCUIT
SPEAKER (OPTIONAL)
MIC (OPTIONAL)
[SP MODELS]
SOUND CARDS OR DEVICE(S)
AND AUDIO INTERFACE CIRCUIT
SPEAKER (OPTIONAL)
MIC (OPTIONAL)
[OPTIONAL FOR SPEAKERPHONE
OPERATION WITH SP MODEL]
PCI BUS
SOUND CARDS OR DEVICE(S)
AND AUDIO INTERFACE CIRCUIT
SPEAKER (OPTIONAL)
MIC (OPTIONAL)
[OPTIONAL FOR SPEAKERHONE
OPERATION WITH SP MODEL]
TELEPHONE
LINE
TELEPHONE LINE/
TELEPHONE HANDSET
INTERFACE CIRCUIT
c. Typical Application Block Diagram for RS56-PCI 176-TQFP BIF and 144-TQFP LCV Device Set
a. Typical Application Block Diagram for
RS56-PCI 144-TQFP Combined BIF and LVC Device
PCI BUS
PCI BUS
PCI BUS
Figure 1. RS56-PCI Configuration Block Diagrams
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Description
General
The RS56-PCI Device Sets provide the processing core
for a complete system design featuring data/fax modem,
voice/TAM, and speakerphone depending on specific
model (Table 1).
Note: The term, “SoftK56”, refers to the family of modem
models listed in Table 1.
The modem is the full-featured, self-contained data
modem, fax modem, voice/TAM, and speakerphone
(optional) solution. These functions, as well as dialing, call
progress, telephone line interface and host interface
functions are supported and controlled through the
command set.
The modem hardware connects to the host PC via a PCI
bus interface. The OEM adds a crystal circuit, telephone
line interface, telephone interface (optional), and audio
interface (optional) to complete the system.
Host-Processed Modem Software
The host-processed modem software performs two
distinct tasks:
1.
General modem control, which includes command
sets, fax Class 1, voice/TAM, speakerphone, error
correction, data compression, and operating system
interface functions.
2.
Modem data pump signal processing, which includes
data and facsimile modulation and demodulation, as
well as voice sample formatting.
Configurations of the modem software are provided to
support modem models listed in Table 1.
Binary executable modem software is provided for the
OEM.
Data/Fax Modes
As a V.90/K56flex data modem, the modem can receive
data from a digital source using a V.90- or K56flex-
compatible central site modem over the digital telephone
network portion of the PSTN at line speeds up to 56 kbps.
Asymmetrical data transmission supports sending data up
to V.34 rates. This mode can fallback to full-duplex V.34
mode, and to slower rates as dictated by line conditions.
As a V.34 data modem, the modem can operate in 2-wire,
full-duplex, asynchronous modes at line rates up to 33.6
kbps. Data modem modes perform complete handshake
and data rate negotiations. Using V.34 modulation to
optimize modem configuration for line conditions, the
modem can connect at the highest data rate that the
channel can support from 33600 bps down to 2400 bps
with automatic fallback. Automode operation in V.34 is
provided in accordance with PN3320 and in V.32 bis in
accordance with PN2330. All tone and pattern detection
functions required by the applicable ITU or Bell standard
are supported.
In fax modem mode, the modem can operate in 2-wire,
half-duplex, synchronous modes and can support Group 3
facsimile send and receive speeds of 14400, 12000,
9600, 7200, 4800, or 2400 bps. Fax data transmission
and reception performed by the modem are controlled and
monitored through the fax EIA/IA-578 Class 1 and T.31
Class 1.0 command interface. Full HDLC formatting, zero
insertion/deletion, and CRC generation/checking are
provided.
Synchronous Access Mode (SAM) - Video
Conferencing
V.80 synchronous access mode between the modem and
the host/DTE is provided for host-controlled
communication protocols, e.g., H.324 video conferencing
applications.
Voice-call-first (VCF) before switching to a videophone
call is also supported.
Voice/TAM Mode
Voice/TAM Mode features include 8-bit
µ
-Law, A-Law, and
linear coding at 8000 Hz and 7200 Hz sample rates. Tone
detection/generation, call discrimination, and concurrent
DTMF detection are also supported. ADPCM coding is
also supported to meet Microsoft WHQL logo
requirements.
Voice/TAM Mode is supported by three submodes:
1.
Online Voice Command Mode supports connection to
the telephone line or, for SP models, a handset.
2.
Voice Receive Mode supports recording voice or
audio data input at the RIN pin, typically from the
telephone line or, for SP models, a
microphone/handset.
3.
Voice Transmit Mode supports playback of voice or
audio data to the TXA1/TXA2 output, typically to the
telephone line or, for SP models, a speaker/handset.
Speakerphone Mode (SP Models)
The SP model includes an additional telephone handset,
external microphone, and external speaker interface
which supports voice and full-duplex speakerphone
(FDSP) operation. The Speakerphone Mode features an
advanced proprietary speakerphone algorithm which
supports full-duplex voice conversation with acoustic, line,
and handset echo cancellation. Parameters are constantly
adjusted to maintain stability with automatic fallback from
full-duplex to pseudo-duplex operation. The
speakerphone algorithm allows position independent
placement of microphone and speaker.
The speakerphone mode provides hands-free full-duplex
telephone operation under host control. The host can
separately control volume, muting, and AGC in
microphone and speaker channels.
The speakerphone mode also supports Voice/TAM Mode
connection to a handset.
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Hardware Interface Signals
The major functional interface signals are shown in Figure
2.
Bus Interface and Codec (BIC) Interface
The BIC (R6793) 144-pin TQFP hardware interface
signals are shown in Figure 3.
The BIC (R6793) 144-pin TQFP pin assignments are
shown in Figure 4.
Bus Interface (BIF) Interface
The BIF (11235) 176-pin TQFP hardware interface signals
are shown in Figure 5.
The BIF (11235) 176-pin TQFP pin assignments are
shown in Figure 6.
Line/Voice Codec (LVC) Interface
The LVC (20410) 144-pin TQFP hardware interface
signals are shown in Figure 7.
The LVC (20410) 144-pin TQFP pin assignments are
shown in Figure 8.
Line Codec (LC) Interface
The LC (20437) 32-pin TQFP hardware interface signals
are shown in Figure 9.
The LC (20437) 32-pin TQFP pin assignments are shown
in Figure 10.
Package Dimensions
The package dimensions are shown in Figure 11 (176-pin
TQFP), Figure 12 (144-pin TQFP), and Figure 13 (32-pin
TQFP).
Electrical and Environmental Specifications
The current and power requirements are listed in Table 2.
The absolute maximum ratings are listed in Table 3.
Additional Information
Additional information is described in the SoftK56-PCI
Designer’s Guide (Order No. 1201) and in the Command
Reference Manual (Order No. 1163).
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MD232F1 R6793 MIS
PCI BUS
VDD
VDDpci
AVDD
AVAA
GND
AGND
CLKRUN#
VIO
PCICLK
PCIRESET#
FRAME#
IDSEL
DEVSEL#
IRDY#
TRDY#
PAR
REQ#
GNT#
INTA#
STOP#
PERR#
SERR#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
AD[31:0]
PME#
SROMCLK
SROMCS
SROMOUT
SROMIN
AUDIO
INTERFACE
DSPKOUT
SPKOUT*
MIC_V*
SPKMUTE (GPIO8)
XIN
XOUT
28.224 MHZ
CRYSTAL
CIRCUIT
+3.3V (VDD)
+3.3V (VDD)
+3.3V (VDD)
+3.3VA OR +5VA (VAA)
GND
AGND
RS56-PCI
SINGLE DEVICE MODEM
[R6793: 144-PIN TQFP]
OR
2-DEVICE MODEM
OF
BUS INTERFACE (BIF)
[11235: 176-PIN TQFP]
AND EITHER
LINE/VOICE CODEC (LVC)
[20410: 144-PIN TQFP]
OR
LINE CODEC (LC)
[20437: 32-PIN TQFP]
VpciEN##
VauxEN#
VpciDET
VauxDET
POWER
DETECTION
AND
SWITCHING
CIRCUIT
256 x 16
OR
128 X 16
SERIAL
EEPROM
GND THRU 1K
DAA AND
TELEPHONE
INTERFACE
OH# (GPIO0)
CID# (GPIO1)
VOICE# (GPIO2)
RINGWAKE# (INPUT0)
CID_DATA (INPUT1)
LCS# (INPUT2)
IRING# (INPUT3)
EXT_L# (INPUT4)
LCS_L#/RH_L# (INPUT5)
RXA
TXA1
TXA2
TELIN
TELOUT
* SP MODEL ONLY.
Figure 2. RS56-PCI Major Interface Signals
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+3.3V
EEPROMVCC
VI/O
VCC
VAUX
ANALOG_IA_POWER
AD7
AD15
AD19
IRING#
C/BE3#
AD25
INTA#
AD31
PCIRESET#
DRESET#
IRDY#
AD12
AD20
AD23
V_TXSIN
AD3
M_CLK
AD6
AD24
SERR#
AD10
IASLEEP
OH#
TRDY#
C/BE0#
M_TXSIN
TXA1
DEVSEL#
AD2
C/BE1#
AD22
RXA
TXA2
V_CTRL
RINGWAKE#
AD26
M_SCLK
V_SCLK
DRESET#
AD1
AD9
AD18
AD21
V_RXOUT
AD16
PAR
AD29
AD4
AD11
AD13
C/BE2#
AD28
AD30
AD17
PERR#
AD0
AD5
AD14
STOP#
M_RXOUT
FRAME#
IDSEL
M_CTRL
DSPKOUT
SROMIN
GNT#
V_STROBE
VC
PCICLK
AD8
AD27
REQ#
M_STROBE
VREF
PCIPME#
SROMCLK
SROMCS
SPEAKMUTE
SROMOUT
+
C31
10uF
C30
0.1uF
C28
0.1uF
L2
R15
1M
Y1
28.224MHz
C32
27pF
5%
C33
27pF
5%
+
C29
10uF
R16
0
R13
1k
R14
4.7k
IN1
INSULATOR
for Y1
R12
10K
D1
BAS16
U2
R6793
59
89
71
87
79
88
80
117
93
130
57
78
70
90
116
91
67
95
131
118
132
123
94
92
96
127
128
45
133
83
21
17
134
18
82
19
136
137
138
139
111
114
112
3
4
5
12
106
107
108
110
6
8
9
22
10
11
23
24
26
27
28
33
31
32
1
36
37
38
39
41
42
43
44
85
124
126
129
144
13
14
15
16
99
101
103
104
119
120
121
122
140
46
72
86
52
76
48
74
50
77
47
49
69
60
61
62
66
64
63
56
58
65
53
68
54
55
100
102
105
135
97
81
125
40
34
30
25
115
20
143
142
141
113
98
84 7
235
51
109
75
73
29
AVDD
V_RXOUT
VDD
V_TXSIN
VDD
V_SCLK
SET3V#
GPOH1/VpciEN
M_SCLK
AD31
AGNDV
AGND
AGND
V_STROBE
GPOH0/VauxEN
M_STROBE
AGNDM
M_CLK
AD30
GPOL1
AD29
INTA#
M_TXSIN
M_RXOUT
M_CTRL
GNT#
REQ#
GPOL0/DRESET#
AD28
SDXTAL1/XIN
PAR
STOP#
AD27
PERR#
SDXTAL2/XOUT
SERR#
AD26
AD25
AD24
CBE3#
INPUT4/EXT_L#
INPUT7/VauxDET
INPUT5/LCS_L#/RH_L#
AD23
AD22
AD21
CBE2#
INPUT0/RINGWAKE#
INPUT1
INPUT2/LCS#
INPUT3/IRING#
AD20
AD19
AD18
CBE1#
AD17
AD16
AD15
AD14
AD13
AD12
AD11
CBE0#
AD9
AD8
VIO1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PME#
PCIRST#
PCICLK
CLKRUN#
IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
RESETEN/GPIO14
GPIO3
CID#/GPIO1
OH#/GPIO0
SROMCS
SROMOUT
SROMIN
SROMCLK
VIO2
SLEEPO/GPIO15
MCTRLSIN
V_CTRL
VCTRLSIN
MRXOUT
VRXOUT
MTXSIN
VTXSIN
MSTROBE
VSTROBE
VSCK
DSPKOUT
SPKOUT
TXA1
TXA2
RXA
VC
VREF
TELIN
TELOUT
MIC_V
IASLEEP
RESET#
AGND
AGND
GPIO8
VOICE#/GPIO2
VDD
VDD
VDD
VDD
VpciDET
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND VDD
VDDGND
VCLKIN
NC
MSCK
MCLKIN
AD10
R10
1k
U3
93LC46B/SN
8
6
4
2
7
1
3
5
VDD
PE
DO
SK
PRE
CS
DI
GND
AD[0..31]
REQ#
STOP#
INTA#
OH#
C/BE3#
PERR#
TXA2
TXA1
IRING#
C/BE2#
DEVSEL#
IDSEL
C/BE0#
PAR
IRDY#
RXA
PCICLK
GNT#
DSPKOUT
RINGWAKE#
SERR#
FRAME#
TRDY#
PCIRESET#
C/BE1#
PCIPME#
SPKOUT
MIC_V
SPEAKMUTE
Ferrite
For Layout: Place Vref and VC
Components near U7 (R6793)
R16 Not Installed = +5V IA Operation
R16 Installed = +3.3V IA Operation
Figure 3. Bus Interface/Codec (BIC) (R6793: 144-Pin TQFP) Hardware Interface Signals
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
LCS# (INPUT2)
CID_DATA (INPUT1)
RINGWAKE# (INPUT0)
VDD
OH# (GPIO0)
CID# (GPIO1)
VOICE# (GPIO2)
GPIO3
SPKMUTE (GPIO8)
GPIO14
GND
VDD
M_CTRL
M_CLK
M_TXSIN
M_SCLK
M_RXOUT
M_STROBE
V_STROBE
V_RXOUT
V_SCLK
V_TXSIN
V_CTRL
PME#
GND
XIN
XOUT
VDD
SET3V#
VDD
AGND
MSTROBE
MRXOUT
MSCLK
MTXSIN
MCLKIN
VIO1
VDD
AD23
AD22
AD21
AD20
VDD
AD19
AD18
AD17
AD16
CBE2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
VDD
PAR
CBE1#
AD15
AD14
VDD
AD13
AD12
AD11
AD10
VDD
AD9
AD8
CBE0#
VDD
GND
AD7
AD6
AD5
AD4
VDD
AD3
AD2
AD1
AD0
DRESET# (GPOL0)
SLEEPO (GPIO15)
VSTROBE/NC*
VRXOUT/NC*
VSCLK/NC*
VTXSIN/NC*
VCLKIN/NC*
VCTRLSIN/NC*
IASLEEP
AGND
AGND
TELIN/NC*
AGNDV/NC*
TELOUT/NC*
AVDD
SPKOUT
TXA1
TXA2
VREF
VC
MIC_V/NC*
RXA
AGNDM
RESET#
DSPKOUT
AGND
VDD
MCTRLSIN
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
MD231F4 PO-R6793-144T
IDSEL
GND
GND
GND
VIO2
CBE3#
AD24
AD25
AD26
VDD
AD27
AD28
AD29
AD30
AD31
CLKRUN#
REQ#
GNT#
PCICLK
VpciDET
PCIRST#
INTA#
SROMCLK
SROMIN
SROMOUT
SROMCS
GPOL1
VpciEN#
VauxEN#
VDD
VauxDET
GND
LCS_L#/RH_L# (INPUT 5)
EXT_L# (INPUT4)
IRING# (INPUT3)
NC
* PIN IS NC ON R6793-12 ONLY (RS56-PCI)
Figure 4. BIC (R6793: 144-Pin TQFP) Pin Signals
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MD231F5 11235 HIS-176T
PCI BUS INTERFACE
176-TQFP
[11235]
XIN
XOUT
PCICLK
FRAME#
IDSEL
DEVSEL#
IRDY#
TRDY#
CBE0#
CBE1#
CBE2#
CBE3#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PAR
REQ#
GNT#
INTA#
STOP#
PERR#
SERR#
PME#
PCIRST#
VIO
VIO
VauxEN#
VauxDET
VpciEN#
VpciDET
SROMOUT
SROMIN
SROMCLK
SROMCS
RESERVED
RESERVED
NC
NC
NC
GPOL1
INPUT6
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
MSWRES
SCANENB
SCANMODE
CLKRUN#
CARDBUS#
132
131
27
62
46
66
63
64
86
73
61
43
98
97
96
95
92
91
90
89
85
84
81
80
79
78
75
74
59
58
57
56
53
52
51
50
42
41
40
37
36
35
34
32
72
30
29
24
67
68
69
134
25
44
47
6
3
7
26
11
12
13
10
19
20
21
22
23
8
2
134
153
154
155
156
157
160
161
162
163
164
137
45
151
31
9
SPKMUTE (GPIO8)
OH# (GPIO0)
CID# (GPIO1)
VOICE# (GPIO2)
RINGWAKE# (INPUT0)
CID_DATA (INPUT1)
LCS# (INPUT2)
IRING# (INPUT3)
EXT_L# (INPUT4)
LCS_L#/RH_L# (INPUT5)
M_CS#
M_IRQ
M_TXCLK
M_TX
M_RXCLK
M_RX
SI_FRAME (SR8FRM)
SI_CLK (SR8CLK)
SI_DD (SR8DD)
SI_DU (SR8UD)
OSC_OUT
SLEEPO (GPIO15)
DA0
DA1
DA2
DA3
DA4
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DRD#
DWR#
DRESET#
ISDN_CS#
ISDN_INT
VOICE_CS#
VOICE_IRQ
M_CLK
M_SCLK
M_STROBE
M_TXSIN
M_RXOUT
M_CTRL
V_SCLK
V_STROBE
V_TXSIN
V_RXOUT
V_CTRL
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
158
167
166
165
170
171
172
173
174
175
113
135
106
105
108
136
103
102
100
101
130
107
118
117
116
115
114
128
127
126
125
124
123
122
121
111
112
104
16
17
14
15
147
146
139
148
138
145
140
143
142
144
141
5
38
49
55
70
76
88
94
110
119
149
168
83
1
133
4
18
176
28
33
39
48
54
60
65
71
77
82
87
93
99
109
120
129
150
159
169
PCI
BUS
EEPROM
GND
LVC
(OPTIONAL,
FOR HC56HCF-PCI
DESIGN COMPATIBILITY)
DAA
LVC
(OPTIONAL,
FOR HC56HCF-PCI
DESIGN COMPATIBILITY)
VCC (+3.3 V)
NC
VDD
27pF
5%
28.224 MHz
1M
27pF
5%
POWER DETECTION AND
SWITCHING CIRCUIT
LVC OR LC: MCLKIN & LVC: VCLKIN
LVC OR LC: MSCLK
LVC OR LC: MSTROBE
LVC OR LC:MTXSIN
LVC OR LC: MRXOUT
LVC OR LC: MCTRLSIN
LVC: VSCLK
LVC: VSTROBE
LVC: VTXSIN
LVC: VRXOUT
LVC: VCTRLSIN
LC: IASLEEP
AUDIO CIRCUIT
NC
Figure 5. Bus Interface (BIF) (11235: 176-Pin TQFP) Hardware Interface Signals
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
1
29
128
127
126
125
1
24
123
122
121
120
119
118
1
17
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
XIN
XOUT
OSC_OUT*
GND
DD0*
DD1*
DD2*
DD3*
DD4*
DD5*
DD6*
DD7*
GND
VDD
DA0*
DA1*
DA2*
DA3*
DA4*
M_CS#*
DWR#
DRD#
VDD
GND
M_RXCLK*
SLEEPO (GPIO15)
M_TXCLK*
M_TX*
DRESET# (GPOL0)
SI_FRAME (SR8FRM)
SI_CLK (SR8CLK)
SI_DU (SR8UD)
SI_DD (SR8DD)
GND
AD0
AD1
AD2
AD3
VDD
GND
AD4
AD5
AD6
AD7
VDD
INPUT6
VauxDET
GND
VDD
VauxEN#
VpciEN#
GPOL1
CARDBUS#
SROMCS
SROMOUT
SROMIN
SROMCLK
VOICE_CS#
VOICE_IRQ
ISDN_CS#
ISDN_INT
GND
RESERVED
RESERVED
NC
NC
NC
INTA#
PCIRST#
VpciDET
PCICLK
GND
GNT#
REQ#
CLKRUN#
AD31
GND
AD30
AD29
AD28
AD27
VDD
GND
AD26
AD25
AD24
CBE3#
VIO1
SCANENB
IDSEL
VIO2
GND
VDD
AD23
AD22
AD21
AD20
GND
VDD
AD19
AD18
AD17
AD16
GND
CBE2#
FRAME#
IRDY#
TRDY#
GND
DEVSEL#
STOP#
PERR#
SERR#
VDD
GND
PAR
CBE1#
AD15
AD14
VDD
GND
AD13
AD12
AD11
AD10
GND
VDD
AD9
AD8
CBE0#
GND
VDD
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
MD231F6-11235 PO-176TQFP
GND
LCS_L#/RH_L# (INPUT5)
EXT_L# (INPUT4)
IRING# (INPUT3)
LCS# (INPUT2)
CID_DATA (INPUT1)
RINGWAKE# (INPUT0)
GND
VDD
OH# (GPIO0)
CID# (GPIO1)
VOICE# (GPIO2)
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GND
SPKMUTE (GPIO8)
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
SCANMODE
GND
VDD
M_CTRL
M_CLK
M_TXSIN
M_SCLK
M_RXOUT
M_STROBE
V_STROBE
V_RXOUT
V_SCLK
V_TXSIN
V_CTRL
MSWRES
M_RX*
M_IRQ*
PME#
VDD
* SIGNAL NOT SUPPORTED BY SOFTK56 MODEM. CONNECT PIN AS DESCRIBED FOR
FOR RH56-PCI (RC56HCF-PCI) PIN-COMPATIBLE DESIGNS.
Figure 6. BIF (11235: 176-Pin TQFP) Pin Signals
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MD231F7 LVC_HIS
LINE/
VOICE
CODEC
(LVC)
144-TQFP
[20410]
NC (CLKIN)
NC (XTLI)
NC (XTLO)
NC (CS#)
GND (IRQ)
NC (RS0)
NC (RS1)
NC (RS2)
NC (RS3)
NC (RS4)
NC (D0)
NC (D1)
NC (D2)
NC (D3)
NC (D4)
NC (D5)
NC (D6)
NC (D7)
NC (READ#)
NC (WRITE#)
RESET2#
NC (RESET1#)
NC (SI_CLK)
NC (SI_FRAME)
GND (SI_DD)
NC (SI_DU)
NC (M_TX)
GND (M_TXCLK)
GND (M_RX)
GND (M_RXCLK)
NC (GP00)
NC (WKRES#)
NC (VDD)
NC (VDD)
NC (VDD)
NC (VDD)
AVDD
AVDD
NC (PB4)
NC (DAA/CELL)
NC (VGG)
AVAA
GND
GND
GND
GND
GND
GND
NC (NOXTL)
VSUB
AGND
AGND
AGND
AGNDV
AGNDM
AGND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
140
141
143
67
130
11
12
64
65
66
144
1
3
4
6
8
9
10
69
68
32
86
98
97
100
99
77
76
111
71
134
72
79
107
137
138
50
37
129
112
117
23
52
60
84
109
121
132
115
51
14
18
19
21
31
49
15
16
17
41
70
81
83
105
142
114
101
102
110
116
118
119
120
126
131
135
136
NC (CELL_BUSY)
NC (CELL_CLOCK)
NC (CELL_DATA)
TELIN
TELOUT
RXA
TXA1
TXA2
VC
VREF
NC (PLLVDD)
NC (PLLGND)
SPKMD
SPKROUT_M
MIC_M
MIC_V
MCLKIN
MTXSIN
MRXOUT
MSTROBE
MSCLK
MCTRLSIN
NC (SR1IO)
NC (IA1CLK)
NC (SA1CLK)
NC (SR4IN)
NC (SR4OUT)
NC (CLKOUT)
NC (SR3OUT)
NC (SR3IN)
NC (SA2CLK)
NC (SR2CLK)
NC (SR2IO)
VCTRLSIN
VSCLK
VSTROBE
VRXOUT
VTXSIN
VCLKIN
NC (SLEEPO)
IASLEEP
NC (IOM_FRAME)
NC (IOM_CLK)
INC (OM_DD)
NC (IOM_DU)
NC (MK5)
NC (MK4)
SET3V#
NC (GP01)
NC (GP11)
NC (GP14)
NC (PE1)
NC (PF6)
NC (PF7)
NC (YCLK)
NC (XCLK)
NC (SYCLK)
NC (TIRO2)
MICBIAS
MRLYA#
MRLYB#
VRLYA#
VRLYB#
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
128
127
78
20
22
30
25
26
28
27
13
61
36
24
33
29
43
44
46
47
45
42
106
94
93
89
87
91
88
90
103
73
104
58
55
53
54
56
57
113
59
95
96
62
124
85
133
40
108
5
2
125
82
63
122
123
7
74
34
48
35
38
39
139
92
75
80
BIF
+3.3V
GND
NC
DAA
NC
NC
VAA [+5V (RECOMMENDED)
OR +3.3V]
AGND
BIF: OSC_OUT
BIF: M_CS#
BIF: M_IRQ
BIF: DA0
BIF: DA1
BIF: DA2
BIF: DA3
BIF: DA4
BIF: DD0
BIF: DD1
BIF: DD2
BIF: DD3
BIF: DD4
BIF: DD5
BIF: DD6
BIF: DD7
BIF: DRD#
BIF: DWR#
BIF: DRESET#
BIF: SI_CLK
BIF: SI_FRAME
BIF: SI_DD
BIF: SI_DU
BIF: M_TX
BIF: M_TXCLK
BIF: M_RX
BIF: M_RXCLK
AUDIO CIRCUIT
NC
NC
NC (VAA = +5V) OR
AGND (VAA = +3.3V)
33
0.1
10
10
0.1 CER
0.1 CER
FB
VAA
NC
GND
SI_CLK (PIN 98)
BIF: M_CLK
BIF: M_TXSIN
BIF: M_RXOUT
BIF: M_STROBE
BIF: M_SCLK
BIF: M_CTRL
BIF: V_CRTL
BIF: V_SCLK
BIF: V_STROBE
BIF: V_RXOUT
BIF: V_TXSIN
MCLKIN (PIN 43)
NC
BIF: SLEEP
NOTES:
1. CORRESPONDING RC56HCF-PCI PIN SIGNALS
ARE SHOWN IN PARENTHESIS.
2. CONNECTIVITY SHOWN FOR INSTALLING 20410
DEVICE INTO AN RC56HCF-PCI DESIGN. ALL NC
PINS CAN BE LEFT OPEN.
3. PINS 71, 76, 100, 111, AND 130 CAN BE LEFT
OPEN OR CONNECTED TO DGND.
Figure 7. Line/Voice Codec (LVC) (20410: 144-Pin TQFP) Hardware Interface Signals
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NC (GP01)
NC (VDD)
NC (SR1IO)
NC
NC (SR2IO)
NC (SA2CLK)
NC (RESERVED)
NC (RESERVED)
GND (SI_DD)
NC (SI_DU)
NC (SI_CLK)
NC (SI_FRAME)
NC (IOM_CLK)
NC (IOM_FRAME)
NC (IA1CLK)
NC (SA1CLK)
NC (RESERVED
NC (CLKOUT)
NC (SR3IN)
NC (SR4IN)
NC (SR3OUT)
NC (SR4OUT)
NC (RESET1#)
NC (MK5)
GND
NC
NC (PF6)
NC
NC (RESERVED)
NC (VDD)
NC (CELL_DATA)
NC (M_TX)
GND (M_TXCLK)
NC (RESERVED)
NC (TIRO2)
NC (SR2CLK)
NC (D1)
NC (GP14)
NC (D2)
NC (D3)
NC (GP11)
NC (D4)
NC (SYCLK)
NC (D5)
NC (D6)
NC (D7)
NC (RS0)
NC (RS1)
NC (PLLVDD)
AGND
NC
NC
NC
AGND
AGND
TELIN
AGNDV
TELOUT
AVAA
SPKROUT_M
TXA1
TXA2
VREF
VC
MIC_V
RXA
AGNDM
RESET2#
MIC_M
MICBIAS
MRLYB#
SPKMD
AVDD
VRLYA#
VRLYB#
SET3V#
NC
MCTRLSIN
MCLKIN
MTXSIN
MSCLK
MRXOUT
MSTROBE
MRLYA#
AGND
AVDD
VSUB
GND
VSTROBE
VRXOUT
VSCLK
VTXSIN
VCLKIN
VCTRLSIN
IASLEEP
GND
NC (PLLGND)
NC (IOM_DD)
NC (PF7)
NC (RS2)
NC (RS3)
NC (RS4)
NC (CS#)
NC (WRITE#)
NC (READ#)
NC
GND (M_RXCLK)
NC (WKRES#)
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
MD231F8 20410PO-144T
NC (D0)
NC (XTLO)
NC
NC (XTLI)
NC (CLKIN)
NC (RESERVED)
NC (VDD)
NC (VDD)
NC (RESERVED
NC (RESERVED
NC (GP00)
NC (MK4)
GND
NC (RESERVED)
GND (IRQ)
NC (PB4)
NC (CELL_BUSY)
NC (CELL_CLOCK)
NC (RESERVED)
NC (PE1)
NC (IOM_DU)
NC (XCLK)
NC (YCLK)
NC (GND)
NC (RESERVED)
NC (RESERVED)
NC (RESERVED)
NC (VGG)
NC (RESERVED)
NC (NOXTL)
NC
NC (SLEEPO)
NC (DAA/CEL)
GND (M_RX)
NC (RESERVED)
GND
NOTE: SIGNALS IN PARENTHESES SHOW CORRESPONDING RC56HCF-PCI
SIGNALS IF DIFFERENT FROM SOFTK56-PCI SIGNALS.
Figure 8. LVC (20410: 144-Pin TQFP) Pin Signals
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MD231F9 20437-HIS
LINE
CODEC
(LC)
32-TQFP
[20437]
MCLKIN
MTXSIN
MRXOUT
MSTROBE
MSCLK
MCTRLSIN
IASLEEP
RESET#
SET3V#
AVDD
AVDD
AVAA
GND
VSUB
AGND
19
20
22
23
21
18
1
4
26
17
25
5
28
27
6
SPKMD
SPKOUT
MIC_M
RXA
TXA1
TXA2
VC
VREF
MICBIAS
MRLYA#
MRLYB#
M_ACT90
M_1BIT_OUT
D_LPBK#
NC
NC
NC
2
3
14
13
9
10
12
11
15
24
16
29
30
31
7
8
32
BIF
DAA
BIF: M_CLK
BIF: M_TXSIN
BIF: M_RXOUT
BIF: M_STROBE
BIF: M_SCLK
BIF: M_CTRL
BIF: SLEEP
BIF: DRESET#
NC (VAA = +5V) OR
AGND (VAA = +3.3V)
+3.3V
+3.3V
VAA [+5V (RECOMMENDED)
OR +3.3V]
GND
AGND
AGND
AUDIO CIRCUIT
10
10
0.1 CER
0.1 CER
FB
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 9. Line Codec (LC) (20437: 32-Pin TQFP) Hardware Interface Signals
MD231F10 20437 PO-32T
NC
D_LPBK#
M_1BIT_OUT
M_ACT90
GND
VSUB
SET3V#
AVDD
IASLEEP
SPKMD
SPKOUT
RESET#
AVAA
AGND
NC
NC
TXA1
TXA2
VREF
VC
RXA
MIC_M
MICBIAS
MRLYB#
MRLYA#
MSTROBE
MRXOUT
MSCLK
MTXSIN
MCLKIN
MCTRLSIN
AVDD
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
Figure 10. LC (20437: 32-Pin TQFP) Pin Signals
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Figure 11. Package Dimensions - 176-Pin TQFP
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e
b
D
DETAIL A
DETAIL A
A1
L1
c
L
A
D2
D1
D1
A2
Millimeters
0.05
21.75
0.5
0.17
0.11
1.6 MAX
0.15
1.4 REF
22.25
20.0 REF
17.5 REF
0.75
1.0 REF
0.50 BSC
0.27
0.17
0.08 MAX
0.0020
0.8563
0.0197
0.0067
0.0043
A
A1
A2
D
D1
D2
L
L1
e
b
c
Coplanarity
Min.
Max.
Min.
Max.
Inches*
Dim.
Ref: 144-PIN TQFP (GP00-D252)
* Metric values (millimeters) should be used for
PCB layout. English values (inches) are
converted from metric values and may include
round-off errors.
0.0630 MAX
0.0059
0.0551 REF
0.8760
0.7874 REF
0.6890 REF
0.0295
0.0394 REF
0.0197 BSC
0.0106
0.0067
0.0031 MAX
PD-TQFP-144 (040395)
D1
D
D2
D1
PIN 1
REF
Figure 12. Package Dimensions - 144-Pin TQFP
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DETAIL A
A1
L1
c
L
A
D1
A2
Millimeters
0.05
8.75
0.5
0.30
0.13
1.6 MAX
0.15
1.4 REF
9.25
7.0 REF
5.6 REF
0.75
1.0 REF
0.80 BSC
0.40
0.19
0.10 MAX
0.0020
0.3445
0.0197
0.0118
0.0051
A
A1
A2
D
D1
D2
L
L1
e
b
c
Coplanarity
Min.
Max.
Min.
Max.
Inches*
Dim.
Ref: 32-PIN TQFP (GP00-D262)
* Metric values (millimeters) should be used for
PCB layout. English values (inches) are
converted from metric values and may include
round-off errors.
0.0630 MAX
0.0059
0.0551 REF
0.3642
0.2756 REF
0.2205 REF
0.0295
0.0394 REF
0.0315 BSC
0.0157
0.0075
0.004 MAX
PD-TQFP-32 (040395)
DETAIL A
D1
e
b
D
D2
D1
D1
D
D2
PIN 1
REF
Figure 13. Package Dimensions - 32-Pin TQFP
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Table 2. Current and Power Requirements
Conditions Current Power
Device State (Dx)
and Bus State (Bx)
PCI Bus
Power
PCI Clock
(PCICLK)
Line
Connection
Typical
Current (mA)
Maximum
Current (mA)
Typical
Power (mW)
Maximum
Power (mW)
Single Device (R6793-12 BIC) and 2-Device Set (11235-14 BIF and 20437-11 LC)
D0, B0 On Running Yes 33 36 109 130
D0, B0 On Running No 22 24 73 86
D3, B0 On Running No 22 24 73 86
D3, B1 On Running No 22 24 73 86
D3, B2, B3 (D3 hot) On Stopped No 2.1 3.2 6.9 11.5
D3, B3 (D3 cold) Off Stopped No <1 1 <3.3 3.6
Single Device (R6793-11 BIC) and 2-Device Set (11235-14 BIF and 20410-11 LVC)
D0, B0 On Running Yes 33 36 109 130
D0, B0 On Running No 22 24 73 86
D3, B0 On Running No 22 24 73 86
D3, B1 On Running No 22 24 73 86
D3, B2, B3 (D3 hot) On Stopped No 2.1 3.2 6.9 11.5
D3, B3 (D3 cold) Off Stopped No <1 1 <3.3 3.6
Notes:
Operating voltage: VDD = +3.3V ± 0.3V.
Test conditions: VDD = +3.3 VDC for typical values; VDD = +3.6 VDC for maximum values.
For all modes, +3.3V is supplied to BIF and LVC and LC.
Definitions:
PCI Bus Power On: PCI Bus +5V and +3.3V on (modem normally powered by +3.3V from PCI Bus +3.3V
or regulated down from PCI Bus +5V); PCI RST# not asserted.
Off: PCI Bus +5V and +3.3V off (modem normally powered by +3.3V from Vaux or Vpci); PCI RST# asserted.
PCI Clock (PCICLK) Running: PCI Bus signal PCICLK running;
Stopped: PCI Bus signal PCICLK stopped (off).
Line connection: Yes: Off-hook, IA powered.
No: On-hook, IA powered down.
Device States: D3: Low power state. Suspend state can change the system power state; the resulting power state depends
on the system architecture (OS, BIOS, hardware) and system configuration (i.e., other PCI installed cards).
D0: Full power state.
Device and Bus States: D0, B0: Any PCI transaction, PCICLK running, VCC present.
D3, B1: No PCI Bus transactions, PCICLK running, VCC present.
D3, B2, B3: No PCI transactions, PCICLK stopped, VCC may be present.
D3, B3: No PCI transactions, PCICLK stopped, no VCC.
Refer to the PCI Bus Power Management Interface Specification for additional information.
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Table 3. Absolute Maximum Ratings
Parameter Symbol Limits Units
Supply Voltage V
DD
-0.5 to +4.0 V
Input Voltage V
IN
-0.5 to (VDD +0.5) (BIF)
-0.5 to (VGG +0.5)* (LVC)
V
Operating Temperature Range T
A
-0 to +70 °C
Storage Temperature Range T
STG
-55 to +125 °C
Analog Inputs V
IN
-0.3 to (VAA + 0.5) V
Voltage Applied to Outputs in High Impedance (Off) State V
HZ
-0.5 to (VDD +0.5) (BIF)
-0.5 to (VGG +0.5)* (LVC)
V
DC Input Clamp Current I
IK
±20 mA
DC Output Clamp Current I
OK
±20 mA
Static Discharge Voltage (25°C) V
ESD
±2500 V
Latch-up Current (25°C) I
TRIG
±400 mA
* VGG = 5.0V ± 0.25V or +3.3V ± 0.3V.
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NOTES
Information provided by Rockwell International Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Rockwell International for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent rights of Rockwell International other than for circuitry embodied in Rockwell products.
Rockwell International reserves the right to change circuitry at any time without notice. This document is subject to change without notice.
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