X6DHR-X8G

Supermicro X6DHR-X8G, X6DHR-XiG Supplementary Manual

  • Hello! I am an AI chatbot trained to assist you with the Supermicro X6DHR-X8G Supplementary Manual. I’ve already reviewed the document and can help you find the information you need or explain it in simple terms. Just ask your questions, and providing more details will help me assist you more effectively!
Attention!!
Important Information!!
(Read the information listed below before using this product.)
1. For the X6DHR-X8G/XiG boards:
Jumpers J4F4/J4F5 (PLLSEL Select): These jumpers allow the user to select PLLSEL (Memory Speed). Make sure
that the jumper settings are set correctly according to your memory speed before you power on the system.
(*Warning!! If these jumpers are not set correctly according to your memory speed, video display failure may
occur!!!)
DDR
*333 MHz
266MHz
J4F4 J4F5
Closed Closed
Open Open
PLLSEL Select
Jumper Settings
(J4F4/J4F5)
(*Default:Closed-333MHz)
J1D1 (12V 8-pin PWR) and J38 (12 V 4-pin PWR): Make sure that both PWR Connectors are used to ensure
adequate power supply to the system and the CPU.
(*Notes: 1. The default setting is “Closed” for both
jumpers to enable DDR Memory at 333MHz. However, if
your memory speed is 266MHz, please make sure to set
both jumpers to “Open”. If Reg. ECC DDR 333 ((-PC2700))
memory modules are used, 4 pieces of double banked
memory and 6 pieces of single banked memory are sup-
ported.)
Add-X6DHR-8G-07/30/04
KB
DIMM 4B
Mouse
USB
0/1
J14
COM1
DIMM 4A
DIMM 3B
DIMM 3A
DIMM 2B
DIMM 2A
DIMM 1B
DIMM 1A
GLAN1
GLAN2
VGA
SCSI Ch B
Battery
JPG1(VGA Enable)
JPL1(LAN Enable)
RAGE-
X
GLAN
CTRL
PXH
PXH
PCI-X
PCI-X
E7520
(North Bridge)
ICH5R
(South
Bridge)
ZCR
IPMI 2.0
BIOS
S I/O
7902
SCSI
CTRL
IDE #1
IDE #2
Floppy
SCSI Ch A
WOL
C
O
M
2
Fan3
SCSI
Enable
FPUSB0/1
JD2
JP9
CLR CMOS
Force PW-On
WOR
SPK
SW
SCSI
Ter. A
JPA1
JBT1
S
M
B
FAN5
SATA1
SATA0
F
P
C
T
R
L
J
F
1
FAN2
FAN1
20-PinPW
8-Pin
CPU
4-Pin
PW
PW SMB
PW
LED
CH
Int
JL1JWD
WD
CPU1
CPU2
JP11
Alarm
SW
JPA3
JPA2
SC
SI Ter. B
OH
J33
J34
J16
LG
5
J14
JD1
JA1
J5
J6
J12
FAN
4
Firmware
Hub
J1B1
J1D1
J38
J32
J
4
F
4
J
4
F
5
M
e
m
o
ry
S
p
e
e
d
(*N
o
te
:4
)
J
1
1
PW
Fail
JP10
SPKR
J4F4/J4F5
/