Elan Microelectronics EM60000 series User manual

EM60000

Series

8-Bit

Micro-Controller Based

Sound Processor

USER’S MANUAL

ELAN MICROELECTRONICS CORP.

March 2003

Doc. Version 2.0

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IBM is a registered trademark and PS/2 is a trademark of IBM.

Windows is a trademark of Microsoft Corporation.

EASY SOUND is a registered trademark of ELAN Microelectronics Corp.

ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.

Printed in Taiwan, ROC

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Such information and material may change to conform to each confirmed order.

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ELAN MICROELECTRONICS CORPORATION

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Group

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USA

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Shenzhen, Ltd.

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Shanghai Corporation, Ltd.

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Zhangjiang Hi-Tech Park

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Tel: +86 021 5080-3866

Fax: +86 021 5080-4600

Contents

EM60000 Series User’s Manual Contents • iii

Contents

1 Introduction 1

1.1 General Description....................................................................................................1

1.2 Features.......................................................................................................................1

1.3 Block Diagram............................................................................................................2

1.4 Parts List .....................................................................................................................2

1.5 Pin Assignments..........................................................................................................3

1.6 Specifications..............................................................................................................3

1.6.1 Absolute Maximum Ratings...........................................................................3

1.6.2 Electrical Characteristics (Temperature: 0°C to 50°C, VSS=0V) ..................4

1.6.3 Internal Oscillator Frequency .........................................................................4

2 Architecture 5

2.1 Architectural Overview...............................................................................................5

2.1.1 Overview.........................................................................................................5

2.1.2 Functional Block Diagram..............................................................................6

2.1.3 Hardware Summary........................................................................................7

2.2 Arithmetic Logic Unit (ALU).....................................................................................7

2.2.1 ALU Instruction Summary .............................................................................8

2.2.1.1 Boolean Instruction:......................................................................8

2.2.1.2 Arithmetic Instruction:..................................................................8

2.2.1.3 Bit Manipulated Instruction:.........................................................9

2.2.1.4 Data Move Instruction:.................................................................9

2.2.2 ALU Related Status Flags...............................................................................9

2.3 Hardware Multiplier..................................................................................................10

2.4 Memory Organization...............................................................................................11

2.4.1 Data Memory................................................................................................11

2.4.2 Program Memory..........................................................................................13

2.4.3 Address Mode...............................................................................................14

2.4.4 Voice ROM ...................................................................................................15

Contents

iv • Contents EM60000 Series User’s Manual

3 System Control 17

3.1 Intoduction................................................................................................................17

3.2 System Control Registers..........................................................................................17

3.2.1 R3 (Status Flag Register).................................................................................18

3.2.2 R4 (RAM Select Register)...............................................................................18

3.2.3 R5 (Interrupt Control Register)........................................................................19

3.2.4 R8 (Port & WDT Control Register).................................................................20

3.2.5 R9 (Bank Select for Special Function) ............................................................21

3.3 I/O Mapped Control Registers..................................................................................22

3.3.1 IOC5 (Prescaler Control Register)...................................................................22

3.4 Program Counter and Stack ......................................................................................24

3.5 Interrupts...................................................................................................................24

3.5.1 TCC Timer Interrupt........................................................................................25

3.5.2 MTC Timer Interrupt ......................................................................................25

3.5.3 Speech Timer Interrupt ....................................................................................25

3.6 Reset..........................................................................................................................26

3.7 Sleep Mode and Wake Up.........................................................................................27

3.7.1 WDT Wake-Up ................................................................................................27

3.7.2 Input Port Wake-Up .........................................................................................27

3.8 Timer Control............................................................................................................27

3.8.1 TCC Timer.......................................................................................................28

3.8.2 MTC Timer ......................................................................................................28

3.8.3 Speech Timer ...................................................................................................29

3.8.4 Watchdog Timers .............................................................................................29

3.9 I/O Port Control ........................................................................................................30

3.9.1 Port 1................................................................................................................31

3.9.2 Port 2................................................................................................................31

3.9.3 Port 3................................................................................................................32

3.9.4 Port 4................................................................................................................33

3.9.5 Port 5................................................................................................................34

Contents

EM60000 Series User’s Manual Contents • v

4 Special Function Control 35

4.1 Introduction...............................................................................................................35

4.2 Speech Function Control ..........................................................................................36

4.2.1 RA (MODE Register) ...................................................................................37

4.2.2 IOC6, 7, 8 (Address Registers).....................................................................38

4.2.3 IOC9 (ROM Data Input Registers)...............................................................38

4.2.4 IOCA (Sampling Rate Register) ...................................................................39

4.2.5 IOCB, IOCC (DAC Output Registers) .........................................................40

4.3 Melody Function Control..........................................................................................40

4.3.1 RA (MODE Register) ...................................................................................41

4.3.2 IOC6, 7, 8 (Address Registers).....................................................................41

4.3.3 IOCA (Envelope Register)............................................................................42

4.3.4 IOCB & IOCC (Frequency Registers)..........................................................42

4.4 Voice ROM Access Control......................................................................................42

4.4.1 IOC6, 7, 8 (Address Registers).....................................................................43

4.4.2 IOC9 (ROM Data Input Registers)...............................................................43

4.5 DAC Function Control..............................................................................................43

4.5.1 RA (MODE Registers)..................................................................................44

4.5.2 IOC6 (Selector Registers).............................................................................45

5 Instruction Set 47

5.1 Introduction...............................................................................................................47

5.2 Instruction Summary.................................................................................................48

5.3 Instruction Description..............................................................................................50

5.3.1 ADD – Addition............................................................................................50

5.3.2 AND – And Operation..................................................................................51

5.3.3 BC – Bit Clear...............................................................................................52

5.3.4 BS – Bit Set...................................................................................................52

5.3.5 CALL – Subroutine Call...............................................................................52

5.3.6 CLR – Clear Register....................................................................................53

5.3.7 COM – Complement R.................................................................................53

5.3.8 COMA – Complement R and Place in Acc...................................................53

5.3.9 DAA – Decimal Adjust.................................................................................54

5.3.10 DEC – Decrement R ....................................................................................54

Contents

vi • Contents EM60000 Series User’s Manual

5.3.11 DECA – Decrement R and Place in Acc......................................................55

5.3.12 DJZ – Decrement R (Skip if Result is Zero)................................................55

5.3.13 DJZA – Decrement R and Place in Acc (Skip if Result is Zero).....................56

5.3.14 GET – Get n-Bit Width Data from the Voice ROM and Store in Acc ........56

5.3.15 INC – Increment R.......................................................................................57

5.3.16 INCA – Increment R and Place in Acc ........................................................57

5.3.17 IOR – Move IOCR to the Acc......................................................................57

5.3.18 IOW – Move Acc to IOCR ..........................................................................58

5.3.19 JBC – Bit Test (Skip if Clear)......................................................................58

5.3.20 JBS – Bit Test (Skip if Set)..........................................................................58

5.3.21 JMP – Unconditional Branch.......................................................................59

5.3.22 JZ – Increment R (Skip if result is zero)......................................................59

5.3.23 JZA – Increment R and Place in Acc (Skip if result is zero) .......................60

5.3.24 MOV – Move Data ......................................................................................60

5.3.25 MPY – Multiply...........................................................................................61

5.3.26 NOP – No Operation....................................................................................62

5.3.27 OR – Inclusive OR.......................................................................................62

5.3.28 PAGE – Set Page Bits..................................................................................63

5.3.29 RET – Return from Subroutine....................................................................64

5.3.30 RETI – Return from Interrupt......................................................................64

5.3.31 RETL – Return Immediate Data to the A Register ......................................65

5.3.32 RETS – Return from Speech Subroutine.....................................................66

5.3.33 RLC – Rotate Left Through Carry...............................................................66

5.3.34 RLCA – Rotate Left through Carry and Place in Acc..................................67

5.3.35 RRC – Rotate Right through Carry..............................................................67

5.3.36 RRCA – Rotate Right through Carry and Place in Acc...............................68

5.3.37 SLEP – Sleep ...............................................................................................68

5.3.38 SUB – Subtract ............................................................................................68

5.3.39 SWAP – Swap High/Low Nibble.................................................................69

5.3.40 SWAPA – Swap High/Low Nibble and Place in Acc...................................70

5.3.41 WDTC – Clear Watchdog Timer .................................................................70

5.3.42 XOR – Exclusive OR...................................................................................70

Contents

EM60000 Series User’s Manual Contents • vii

6 Software Application 73

6.1 Introduction...............................................................................................................73

6.2 Program Initialization ...............................................................................................73

6.2.1 Example – Power-on Initialization ...............................................................74

6.3 Program Control........................................................................................................76

6.3.1 Example 1 - Using DJZ or DJZA .................................................................76

6.3.2 Example 2 - Using JBC, JBS, BC, and BS...................................................76

6.4 Logic and Arithmetic Operation...............................................................................77

6.4.1 Example - Applying the AND and COMA Instructions ...............................77

6.4.2 Example - Applying the OR Instruction. ......................................................78

6.4.3 Example - Applying the BC, BS, SWAPA, and SWAP Instructions.............78

6.4.4 Example - Applying the ADD, INC, and INCA Instructions........................79

6.4.5 Example - Applying the SUB, DEC, and DECA Instructions......................79

6.5 I/O Port Applications ................................................................................................80

6.5.1 Example - Input Pin Polling and Configuring Output Port...........................80

6.5.2 Example - Simple Keyboard Scan (16 Keys)...............................................82

6.6 Interrupt Subroutine..................................................................................................87

6.6.1 TCC Timer Interrupt.....................................................................................87

6.6.2 MTC Timer Interrupt ....................................................................................88

6.6.2.1 Example - Timer Interrupt ..........................................................88

6.6.3 Speech Timer Interrupt .................................................................................90

6.6.3.1 Example - Speech Interrupt ........................................................91

6.7 Voice ROM Access ...................................................................................................92

6.7.1 Example - Voice ROM Access......................................................................92

6.8 Playing Speech..........................................................................................................93

6.8.1 Example - Simple Speech Playback (PCM) .................................................94

6.9 Playing Melody.........................................................................................................96

6.9.1 Example - Playing Melody ...........................................................................96

6.10 Power Down Mode...................................................................................................99

6.10.1 Example - Power Down and Wake Up by Input Port.................................100

6.10.2 Example - Power Down Mode Application for Keyboard-Scan ................100

Contents

viii • Contents EM60000 Series User’s Manual

Chapter 1

Introduction

1.1 General Description

EM60000 series is an 8-bit micro-controller based sound processor IC featuring

audio function that delivers multi-channel instrument playback. The

micro-controller consists of –

 a powerful 8-bit RISC CPU that handles most of the speech/melody

functions

 an 8K word program ROM

 a voice ROM that extends up to one megabyte

The micro-controller provides 2 speech channels and 4 melody channels that

can be played back simultaneously. The speech synthesis is software

implemented and supports a wide range of sampling rates and diverse volume

levels.

The micro-controller also provides real instrument waveforms to obtain good

quality audio melody. The EM60000 offers one 8-bit input port and one 8-bit

I/O port with internal pull-low/wake-up functions for user’s applications. This

is in addition to the three general-purpose I/O ports that are provided. By

programming, applications such as section combination, trigger mode, output

control, keyboard matrix, and other logic functions can be easily implemented

with the micro-controller. Together, these powerful features motivate users in

achieving a wide range of innovative concepts.

1.2 Features

 Operating voltage: 2.4 ~ 5.5V

 8-bit RISC CPU

 Two general-purpose timers and two speech timers with interrupts

 8K word program ROM access

 Total of six channels - 2 speech and 4 melody channels (both channels can be

played simultaneously

 Wide-range of speech sampling rates - 4KHz to 20KHz (program controlled)

 Speech/voice algorithm is software (PCM, ASPCM, ADPCM) implemented

 On chip Voice ROM that extends up to one megabyte

 Uses real instrument waveforms for good quality audio melody

 Built-in 8-bit by 8-bit hardware multiplier with 16-bit result

 One 8-bit input port and one 8-bit I/O port with pull-low/wake-up functions

 Provides additional general-purpose I/O ports (up to 3 ports)

EM60000 Series User’s Manual Introduction • 1

Chapter 1

 Provides crystal oscillation or internal oscillator (by connecting a resistor).

 Two 8-bit current DAC outputs.

 Built-in watchdog timer (WDT).

1.3 Block Diagram

Tes t

OSCI OSCO

Reset

Speech Timer

VO2 VO1

8 8 8 8

8

Port 5 Port 3 Port 4 Port 2 Port 1

8-bit µC

Timing Generator

8-bit D/A

Program ROM

Voice ROM

I/O Control

RAM

Sleep/Wakeup

WDT

Timers

Addressing

Interface

Multi-tone Generator

Multiplier

8×8

Control Unit

1.4 Parts List

The EM60000 series IC’s are equipped with 8K×13 bit program ROM and 144

bytes RAM.

Part

Number

Voice ROM Input Pin I/O Pin

Output

DAC

Speech

Channels

Melody

Channels

EM60001 32K × 8 bits 8 (Port 1) 16 (Port 2, 3) None 2 2 4

EM60301 256K × 8 bits 8 (Port 1) 24 (Port 2, 3, 4) None

2 2

4

EM60600 2048K × 8 bits 8 (Port 1) 24 (Port 2, 3, 4) 8 (Port 5)

2 2

4

EM60600S 2048K × 8 bits 8 (Port 1) 24 (Port 2, 3, 4) 8 (Port 5)

2 2

4

2 • Introduction EM60000 Series User’s Manual

Chapter 1

1.5 Pin Assignments

Symbol I/O Function Description

OSCI I Crystal in/Resistor

OSCO O Clock output

P1.0~7 I Bit 0~7 of Port 1

P2.0~7 I/O Bit 0~7 of Port 2

P3.0~7 I/O Bit 0~7 of Port 3

P4.0~7 I/O Bit 0~7 of Port 4 (except EM60001)

P5.0~7 O Bit 0~7 of Port 5 (except EM60001, EM60301)

VO1 O Current output of DAC 1

VO2 O Current output of DAC 2

VDD - Positive power supply

VSS - Negative power supply

TEST I For testing use only (normally floating)

RESET I Reset pin (active low, internal pull-high)

1.6 Specifications

1.6.1 Absolute Maximum Ratings

Parameter Specification

Supply Voltage (V

DD

- V

SS

) -0.3V to +6.0V

Input Voltage V

SS

-0.3V to V

DD

+0.3V

Operating Temperature 0°C to 50°C

Storage Temperature -55°C to 125°C

EM60000 Series User’s Manual Introduction • 3

Chapter 1

1.6.2 Electrical Characteristics

(Temperature: 0°C to 50°C, VSS=0V)

Items Sym Min. Typ. Max. Unit Condition

Operating Voltage V

DD

2.4 - 5.5 V -

I

SB

- - 1.0 µA V

DD

=4.5V

Standby Current

I

SB

- - 1.0 µA V

DD

=3V

I

OP

- 3 5 mA V

DD

=4.5V, F

OSC

=6MHz, no load

Operating Current

I

OP

- 1.5 3 mA V

DD

=3V, F

OSC

=4MHz, no load

I

OH

9 - - mA V

DD

=4.5V, V

OH

=2.4V

Drive Current of

Port 2, 3, 4, & 5

I

OH

2 - - mA V

DD

=3V, V

OH

=2.4V

I

OL

3.5 - - mA V

DD

=4.5V, V

OL

=0.4V

I

OL

- - 24 mA V

DD

=4.5V, V

OL

=3V

I

OL

2.5 - - mA V

DD

=3V, V

OL

=0.4V

Sink Current of Port

2, 3, 4, & 5

I

OL

- - 12 mA V

DD

=3V, V

OL

=1.5V

V

IH

1.8 - - V V

DD

=4.5V

V

IL

- - 0.8 V V

DD

=4.5V

V

IH

1.4 - - V V

DD

=3V

Input Voltage of All

Input Ports (Without

Internal Pull-low)

V

IL

- - 0.6 V V

DD

=3V

I

- 8 12 µA V

DD

=4.5V

Input Current (With

Internal Pull-low)

I

- 3 5 µA V

DD

=3V

I

VO

2 3 4 mA V

DD

=4.5V, VO=0.7V

D/A Output Current

(maximum volume)

I

VO

2 3 4 mA V

DD

=3V, VO=0.7V

F

OSC

- 4 8 MHz V

DD

=4.5V

Operating

Frequency Range

F

OSC

- - 4 MHz V

DD

=2.4V

1.6.3 Internal Oscillator Frequency

External Resistor (R

EXT

) System Frequency (F

OSC

)

200 K ohms 1MHz

100 K ohms 2MHz

50 K ohms 4MHz

25 K ohms 6MHz

12.5 K ohms 8MHz

4 • Introduction EM60000 Series User’s Manual

Chapter 2

Architecture

2.1 Architectural Overview

2.1.1 Overview

Architecture

The EM60000 series have a high performance 8-bit RISC CPU with the

Havard-type architecture which allows the program and data to have separate

memories in order to improve the bandwidth of data access. Applying a

two-level overlapped fetch-and-execute pipeline, all instructions will only

require a single instruction cycle (except for those that modify the program

counter). Note that each instruction cycle takes two system clocks, resulting in

a high instruction throughput and fast interrupt response.

Arithmetic Logic Unit (ALU)

The EM60000 series contain an 8-bit ALU and accumulator (ACC). The ALU

is a general-purpose arithmetic unit that performs 2’s-complement arithmetic

and logical operations. It operates under all of the data memory in direct or

indirect address mode that includes memory-mapped control registers. The

ALU also supports BCD decimal arithmetic operations.

Data Memory

The data memory of EM60000 series has a total of 144 bytes with direct and

indirect address modes. Three locations of the data memory are set aside to be

shared by the multiplier. All operations can be applied directly to the data

memory. Part of the control registers are mapped to the data memory and other

part are mapped to the IOC register (I/O mapped control register). The data

memory is divided into one common and four banked blocks selected by 2

control bits.

Hardware Multiplier

The 8x8 hardware multiplier of EM60000 series takes only a single instruction

cycle. It performs signed multiplication and generates a 16-bit signed result that

is stored in two registers mapped in the data memory. The multiplication

instruction can be applied on data memory or on an immediate constant,

providing a wide range of user applications, such as Digital Signal Processing.

EM60000 Series User’s Manual Architecture • 5

Chapter 2

Program Counter and Hardware Stack

The program counter of EM60000 series is 13 bits in length and provides 8K

program ROM address. The program counter is mapped to the data memory

and operates by direct instruction. Note that such operations take two

instructions cycles to perform. An 8-level hardware stack is available to

facilitate 8-level nested subroutine calls and interrupts.

Timers

The EM60000 series have one watchdog timer and a total of four timers with

interrupt function. Two of the latter are general-purpose timers, TCC and MTC.

The former is equipped with a prescaler for general applications, and the latter

(MTC) has a prescaler for controlling the melody playback instrument. The

other two timers are dedicated for speech/voice playback. By taking advantage

of the full set of timer functions, sophisticated multi-channel instrument

applications can be easily implemented.

2.1.2 Functional Block Diagram

ST1

MTC

TCC

I/O pins

I/O Ports

I/O Port Control

8

13

Program

ROM

Address

Program

ROM Data

IR Decode

IR

Stack (8-Levels)

Program Counter

13

OSCO

OSCI

Oscillator /

Timing Control

Prescaler

Interrupt Control

8

Control

Register

RAM

WDT

R3

ACC

ALU

8

Address Generator

R9

R4

8

DATA BUS

PROOL

16

PRODH

Multiplier

8 X 8

MULT

The functional block diagram shown above outlines the block and data paths

within the EM60000 series processor. Detailed descriptions of each block are

provided in the following sections.

6 • Architecture EM60000 Series User’s Manual

Chapter 2

2.1.3 Hardware Summary

The following table explains the functions of the hardware in the above block

diagram. The acronyms, e.g., ACC, ALU, etc, under “Symbol” column are the

designated names of the internal function blocks. The “Address” column shows

the control registers address mapping for the corresponding control register

symbol in the “Symbol” column.

Symbol Function Address

ACC 8-bit accumulator -

ALU 8-bit 2’s-complement arithmetic logic unit -

Multiplier

8×8 hardware multiplier

-

MULT 8-bit multiplicand for the multiplier 0x10

PRODH &

PRODL

PRODH hold the high byte of product result, PRODL hold

the low byte of product result

0x11

0x12

R3 Status register contains status flag and page bits 0x03

R4 RAM selects register for indirect address and RAM bank 0x04

R9 Bank select register for special function control registers 0x09

Program Counter Program counter with 13 bits for 8K program ROM address 0x02

Stack 8-level hardware stacks for subroutine call and interrupt

IR Instruction register used for instruction fetch

IR Decode Instruction decoder to generate control signals

Address

Generator

Address generator for data RAM and control registers -

System Control

Registers

System control registers are useful for controlling

processor, melody, I/O functions. They are memory or I/O

mapped

Tone Generator 4-channel tone generator for melody instrument synthesis -

Prescaler Pre-scales the timing clock before entering the counter

TCC General-purpose timer with interrupt function 0x01

MTC General-purpose/melody timer with interrupt function 0x06

ST1 and ST2 2 speech timers with speech playback interrupt function -

WDT Watchdog timer

I/O Control I/O function control (input/output, pull-low, wake-up, etc)

2.2 Arithmetic Logic Unit (ALU)

The EM60000 series contain an 8-bit accumulator and an 8-bit arithmetic logic

unit that can perform 2’s-complement arithmetic operation, Boolean operation,

rotation, bit manipulation, data move, etc. There are several flags in the status

register to indicate the result of the operations. The following steps occur

during an ALU operation:

EM60000 Series User’s Manual Architecture • 7

Chapter 2

1. Data is fetched from the source location (such as data memory or I/O ports).

2. Data is then processed by the ALU. If the accumulator is one of the

operands, then it will be loaded into the ALU at the same time.

3. The result is moved to the destination location (such as accumulator, data

memory, or I/O ports).

Most of the ALU operations have two operands, one must be the accumulator,

and the other can either be the constant, memory, or I/O ports. In case of just

one operand, the data is processed by ALU itself. For data move operations, the

ALU simply passes the source data to the destination.

2.2.1 ALU Instruction Summary

2.2.1.1 Boolean Instruction:

Instruction Operation Operand

AND Logical “AND” A, R, constant

OR Logical “OR” A, R, constant

XOR Logical “XOR” A, R, constant

2.2.1.2 Arithmetic Instruction:

Instruction Operation Operand

ADD Arithmetic addition A, R, constant

SUB Arithmetic subtraction A, R, constant

INC Increase memory content by 1 R

INCA Increase memory content by 1 and load the result into ACC R

DEC Decrease memory content by 1 R

DECA Decrease memory content by 1 and load the result into ACC R

CLR Set memory content to zero R

RRC Rotate memory right 1 bit with carry bit R

RRCA

Rotate memory content right 1 bit with carry bit and load the

result into ACC

R

RLC Rotate memory content left 1 bit with carry bit R

RLCA

Rotate memory content left 1 bit with carry bit and load the

result into ACC

R

COM Take complement of memory content R

COMA

Take complement of memory content and load the result into

ACC

R

DAA Decimal adjustment -

JZ

Increase memory content by 1. If the result is zero, skip the

next instruction.

R

JZA

Increase memory content by 1 and load result into ACC. If

the result is zero, skip the next instruction.

R

DJZ

Decrease memory content by 1. If the result is zero, skip the

next instruction.

R

DJZA

Decrease memory content by 1 and load result into ACC. If

the result is zero, skip the next instruction.

R

8 • Architecture EM60000 Series User’s Manual

Chapter 2

2.2.1.3 Bit Manipulated Instruction:

Instruction Operation Operand

BS Set bit in memory content R

BC Clear bit from memory content R

2.2.1.4 Data Move Instruction:

Instruction Operation Operand

MOV Move data between operand A, R

SWAP Swap high/low nibble of memory R

SWAPA

Swap high/low nibble of memory and load the result into

ACC

R

“A” under Operand column stands for ACC (accumulator), and “R” is data memory or memory-mapped

registers, such as I/O ports, or control registers.

Example: The logical “AND” instructions

AND A, @0xF0 ; ACC = ACC & 0xF0 (0xF0 is constant)

AND A, 0x10 ; ACC = ACC & content of R10 (R10 is data memory)

AND 0x10, A ; R10 = R10 & ACC

For the detailed descriptions of the instructions, refer to Chapter 5, Instruction

Set.

2.2.2 ALU Related Status Flags

The ALU related status flags are listed as the following:

Symbol Description

C Carry flag. C=1 if there is carry-out after an ALU operation

DC

Auxiliary carry flag. DC=1 if a carry comes from the low nibble to the high

nibble of the ALU

Z Zero flag. Z=1 if the operation is zero

EM60000 Series User’s Manual Architecture • 9

Chapter 2

2.3 Hardware Multiplier

The EM60000 series incorporate an 8 x 8 hardware multiplier. By making

multiplications a hardware function, the operation can be completed in a single

instruction cycle. The operation is a signed multiplication and provides a

signed 16-bit result. The result is stored in the Product registers R11 and R12,

with R11 (PRODL) keeping the low byte and R12 (PRODH) the high byte. The

multiplicand has to be prepared in R10 (MULT) before the operation.

R10 (MULT)

× Operand of MPY instruction

Result R12 (PRODH) R11 (PRODL)

Where:

R10 (MULT) is a signed 8-bit value (ranges from –128 to +127).

Operand of MPY instruction is a signed 8-bit value that comes from the operand of an MPY

instruction.

R12 (PRODH), R11 (PRODL) has its multiplication result in a signed 16-bit value. R12 contains

the high byte and R11 the low byte.

Example 1: Integer multiplication, 10×10 = 100 (0x64).

MOV A, @10

MOV 0x10, A ; let R10 (MULT)=10

MPY @10 ; 10×10=100 (0x0064), operand is immediate value

Example 2: Integer multiplication, 10×10=100 (0x64).

MOV A, @10

MOV 0x10, A ; let R10 (MULT)=10

MOV A, @10

MOV 0x14, A ; let R14=10

MPY 0x14 ; 10×10=100 (0x0064), operand is register address

Example 3: Fractional multiplication. 64×0.75=48 (0x40×0x60=0x1800,

0x1800 left shift one bit 0x3000, high byte=0x30, it is 48 in

decimal)

MOV A, @0x40

MOV 0x10, A ; let R10 (MULT)=0x40

MPY @0x60 ; 0x40×0x60, operand is immediate value

BC 0x03, 0 ; clear carry flag of R3 (Status Flag)

RLC 0x11 ; R11 (PRODL) left rotate one bit with carry

RLC 0x12 ; R12 (PRODH) left rotate one bit with carry

MOV A, 0x12 ; correct result (0x30) will be in Accumulator

The single-cycle multiplier can improve computational throughput and reduce

code size for multiplication algorithms. With these advantages, applications

such as Digital Signal Processing can be implemented without the use of high

cost DSP chips.

10 • Architecture EM60000 Series User’s Manual

Chapter 2

2.4 Memory Organization

The EM60000 series provide 8K words of program memory and 144 bytes of

data memory. The system control registers and all I/O ports are mapped to data

memory locations.

2.4.1 Data Memory

All the 144 bytes data memory of EM60000 series can be made the operand of

an instruction. The data memory address range is from 0x00 to 0x3F. The

lower address locations (0x00 to 0x1F) are reserved for the system control

registers, I/O port data registers, and some other general-purpose data memory.

The higher locations (0x20 to 0x3F) are the general-purpose data memory and

are divided into 4 memory banks. When using the "banked" area of the data

memory, you must set the memory bank select bit (in the RAM Select Register,

R4) before accessing the desired data memory. The following table shows the

contents of "unbanked" and "banked" areas of the data memory.

1. Unbanked Area: Address Table of System Control Registers and

Data Memory.

Address Symbol Description

0x00 R0 Indirect address register

0x01 R1 (TCC) 8-bit general purpose timer register

0x02 R2 (PC) Lower 8-bit of program counter

0x03 R3 (SF) Status flag register

0x04 R4 (RSR)

RAM select register for selecting memory bank and indirect

address register

0x05 R5 (INTC) Interrupt control register for interrupt enable function and flag

0x06 R6 (MTC) 8-bit general purpose timer register for melody playing

0x07 R7 Not used or invalid address

0x08 R8 I/O ports pull-low, wake-up and watchdog timer control register

0x09 R9 Bank select register for special function control registers

0x0A R10 (MODE) Special control register for speech, melody & DAC

0x0B RB Port 1 input data register

0x0C RC Port 2 I/O data register

0x0D RD Port 3 I/O data register

0x0E RE Port 4 I/O data register

0x0F RF Port 5 output data register

0x10 R10 (MULT) Multiplicand data for the multiplier

0x11 R11 (PRODL) Low byte of product result from the multiplier

0x12 R12 (PRODH) High byte of product result from the multiplier

0x13

…

0x1F

R13 to R1F General-purpose data memory for user

EM60000 Series User’s Manual Architecture • 11

Chapter 2

2. Banked Area: 4 Banks of Data Memory Address, Ranges from

0x20 to 0x3F

13 common data memory and 4 data memory banks are available totaling 141

bytes. Note that R10, R11, and R12 may be used as common data memory if

the multiplier is not utilized, making 144 bytes of memory available. The

following illustrates the memory map of the data memory “banked” area.

Address Mapped Data Memory

R0

IAR

R1

TCC

R2

PC

R3

SF

R4 RSR

Stack

(8 levels)

I/O Mapped Register

R5

INTC

IOC5 Prescaler

R6

MTC

IOC6

R7

Not used

IOC7

R8

IOC8

R9

IOC9

RA

Mode

IOCA

RB

Port 1

IOCB

RC

Port 2

IOCC

RD

Port 3

IOCD Port 2 I/O

RE

Port 4

IOCE Port 3 I/O

RF

Port 5

IOCF Port 4 I/O

R10

MULT

R11

PRODL

R12

PRODH

R13

: : R13~1F Common Data Memory

R1F

00 01 10 11

R20

(Bank 0)

(Bank 1)

(Bank 2)

(Bank 7)

:

32x8

32x8 32x8

:

Data

. . . . .

Data

R3F

Memory

NOTE

1. R0 and R1 indicate address is 0x00 and 0x01, respectively.

2. Refer to Chapter 3; Section 3.3 for detailed discussion of the I/O mapped control

registers.

3. All the data memory will NOT initialize after a reset.

4. Grayed blocks are the control register banks for Special Function Control.

12 • Architecture EM60000 Series User’s Manual

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