Vodafone SS 08 User manual

Type
User manual
Vodafone Chair Mobile Communications Systems, Prof. Dr.-Ing. G. Fettweis
chair
Digital Signal Transmission Lab
SS 08
Oliver Arnold
Steffen Kunze
TU Dresden, 4/29/2008 Slide 2
chair
Introduction
Hardware
Why to use digital signal processing?
General introduction to DSPs
The TMS320C6711 DSP
Architecture Overview
Peripherals
DSK6711 evaluation board - Software
Code Composer Studio
DSP/BIOS
Multi-channel Buffered Serial Port (McBSP)
TU Dresden, 4/29/2008 Slide 3
chair
Hardware
TU Dresden, 4/29/2008 Slide 4
chair
Digital Signal Processing (DSP)
Consumer Audio
Stereo A/D, D/A
PLL
Mixers
Multimedia
Stereo audio
Imaging
Graphics palette
Voltage regulation
Wireless / Cellular
Voice-band audio
RF codecs
Voltage regulation
HDD
PRML read channel
MR pre-amp
Servo control
SCSI tranceivers
Automotive
Digital radio A/D/A
Active suspension
Voltage regulation
DTAD
Speech synthesizer
Mixed-signal
processor
DSP:
Technology
Enabler
TU Dresden, 4/29/2008 Slide 5
chair
System Considerations
Performance
Performance
Interfacing
Interfacing
Power
Power
Size
Size
Ease
Ease
-
-
of Use
of Use
Programming
Programming
Interfacing
Interfacing
Debugging
Debugging
Integration
Integration
Memory
Memory
Peripherals
Peripherals
Cost
Cost
Device cost
Device cost
System cost
System cost
Development cost
Development cost
Time to market
Time to market
TU Dresden, 4/29/2008 Slide 6
chair
Why Go Digital?
Digital signal processing techniques are now
so powerful that sometimes it is extremely
difficult, if not impossible, for analogue signal
processing to achieve similar performance.
Examples:
FIR filter with linear phase
Adaptive filters
TU Dresden, 4/29/2008 Slide 7
chair
Why Go Digital?
Analogue signal processing is achieved by
using analogue components such as:
Resistors
Capacitors
Inductors
The inherent tolerances associated with
these components, temperature, voltage
changes and mechanical vibrations can
dramatically affect the effectiveness of the
analogue circuitry
TU Dresden, 4/29/2008 Slide 8
chair
Why Go Digital?
With DSP? - It is easy to:
Change applications
Correct applications
Update applications
Additionally DSPs reduce:
Noise susceptibility
Chip count
Development time
Cost
Power consumption
TU Dresden, 4/29/2008 Slide 9
chair
General Introduction to DSPs
TU Dresden, 4/29/2008 Slide 10
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What Problem Are We Trying To Solve?
Digital sampling of
an analog signal:
A
t
Most DSP algorithms can be
expressed as:
count
i = 1
Y = Σ a
i
* x
i
for (i = 1; i < count; i++){
sum += m[i] * n[i]; }
DAC
xY
ADC
DSP
TU Dresden, 4/29/2008 Slide 11
chair
What are the typical DSP algorithms?
The Sum of Products (SOP) is the key element in
most DSP algorithms:
0
() ( )
M
k
k
yn axn k
=
=
==
+=
N
k
k
M
k
k
knybknxany
10
)()()(
=
=
N
k
knhkxny
0
)()()(
=
=
1
0
])/2(exp[)()(
N
n
nkNjnxkX
π
() ()
=
+=
1
0
12
2
cos).().(
N
x
xu
N
xfucuF
π
Discrete Cosine Transform
Discrete Fourier Transform
Convolution
Infinite Impulse Response Filter
Finite Impulse Response Filter
EquationAlgorithm
TU Dresden, 4/29/2008 Slide 12
chair
Use a DSP processor when the following
are required:
Cost saving
Smaller size
Low power consumption
Processing of many “high” frequency signals in
real-time
Use a GPP processor when the following
are required:
Large memory
Advanced operating systems
Why do we need DSP processors?
TU Dresden, 4/29/2008 Slide 13
chair
Hardware vs. Microcode multiplication
DSP processors are optimized to perform
multiplication and addition operations.
Multiplication and addition are done in
hardware and in one cycle.
Example: 4-bit multiply (unsigned).
1011
1011
x 1110
x 1110
1011
1011
x 1110
x 1110
Hardware
Hardware
Microcode
Microcode
10011010
10011010
0000
0000
1011.
1011.
1011..
1011..
1011...
1011...
10011010
10011010
Cycle 1
Cycle 1
Cycle 2
Cycle 2
Cycle 3
Cycle 3
Cycle 4
Cycle 4
Cycle 5
Cycle 5
TU Dresden, 4/29/2008 Slide 14
chair
General Purpose DSP vs. DSP in ASIC
Application Specific Integrated Circuits
(ASICs) are semiconductors designed for
dedicated functions.
The advantages and disadvantages of using
ASICs are listed below:
Advantages
Advantages
High throughput
High throughput
Lower silicon area
Lower silicon area
Lower power consumption
Lower power consumption
Improved reliability
Improved reliability
Reduction in system noise
Reduction in system noise
Low overall system cost
Low overall system cost
Disadvantages
Disadvantages
High investment cost
High investment cost
Less flexibility
Less flexibility
Long time from design to
Long time from design to
market
market
TU Dresden, 4/29/2008 Slide 15
chair
Floating vs. Fixed point processors
Applications which require:
High precision
Wide dynamic range
High signal-to-noise ratio
Ease of use
ÎNeed a floating point processor
Drawback of floating point processors:
Higher power consumption
Usually higher cost
Usually slower than fixed-point counterparts and
larger in size
TU Dresden, 4/29/2008 Slide 16
chair
TMS320C6711 Architectural Overview
TU Dresden, 4/29/2008 Slide 17
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General DSP System Block Diagram
P
E
R
I
P
H
E
R
A
L
S
Central
Processing
Unit
Internal Memory
Internal Buses
External
Memory
TU Dresden, 4/29/2008 Slide 18
chair
‘6711 CPU Overview
Specification
Clock Rate: 100/150 MHz Î 600/900 MFLOPS
0.18-μm/5-Level Metal Process – CMOS Technology
CPU has got two Datapaths, altogether:
Four ALUs (Floating- and Fixed-Point)
Two ALUs (Fixed-Point)
Two Multipliers (Floating- and Fixed-Point)
Load-Store Architecture
2*16 32-Bit General-Purpose Registers
TU Dresden, 4/29/2008 Slide 19
chair
‘6711 CPU Overview
VelociTI Î advanced very-long instruction words (VLIW)
Program Memory Width is 256 Bit
Up to 8 32-Bit instructions can be executed in parallel/Cycle
16, 32 and 40 bit fixed point operands
32 and 64 bit floating point operands
Instruction parallelism is detected at compile-time
no data dependency checking is done in Hardware.
Instruction Packing Reduces Code Size
All operations work on registers
Memory Architecture
4K-Byte L1P Program Cache (Direct Mapped)
4K-Byte L1D Data Cache (2-Way Set-Associative)
64K-Byte L2 Unified Mapped RAM/L2 Cache (Flexible Data/Program
Allocation)
TU Dresden, 4/29/2008 Slide 20
chair
Functional Block and CPU Diagram
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Vodafone SS 08 User manual

Type
User manual

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