Ziatech Corporation ZT 8809A Operating instructions

ZT 8808A/8809A

V20 Single Board Computers

OPERATING MANUAL

FOR

ZT 8808A/8809A REVISION A

ZT 88CT08A/88CT09A REVISION A

May 1, 1993

1050 Southwood Drive

San Luis Obispo, CA 93401 USA

FAX (805) 541-5088

Telephone (805) 541-0488

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CUSTOMER SUPPORT

If you have a technical question, please call Ziatech’s

Customer Support Service at one of the following numbers.

Corporate Headquarters: (805) 541-0488

(805) 541-5088 (FAX)

You can also use a modem to leave a message on the 24-hour

Ziatech Bulletin Board Service (BBS) by calling

(805) 541-8218. The BBS will provide you with current

Ziatech product revision and upgrade information.

PREFACE

The ZT 8808A and ZT 8809A are single board computers designed

primarily for DOS applications on the STD bus. The combination of

the 8088-compatible V20 microprocessor with RAM, EPROM, serial

ports, a printer port, timers, and a real-time clock makes a hardware-

compatible PC viable for compact industrial applications.

This manual describes the operation and use of the ZT 8808A/8809A.

The only difference between the ZT 8808A and ZT 8809A is the

processor clock speed; the ZT 8808A runs at 5 MHz and the

ZT 8809A runs at 8 MHz. The ZT 88CT08A and ZT 88CT09A are

extended temperature CMOS versions of the ZT 8808A and

ZT 8809A.

Except where otherwise specifically stated, all references in this

manual to the ZT 8809A also apply to the ZT 8808A and

ZT 88CT08A/88CT09A.

The following organizational outline describes the focus of each

chapter. Section headings enclosed in boxes indicate the locations of

labeled tabs, provided for quick access to the appropriate information.

Chapter 1, "Introduction,"is an overview of the ZT 8809A. It

includes a product definition, a listing of product features, a functional

block diagram, and a brief description of each block. If you are

evaluating the ZT 8809A to determine whether it fits your needs, this

chapter is especially useful to you.

Chapter 2, "Getting Started,"summarizes the information you need

to get your ZT 8809A up and running. Refer to the remaining

chapters in this manual for further explanation of the material covered

here.

Chapter 3, "Theory Of Operation," presents a detailed description

of ZT 8809A system level operation. Some of the topics discussed

include microprocessor performance compared to the IBM PC,

Preface

STD bus compatibility, serial communications, interrupts, direct

memory access, power-fail protection, and battery backup.

Chapter 4, "Application Examples," provides specific examples of

the ZT 8809A in operation, including code to implement these

applications. The examples demonstrate the use of interrupts, timers,

and the real-time clock.

Chapter 5, "Memory and I/O Capability," focuses on the memory

and input/output organization of the V20 microprocessor relative to

the ZT 8809A.

Chapter 6, "CPU Description (V20)," describes the basic

components of the V20 microprocessor, its enhancements over 8088

architecture, its ability to operate in both native mode and 8080

emulation mode, its operation with DMA, and the wait state

generator.

Chapter 7, "Numeric Data Processor (8087)," explains the

installation and operation of the optional 8087 Numeric Data

Processor for numerically intensive applications.

Chapter 8, "Serial Communications (16C452)," describes the two

RS-232-C serial ports on the ZT 8809A, serial port signals, and

register addresses.

Chapter 9, "Centronics Printer Interface," details the Centronics

printer port interface.

Chapter 10, "Real-Time Clock (DS 1215)," explains the

organization of the real-time clock, including method of access and

register organization.

Preface

Chapter 11, "Counter/Timers (8254)," describes the main

components of the three programmable 16-bit counter/timers

implemented in an Intel 8254 chip on the ZT 8809A. This chapter

describes the method used to program the counter/timers and their use

by STD DOS and STD ROM.

Chapter 12, "Interrupt Controller (8259A)," describes the features

and operation of the Intel 8259A Programmable Interrupt Controller

(PIC).

Chapter 13, "ZT 88CT08A/88CT09A CMOS Boards," describes

the functional, electrical, and environmental characteristics of the

CMOS versions of the ZT 8808A and ZT 8809A that differ from the

non-CMOS versions.

Appendix A, "Jumper Configurations," describes the ZT 8809A

jumper selectable options in detail.

Appendix B, "Specifications," contains the electrical, mechanical,

and environmental specifications for the ZT 8809A. It also contains

STD-80 bus timing diagrams, cable drawings, and tables showing

connector pin assignments.

Appendix C, "Customer Support," offers technical assistance for

ZT 8809A users. A revision history, and warranty and service

information are also included.

CONTENTS

I. INTRODUCTION

Chapter 1. INTRODUCTION 1-1

OVERVIEW ..................................................... 1-1

ZT 88CT08A and ZT 88CT09A................................ 1-3

FEATURES OF THE ZT 8809A ................................... 1-4

FUNCTIONAL BLOCKS ......................................... 1-6

V20 (uPD70108) Processor .................................... 1-6

Memory and I/O Addressing................................... 1-6

Wait-State Generator .......................................... 1-7

Direct Memory Access (DMA) ................................ 1-7

Optional Battery Backup ...................................... 1-7

AC/DC Power-Fail Detection .................................. 1-8

Real-Time Clock............................................. 1-9

Serial Communications....................................... 1-9

Counter/Timers ............................................. 1-10

Interrupts ................................................... 1-11

Centronics Printer/General Purpose I/O Port .................... 1-12

Optional Numeric Data Coprocessor (8087).................... 1-12

Clock Slowdown & Halt Restart (CMOS boards only)........... 1-13

II. GETTING STARTED

Chapter 2. GETTING STARTED 2-1

OVERVIEW ..................................................... 2-2

UNPACKING .................................................... 2-2

WHAT’S IN THE BOX? .......................................... 2-3

SYSTEM REQUIREMENTS ...................................... 2-4

Contents

Physical Requirements........................................ 2-4

Power Requirements.......................................... 2-4

Environmental Requirements.................................. 2-6

INSTALLING THE ZT 8809A.................................... 2-7

Configuring the ZT 8809A for STD ROM ....................... 2-9

Configuring the ZT 8809A for STD DOS ...................... 2-13

MEMORY ADDRESSING ....................................... 2-19

I/O ADDRESSING .............................................. 2-22

UPGRADING FROM ZT 8806/8807 SYSTEMS ................... 2-24

III. USER’S REFERENCE

Chapter 3. THEORY OF OPERATION 3-1

OVERVIEW ..................................................... 3-2

RELATIVE MICROPROCESSOR PERFORMANCE ................ 3-3

STD BUS COMPATIBILITY ...................................... 3-4

MEMORY AND I/O .............................................. 3-4

SERIAL COMMUNICATIONS .................................... 3-4

Serial Port 1 (COM1) ......................................... 3-5

Serial Port 2 (COM2) ......................................... 3-6

INTERRUPTS ................................................... 3-8

Interrupt Request Assignments ................................. 3-8

Polled Interrupts on the STD Bus.............................. 3-10

STD Bus Vectored Interrupts ................................. 3-12

STD Bus Cascaded Interrupts ................................. 3-13

Non-Maskable Interrupts ..................................... 3-14

DIRECT MEMORY ACCESS (DMA) ............................ 3-15

Advantages of DMA ......................................... 3-15

DMA Operation............................................. 3-16

POWER-FAIL PROTECTION ................................... 3-18

DC Power-Fail .............................................. 3-18

AC Power-Fail .............................................. 3-19

System Battery Fail .......................................... 3-22

BATTERY ..................................................... 3-23

STATUS INDICATOR (LED) .................................... 3-25

RESET ......................................................... 3-26

CMOS VERSIONS OF THE ZT 8808A/8809A..................... 3-27

Added Features ............................................. 3-27

Functional Differences ....................................... 3-29

Contents

Chapter 4. APPLICATION EXAMPLES 4-1

OVERVIEW ..................................................... 4-2

EXAMPLE 1-A: USING SIMPLE INTERRUPTS ................... 4-3

Objectives................................................... 4-3

System Configuration......................................... 4-3

Software Outline............................................. 4-4

Program Code................................................ 4-6

EXAMPLE 1-B: HANDLING SLAVE INTERRUPTS .............. 4-13

Objectives.................................................. 4-13

System Configuration........................................ 4-14

Software Outline............................................ 4-14

Program Code.............................................. 4-17

EXAMPLE 2: POWER-FAIL/WATCHDOG TIMER ................ 4-28

Objectives.................................................. 4-28

System Level Issues ......................................... 4-28

System Requirements........................................ 4-29

Software Outline............................................ 4-31

Flowcharts For AC Power-Fail & Watchdog Interrupts.......... 4-34

EXAMPLE 3: REAL-TIME CLOCK DRIVERS .................... 4-40

Objectives.................................................. 4-40

System Configuration........................................ 4-40

Software Outline............................................ 4-40

Chapter 5. MEMORY AND I/O CAPABILITY 5-1

OVERVIEW ..................................................... 5-1

MEMORY ADDRESSING ........................................ 5-2

Memory Expansion (MEMEX) ................................ 5-2

On-Board Memory Capacity ................................... 5-2

Write Protection.............................................. 5-3

MEMORY MAPS ................................................ 5-4

BATTERY BACKUP ............................................ 5-10

MEMORY DEVICE LOCATIONS ................................ 5-11

Sockets 3D1 and 5D1 ........................................ 5-12

Sockets 7D1 and 9D1 ........................................ 5-13

DEVICE ACCESS TIMES ....................................... 5-14

INPUT/OUTPUT ADDRESSING ................................. 5-15

Chapter 6. CPU DESCRIPTION (V20) 6-1

V20 OVERVIEW ................................................ 6-2

Segment Registers............................................ 6-3

Program Counter (PC) [IP] .................................... 6-5

Contents

Prefetch Pointer (PFP) ........................................ 6-6

General Purpose Registers ..................................... 6-6

Pointers and Index Registers ................................... 6-7

Program Status Word (PSW) [FL] .............................. 6-8

V20 ARCHITECTURAL ENHANCEMENTS ....................... 6-9

Dual Data Bus ............................................... 6-9

Effective Address Generator ................................... 6-9

16/32-Bit Temporary Shift Registers (TA,TB) .................. 6-10

Loop Counter (LC) .......................................... 6-10

Program Counter (PC) and Prefetch Pointer (PFP) .............. 6-10

Enhanced and Unique Instructions............................. 6-11

MODE OPERATIONS - 8080 EMULATION MODE ............... 6-12

Break for Emulation (BRKEM) ............................... 6-14

Return From Emulation (RETEM) ............................ 6-14

Call Native Routine (CALLN) ................................ 6-15

Return from Interrupt (RETI) ................................. 6-15

Register Use in Emulation Mode .............................. 6-16

DMA SUPPORT ................................................ 6-18

RESET STATE ................................................. 6-20

WAIT-STATE GENERATOR ..................................... 6-21

Chapter 7. NUMERIC DATA PROCESSOR (8087) 7-1

OVERVIEW ..................................................... 7-1

zSBC 337 PIGGYBACK PROCESSOR ............................ 7-3

INSTALLING THE zSBC 337..................................... 7-4

COPROCESSOR INTERFACE .................................... 7-7

MEMORY ADDRESSING ........................................ 7-8

INTERRUPT/NUMERIC ERRORS................................ 7-9

REFERENCES ................................................. 7-13

Chapter 8. SERIAL COMMUNICATIONS (16C452) 8-1

OVERVIEW ..................................................... 8-2

SERIAL COMMUNICATIONS PROTOCOL ....................... 8-3

SERIAL INTERFACE (RS-232-C/422/485)......................... 8-8

RS-232-C vs. RS-422/485.................................... 8-10

Signal Definitions........................................... 8-11

SERIAL REGISTERS ........................................... 8-16

Transmit and Receive Buffer Registers ........................ 8-20

Scratchpad Register ......................................... 8-20

Line Control Register ........................................ 8-21

Baud Rate Generator ......................................... 8-24

Contents

Line Status Register ......................................... 8-26

Interrupt ID Register ......................................... 8-28

Interrupt Enable Register ..................................... 8-30

Modem Control Register ..................................... 8-31

Modem Status Register ...................................... 8-33

Chapter 9. CENTRONICS PRINTER INTERFACE 9-1

OVERVIEW ..................................................... 9-1

PRINTER PORT OUTPUT CHARACTERISTICS ................... 9-3

USING THE PRINTER PORT ..................................... 9-4

REGISTER DEFINITIONS/ADDRESSES .......................... 9-5

Data Port .................................................... 9-6

Status Port ................................................... 9-7

Control Port ................................................. 9-8

DISABLING SHARING OF PRINTER PORT SIGNALS ........... 9-12

OPTIONAL PRINTER CABLE PINOUT .......................... 9-14

PRINTER PORT RESET STATE ................................. 9-15

Chapter 10. REAL-TIME CLOCK (DS 1215) 10-1

OVERVIEW .................................................... 10-1

OPERATION ................................................... 10-3

TIMECHIP COMPARISON REGISTER DEFINITION ............. 10-5

TIMEKEEPER REGISTER INFORMATION ...................... 10-6

TIMECHIP REGISTER DEFINITION ............................ 10-7

AM/PM 12/24-Hour Mode ................................... 10-8

Oscillator and Reset Bits ..................................... 10-8

Zero Bits ................................................... 10-8

Chapter 11. COUNTER/TIMERS (8254) 11-1

OVERVIEW .................................................... 11-2

BLOCK DIAGRAM ............................................. 11-3

COUNTER/TIMER ARCHITECTURE ............................ 11-4

OPERATION ................................................... 11-6

Reset State ................................................. 11-6

Programming ............................................... 11-6

Read Operations............................................. 11-8

Mode Definitions........................................... 11-16

Operation Common to All Modes ............................ 11-23

Counter Use by STD DOS and STD ROM .................... 11-25

Contents

Chapter 12. INTERRUPT CONTROLLER (8259A) 12-1

OVERVIEW .................................................... 12-3

I/O PORT ADDRESSES ......................................... 12-3

OPERATION OVERVIEW ....................................... 12-4

FUNCTIONAL DESCRIPTION .................................. 12-7

Interrupt Request Register (IRR) .............................. 12-8

Interrupt Mask Register (IMR) ................................ 12-8

Priority Resolver (PR) ....................................... 12-9

Interrupt In-Service Register (ISR) ............................ 12-9

Control Logic ............................................... 12-9

Read/Write Control Logic ................................... 12-10

Initialization and Operation Registers ......................... 12-10

Cascade Buffer/Comparator ................................. 12-10

PROGRAMMABLE REGISTERS ............................... 12-11

Initialization Control Words (ICW1-4) ........................ 12-12

Operation Control Words (OCW1-3) ......................... 12-16

8259A I/O PORT ADDRESSES ................................. 12-21

INTERRUPT ASSIGNMENTS ON THE ZT 8809A............... 12-22

OPERATION OF THE INTERRUPT CONTROLLER ............. 12-24

Priorities .................................................. 12-24

Interrupt Triggering........................................ 12-27

Interrupt Status............................................ 12-29

EOI COMMANDS ............................................. 12-31

Nonspecific EOI Commands ................................ 12-31

Specific EOI Commands .................................... 12-32

Automatic EOI Mode ....................................... 12-32

RESET ........................................................ 12-34

Chapter 13. ZT 88CT08A/88CT09A CMOS BOARDS 13-1

OVERVIEW .................................................... 13-1

FUNCTIONAL DIFFERENCES .................................. 13-2

Logic Family (CT vs. C) ..................................... 13-2

Use of 80C88 Processor ...................................... 13-3

Addition of Optional 8087(-2) ................................ 13-4

Clock Slowdown Mode ...................................... 13-4

Halt With Restart Via Interrupt ................................ 13-6

ELECTRICAL/ENVIRONMENTAL DIFFERENCES .............. 13-8

Increased Temperature Range ................................. 13-8

Reduced Power Consumption................................. 13-8

Bus Loading................................................ 13-9

Contents

IV. APPENDICES

Appendix A. JUMPER CONFIGURATIONS A-1

OVERVIEW .................................................... A-1

JUMPER DESCRIPTIONS ....................................... A-3

Appendix B. SPECIFICATIONS B-1

OVERVIEW .................................................... B-1

ELECTRICAL AND ENVIRONMENTAL ......................... B-2

Absolute Maximum Ratings ................................... B-2

DC Operating Characteristics .................................. B-2

Battery Backup Characteristics ................................ B-3

STD Bus Loading Characteristics .............................. B-3

MECHANICAL ................................................. B-6

CONNECTORS ................................................. B-9

CABLES ....................................................... B-20

TIMING ....................................................... B-23

Appendix C. CUSTOMER SUPPORT C-1

OVERVIEW .................................................... C-1

TROUBLESHOOTING .......................................... C-2

Powering Up STD ROM ...................................... C-2

Powering Up STD DOS ...................................... C-4

ZT 8808A/8809A REVISION HISTORY ........................... C-8

Revision 0 - Original Release of Board, 12/17/91................ C-8

Revision A - 8/19/92 ......................................... C-8

ZT 88CT08A/88CT09A REVISION HISTORY ..................... C-8

RELIABILITY .................................................. C-9

WARRANTY .................................................. C-10

TECHNICAL ASSISTANCE .................................... C-11

RETURNING FOR SERVICE ................................... C-12

TABLES

Table 3–1 Processor Speed Comparison. ......................... 3-3

Table 3–2 Serial Communications Standards. .................... 3-7

Table 5–1 Memory Configurations, 3D1/5D1/BRAM. ........... 5-12

Table 5–2 Memory Configurations, 7D1/9D1. ................... 5-13

Table 5–3 Device Access Times. .............................. 5-14

Table 6–1 Segment Registers. .................................. 6-4

Table 6–2 8080 Emulation Register Use. ....................... 6-16

Table 6–3 Memory Access Times. ............................. 6-21

Table 7–1 Queue-Status Line Functions. ......................... 7-7

Table 8–1 16C452 Reset State. ................................ 8-14

Table 8–2 ZT 8809A I/O Port Assignments. .................... 8-17

Table 8–3 16C452 Addressable Registers Summary. ............. 8-18

Table 8–4 Baud Rate Table. ................................... 8-25

Table 8–5 16C452 Interrupt Control Functions. .................. 8-28

Table 9–1 16C452 Printer Port Output Characteristics. ............ 9-3

Table 9–2 Parallel Port Register Definitions. ..................... 9-5

Table 9–3 Parallel Port Register Addresses. ...................... 9-5

Table 9–4 Shared Printer Signals. .............................. 9-13

Table 9–5 ZT 90039 Cable Pinout. ............................. 9-14

Table 11–1 Read-Back Command Example. .................... 11-15

Table 11–2 Gate Pin Operations Summary. ..................... 11-22

Table 11–3 Minimum and Maximum Initial Counts. ............. 11-24

Table 12–1 PIC Registers. .................................... 12-11

Table A–1 Jumper Descriptions. ................................ A-3

Table A–2 Memory Addressing, W55-W59. .................... A-42

Table B–1 STD Bus Signal Loading, P Connector. ................ B-4

Table B–2 STD Bus Signal Loading, E Connector. ................ B-5

Table B–3 Mechanical Specifications. ........................... B-7

Table B–4 J1 Pin Assignments (RS-232-C). ..................... B-13

Table B–5 J2 Pin Assignments (RS-232-C). ..................... B-14

Table B–6 J2 Pin Assignments (RS-422/485). ................... B-15

Table B–7 J3 Pin Assignments. ................................ B-16

Table B–8 J4 Pin Assignments. ................................ B-17

Tables

Table B–9 J5 Pin Assignments. ................................ B-17

Table B–10 J6 Pin Assignments. ................................ B-18

Table B–11 J7 Pin Assignments. ................................ B-19

ILLUSTRATIONS

Figure 1–1 ZT 8809A Functional Block Diagram. ................. 1-5

Figure 2–1 Non-DOS Factory Default Jumper Configuration. ....... 2-8

Figure 2–2 ZT 8809A Configured For STD DOS. ................ 2-14

Figure 2–3 STD DOS Factory Default Memory Map. ............. 2-20

Figure 2–4 STD ROM Factory Default Memory Map. ............ 2-21

Figure 2–5 I/O Map, STD DOS / STD ROM Systems. ............ 2-23

Figure 3–1 PIC Interrupt Input Requests. ......................... 3-9

Figure 3–2 Polled Interrupt Structure. ........................... 3-11

Figure 3–3 Small Scale Vectored Structure. ...................... 3-12

Figure 3–4 Large Scale Vectored Structure. ...................... 3-13

Figure 3–5 DMA With STD Bus Controller. ..................... 3-17

Figure 3–6 AC Transformer Connection. ........................ 3-19

Figure 5–1 STD DOS Factory Default Memory Map. .............. 5-4

Figure 5–2 STD DOS Factory Default Jumper Configuration. ....... 5-5

Figure 5–3 STD DOS Map with 640K On-Board RAM. ............ 5-6

Figure 5–4 STD DOS With 640K RAM Jumper Configuration. ..... 5-7

Figure 5–5 Non-DOS Factory Default Memory Map. .............. 5-8

Figure 5–6 Non-DOS Factory Default Jumper Configuration. ....... 5-9

Figure 5–7 Memory Chip Locations. ............................ 5-11

Figure 5–8 ZT 8809A I/O Map. ................................ 5-16

Figure 6–1 Program Status Word. ................................ 6-8

Figure 6–2 V20 Modes. ....................................... 6-13

Figure 6–3 DMA With STD Bus Controller. ..................... 6-19

Figure 7–1 zSBC 337 Piggyback Processor Installation. ............ 7-6

Figure 8–1 Establishing Serial Communications. .................. 8-5

Figure 8–2 Loopback of RTS/CTS, DTR/DSR. .................... 8-7

Figure 8–3 16C452 Serial Port Block Diagram. ................... 8-9

Figure 9–1 Printer Interface Block Diagram. ...................... 9-2

Figure 10–1 Real-Time Clock Block Diagram. .................... 10-2

Figure 10–2 Timechip Comparison Register. ...................... 10-5

Figure 10–3 Timechip Register. ................................. 10-7

Figure 11–1 Intel 8254 Timers Block Diagram. ................... 11-3

Figure 11–2 Internal Block Diagram of a Counter. ................. 11-4

Illustrations

Figure 11–3 Control Word Format. .............................. 11-7

Figure 11–4 Counter Latch Command Format. .................... 11-9

Figure 11–5 Counter Status Format. ............................ 11-12

Figure 11–6 Null Count Operation. ............................. 11-13

Figure 12–1 V20 Interrupt Vector Table. ......................... 12-5

Figure 12–2 8259A Block Diagram. ............................. 12-7

Figure 12–3 8259A ICW Formats. .............................. 12-13

Figure 12–4 8259A Operation Control Word Formats. ............ 12-17

Figure 12–5 8259A Interrupts. ................................. 12-23

Figure A–1 W1 - W12 Jumper Block. ............................ A-2

Figure A–2 W13 - W32 Jumper Block. .......................... A-11

Figure A–3 COM2 Configured as RS-232-C DCE. ............... A-18

Figure A–4 COM2 Configured as RS-232-C DTE. ............... A-19

Figure A–5 COM2 Configured as RS-422 DCE. ................. A-20

Figure A–6 COM2 Configured for RS-485 Operation. ............ A-21

Figure A–7 COM1 Configured for DTE Operation. ............... A-23

Figure A–8 COM1 Configured for DCE Operation. .............. A-24

Figure A–9 W33-W36, W38-W46, W68 Jumper Blocks. .......... A-26

Figure A–10 Socket 3D1 Configuration. .......................... A-31

Figure A–11 W37, W47-50, W66-W67 Jumper Blocks. ............ A-34

Figure A–12 W51 - W59 Jumper Block. .......................... A-37

Figure A–13 W60 - W65 Jumper Block. ......................... A-46

Figure A–14 ZT 8809A User Configuration. ...................... A-54

Figure A–15 Non-DOS Factory Default Jumper Configuration. ..... A-55

Figure A–16 ZT 8809A Configured for STD DOS. ................ A-56

Figure B–1 Board Dimensions Without zSBC 337. ................ B-7

Figure B–2 Board Dimensions With zSBC 337. ................... B-8

Figure B–3 P/E Connector Pinout. .............................. B-11

Figure B–4 ZT 8809A Connector Locations. ..................... B-12

Figure B–5 ZT 90014 Cable Drawing. .......................... B-20

Figure B–6 ZT 90027 Cable Drawing. .......................... B-21

Figure B–7 ZT 90039 Cable Drawing. .......................... B-22

Figure B–8 ZT 8809A CLOCK* Timing. ........................ B-23

Figure B–9 ZT 8809A Status Timing. ........................... B-24

Figure B–10 ZT 8809A Read Timing. ............................ B-25

Figure B–11 ZT 8809A Write Timing. ........................... B-26

Figure B–12 ZT 8809A Wait Request Timing. .................... B-27

Figure B–13 ZT 8809A Bus Exchange Timing. ................... B-28

Figure B–14 ZT 8809A Interrupt Timing. ........................ B-29

Chapter 1

INTRODUCTION

Contents Page