Finisar FTLX1671D3BTL Datasheet

Finisar
Brand
Finisar
Model
FTLX1671D3BTL
Category
Network transceiver modules
Type
Datasheet
© Fin
i
PR
O
•
•
•
•
•
•
•
•
•
•
•
Finis
trans
c
mod
e
10G
B
and
i
usin
g
inter
o
diag
n
8472
4
Finis
PR
O
i
sar Corporati
o
P
10
G
O
DUCT FE
A
Hot-plug
g
Supports
Power di
s
Typical
<
RoHS-6
Industria
l
-40°C to
8
Single 3.
3
Maximu
m
1550nm
c
technolo
g
Receiver
interface
Duplex L
Built-in
d
ar’s FTLX
1
c
eivers are
e
fiber.
T
B
ASE-ER/E
i
s a “limiti
n
g
an EDC P
o
perating th
n
ostics func
t
4
. The trans
c
ar Applicati
o
O
DUCT SE
L
o
n - February
2
P
RELI
M
G
b/s Ind
u
A
TURES
g
able SFP+
f
9.95 to 10.3
s
sipation <
1
<
1W
c
ompliant (l
e
l
temperatur
e
8
5°C
3
V power s
u
m
link lengt
h
c
ooled CM
L
g
y
limiting ele
c
C connecto
r
d
igital diagn
o
1
671D3BT
L
designed f
o
T
hey are c
o
W
3
. The F
T
n
g module”,
HY IC sho
u
e
host-
b
oar
d
t
ions are a
v
c
eiver is R
o
o
n Note A
N
L
ECTION
2
011
M
INAR
Y
RoHS
-
u
strial T
e
SFP+
FTLX
f
ootprint
Gb/s
b
it rat
e
1
.5W;
e
a
d
-free)
e
range
u
pply
h
of 40km
L
TM
c
trical
r
o
stic functio
L
10Gb/s
E
o
r use in 10
-
o
mpliant w
i
T
LX1671D3
B
i.e., it em
p
u
ld follow t
h
d
EDC PH
Y
v
ailable via
o
HS compli
a
N
-2038
6
.
FTLX
1
Rev. A0
Y
Produ
c
-
6 Comp
l
e
mperat
u
Transce
i
1671D3
B
e
s
ns
APP
L
• 1
0
E
nhanced S
m
-
Gigabit Et
h
i
th SFF-84
3
B
TL incorp
o
p
loys a limi
t
h
e IC man
u
Y
with a li
m
a 2-wire s
e
a
nt and lead
1
671D3
B
c
t Speci
fi
l
iant
u
re 40k
m
i
ver
B
TL
Prelimi
n
L
ICATION
S
0
GBASE-E
R
m
all Form
h
ernet links
3
1
1
, SFF-8
4
o
rates adva
n
t
ing receive
r
u
facturer’s r
e
m
iting recei
v
e
rial interfa
c
free per Di
r
B
TL
fi
cation
m
Dataco
m
n
ary photo sho
w
S
R
/EW 10G
E
Factor Plu
g
up to 40k
m
4
32
2
and I
E
n
ced CML
™
r
. Host bo
a
e
commende
d
v
er SFP+ m
o
c
e, as spec
i
r
ective 200
2
Page
m
w
n.
E
thernet
g
gable SF
P
m
over sing
l
E
EE 802.3
a
™
technolog
y
a
rd designe
r
d
settings f
o
o
dule. Digit
a
i
fied in SF
F
2
/95/EC
5
, a
n
1
P
+
l
e
a
e
y
,
r
s
o
r
a
l
F
-
n
d
FTL
X
© Fin
i
I.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Notes
:
1.
C
2. T
F
t
h
o
u
e
x
o
u
3. L
4. I
n
5. L
be
X
1671D3BCL
i
sar Corporati
o
Pin Desc
r
Symbol
V
EET
T
FAULT
T
DIS
SDA
SCL
MOD_AB
RS0
RX_LOS
RS1
V
EER
V
EER
RD-
RD+
V
EER
V
CCR
V
CCT
V
EET
TD+
TD-
V
EET
:
C
ircuit groun
d
i
F
AULT
is an op
e
h
e host board i
f
u
tput indicates
x
ceeding the p
r
u
tput is pulled
aser output di
s
n
ternally pulle
d
OS is open co
l
e
tween 2.0V a
n
Fi
g
ure
SFP+ ER/E
W
o
n - February
2
r
iptions
Transmi
t
Transmi
t
Transmi
t
2-wire S
2-wire S
S Module
A
Rate Sel
e
Loss of
S
Rate Sel
e
Receive
r
Receive
r
Receive
r
Receive
r
Receive
r
Receive
r
Transmi
t
Transmi
t
Transmi
t
Transmi
t
Transmi
t
i
s internally is
o
e
n collector/dr
a
f
intended for
u
a transmitter
f
r
eset alarm thr
to <0.8V.
s
abled on T
DIS
>
d
down per SF
F
l
lector output.
n
d 3.6V. Logi
c
1. Dia
g
ram
o
Towards
Bezel
W
Preliminary
S
2
011
t
ter Groun
d
t
ter Faul
t
t
ter Disable. L
a
erial Interface
erial Interface
A
bsent. Grou
n
e
ct 0.
S
ignal indicati
o
e
ct 1.
r
Groun
d
r
Groun
d
r
Inverted DA
T
r
Non-inverted
r
Ground
r
Power Suppl
y
t
ter Power Su
p
t
ter Ground
t
ter Non-Inver
t
t
ter Inverted
D
t
ter Ground
o
lated from ch
a
a
in output, whi
u
se. Pull up v
o
f
ault caused b
y
esholds. A lo
w
>
2.0V or ope
n
F
-8431 Rev 4.
Should be pu
l
c
0 indicates n
o
o
f Host Board
V
V
T
S
S
M
R
R
1
2
3
4
5
6
7
8
9
10
T
R
S
pecification –
Rev. A0
Name/D
e
a
ser output di
s
Data Line
Clock Line
n
ded within th
e
o
n. Logic 0 i
n
T
A out. AC C
o
DATA out.
A
y
p
ply
t
ed DATA in.
D
ATA in. AC
C
a
ssis ground.
ch should be
p
o
ltage should b
e
y
either the T
X
w
output indic
a
n
, enabled on
T
1.
l
led up with 4.
7
o
rmal operatio
n
Connector B
l
VeeT
VeeT
VeeR
VeeR
TD-
TD+
RD+
RD-
VccT
VccR
V
eeT
V
eeR
T
X_Fault
S
D
A
S
CL
M
OD_ABS
R
S0
R
X_LOS
T
X_Disable
R
S1
February 201
1
e
scription
s
abled on high
e
module
n
dicates norma
l
o
upled.
A
C Coupled.
AC Coupled.
C
oupled.
p
ulled up with
a
e
between 2.0
V
X
bias current o
a
tes normal op
e
T
DIS
<0.8V.
7
k – 10kΩ on
h
n
; logic 1 indi
c
l
ock Pin Num
b
20
19
18
17
16
15
14
13
12
11
Tow
a
A
S
I
1
or open.
l
operation.
a
4.7k – 10k
O
V
to Vcc + 0.3
V
r the TX outp
u
e
ration. In the
l
h
ost board to
a
c
ates loss of si
g
b
ers and Na
m
a
rds
I
C
Page
R
O
hms resistor o
V
. A high
u
t power
l
ow state, the
a
voltage
g
nal.
m
es.
2
R
ef.
1
2
3
2
2
2
4
5
4
1
1
1
1
1
n
FTL
X
© Fin
i
II.
A
Exce
Maxi
m
Stora
g
Relati
v
1.
N
III.
Suppl
y
Suppl
y
Tran
s
Input
d
Diffe
r
Trans
m
Trans
m
Recei
v
Diffe
r
Outp
u
LOS
F
LOS
N
Powe
r
Notes
:
1.
C
2. I
n
3. 2
0
f
o
4. L
o
p
5. S
e
6. T
h
u
s
t
h
IV.
Tran
s
Optic
a
(OM
A
Aver
a
Optic
a
Side-
M
Optic
a
Trans
m
Aver
a
trans
m
Tx Jit
t
Relati
v
X
1671D3BCL
i
sar Corporati
o
A
bsolute
M
eding the li
m
P
a
m
um Supply
V
g
e Temperatur
e
v
e Humidity
N
on-condensin
g
Electrical
Pa
r
y
Voltage
y
Curren
t
s
mitter
d
ifferential im
p
r
ential data inp
u
m
it Disable V
o
m
it Enable Vo
l
v
er
r
ential data out
p
u
t rise time an
d
F
aul
t
N
ormal
r
Supply
N
ois
e
:
C
onnected dire
c
n
to 100Ω diffe
r
0
– 80%. Me
a
o
ur 0’s sequen
c
OS is an open
p
eration is log
i
e
e Section 2.8
.
h
e FTLX1671
D
s
ing an EDC
P
h
e hos
t
-
b
oard
E
Optical
C
Param
e
s
mitter
a
l Modulation
A
A
) minus TDP
a
ge Launch Po
w
a
l Wavelength
M
ode Suppres
s
a
l Extinction
R
m
itter and Dis
p
a
ge Launch po
w
m
itte
r
t
e
r
v
e Intensity N
o
SFP+ ER/E
W
o
n - February
2
M
aximum R
a
m
its below
m
a
rameter
V
oltage
e
g
.
Character
i
r
ameter
p
edance
u
t swing
o
ltage
l
tage
p
ut swing
d
fall time
e
Tolerance
c
tly to TX dat
a
r
ential termin
a
a
sured with M
o
c
e in the PRB
S
collector outp
u
i
c 0; loss of si
g
.
4 of SFF-843
1
D
3BTL is a “l
i
P
HY IC should
E
DC PHY wit
h
C
haracteris
t
e
ter
A
mplitude
w
e
r
s
ion Ratio
R
atio
p
ersion Penalt
y
w
er of OFF
o
ise
W
Preliminary
S
2
011
a
tin
g
s
m
ay damage
i
stics
(T
OP
=
-
V
a
input pins. A
a
tion.
o
dule Complia
n
S
9 is an accep
t
u
t. Should be
p
g
nal is logic 1.
1
Rev 4.1.
i
miting modul
e
follow the IC
h
a limiting re
c
t
ics
(T
OP
= -4
S
y
mbo
l
P
OMA-TD
P
P
AVE
λ
SMSR
ER
y
TDP
P
OFF
Tx
j
RIN
S
pecification –
Rev. A0
the transcei
Symbol
Vcc
T
S
RH
-
40 to 85 °C,
V
Symbol
Vcc
Icc
R
in
Vin,pp
V
D
V
EN
Vout,pp
T
r
, T
f
V
LOS faul
t
V
LOS norm
V
ccT/VccR
C coupling fr
o
n
ce Test Boar
d
t
able alternati
v
p
ulled up wit
h
e
”, i.e., it emp
l
manufacturer’
c
eiver SFP+ m
o
0 to 85 °C, V
C
l
Min
P
-2.1
-4.7
1530
30
3.0
February 201
1
ver module
Min T
yp
-0.5
-40
0
V
CC
= 3.14 to
3
Min T
yp
3.14
27
0
10
0
180
2
Vee
300
28
2
Vee
Per SFF-84
o
m pins into la
s
d
and OMA te
s
v
e.
h
4.7
k
Ω – 10k
Ω
l
oys a limiting
s recommend
e
o
dule.
C
C3
= 3.14 to 3
.
Typ
Per 802.3ae r
e
1
permanentl
y
p
Max
4.0
85
85
3
.46 Volts)
p
Max
3.46
0
400
0
700
Vcc
Vee+ 0.8
850
Vcc
HOST
Vee+0.8
31 Rev 4.1
s
er driver IC.
s
t pattern. Use
Ω
on the host
b
receiver. Hos
e
d settings for
i
.
46 Volts)
Max
+4.0
1565
3.0
-30
e
quirements
-128
Page
y
.
Unit
R
V
°C
%
Unit
R
V
mA
Ω
mV
V
V
mV
ps
V
V
mVpp
of four 1’s an
d
b
oard. Normal
t board design
e
i
nteroperating
Unit Re
f
dBm
dBm 1
nm
dB
dB
dB
dBm
dB/Hz
3
R
ef.
1
R
ef.
1
2,6
3
4
4
5
d
e
rs
f
.
FTL
X
© Fin
i
Recei
v
Recei
v
@ 10.
Stress
(OM
A
Aver
a
Dama
g
Optic
a
Recei
v
LOS
D
LOS
A
LOS
H
Notes
:
1.
A
tr
n
o
2.
V
3.
V
4.
A
V.
Bit R
a
Bit Er
r
Max.
S
Notes
:
1. 1
0
2. T
3. S
M
Pow
e
The
F
abov
e
AN-
2
II po
w
Tim
i
Time
t
Notes
:
1.
M
t
_
X
1671D3BCL
i
sar Corporati
o
v
er
v
er Sensitivity
3 Gb/s
ed Receiver S
e
A
) @ 10.3 Gb/
s
a
ge Receive Po
g
e Threshol
d
a
l Center Wav
e
v
er Reflectanc
e
D
e-Assert
A
sser
t
H
ysteresis
:
A
verage launch
ansmitter wit
h
o
t ensure com
p
V
alid between
1
V
alid between
1
A
verage power
General S
p
Para
m
a
te
r
or Ratio
S
upported Lin
k
:
0
GBASE-ER,
ested with a 2
3
M
F-28 fiber, 1
e
r Level I/
P
F
TLX1671
D
e
1W at hig
h
2
076 for det
a
w
e
r
-up seq
u
i
n
g
Parame
t
Parame
t
t
o initialize co
o
:
M
ore details on
_
on = 3 secon
d
SFP+ ER/E
W
o
n - February
2
(OMA)
e
nsitivity
s
we
r
e
length
e
power (min) i
h
launch power
p
liance.
1
530 and 1565
1
530 and 1565
figures are in
fo
p
ecification
s
m
eter
k
Length
10GBASE-E
W
3
1
– 1 PRBS.
565nm wavel
e
P
ower Level
D
3BTL is a
P
h
temperatu
r
a
ils of the h
o
u
ence to ens
u
t
ers
t
er
o
led module
Timing Para
m
d
s.
W
Preliminary
S
2
011
R
SENS1
R
SENS2
P
AVE
λ
C
R
rx
LOS
D
LOS
A
s informative
a
below this va
l
nm. Measure
d
nm. Per IEEE
fo
rmative only,
s
S
y
mbo
l
BR
BER
L
MAX
W
.
e
ngth.
II Power-
u
P
ower Leve
l
r
e. Please r
e
o
st responsi
b
u
re proper tr
a
S
y
mbo
l
t_start_up_c
o
m
eters can be f
o
S
pecification –
Rev. A0
-15.8
1260
-28
0.5
a
nd not the pri
n
l
ue cannot be
c
d
with worst E
R
802.3ae.
per IEEE 802
l
Min
9.95
u
p Sequenc
e
l
II device, a
e
fer to SFF-
8
b
ilities rega
r
a
nsceiver o
p
l
Min
o
oled
o
und in SFF-8
4
February 201
1
n
cipal indicat
o
c
ompliant; ho
w
R
; BER<10
-12
;
.3ae.
Typ
40
e
s the maxi
m
8
431 and Fi
n
r
ding the Po
w
p
eration.
Typ
60
4
31. Maximu
m
1
-14.1
-11.3
-1.0
+4
1600
-26
-19
o
r of signal str
e
w
ever, a value
a
2
31
– 1 PRBS
.
Max
10.3
10
-12
m
um power
d
n
isar Applic
a
w
er Level I/
P
Max
90
m
Tx_Disable
n
Page
dBm 2
dBm 3
dBm 4
dBm
nm
dB
dBm
dBm
dB
e
ngth. A
a
bove this doe
s
.
Units Re
f
Gb/s
1
2
km
3
d
issipation i
s
a
tion Note
P
ower Leve
Units Re
f
s
1
n
egate time
4
s
f
.
s
l
f
.
FTL
X
© Fin
i
VI.
E
Finis
to +
8
Case
O
Stora
g
VII.
Finis
Thes
e
requ
i
EN (
I
VIII
.
Finis
prot
o
the
G
The
s
the t
r
Addi
t
inter
f
trans
c
pow
e
warn
a fac
t
The
S
2-wi
r
mon
i
defi
n
thus
f
Sour
c
2030
The
o
Diag
n
thro
u
sign
a
SFP
t
nega
t
X
1671D3BCL
i
sar Corporati
o
E
nvironme
ar FTLX16
7
8
5°C case te
m
Para
m
O
perating Te
m
g
e Temperatur
e
Re
g
ulat
o
ar transceiv
e
e
products a
r
i
rements of
E
I
EC) 60950.
.
Di
g
ital
D
ar FTLX16
7
o
col as defin
e
G
BIC standa
r
s
tandard SF
P
r
ansceiver’s
t
ionally, Fi
n
f
ace, which
a
c
eiver temp
e
e
r and trans
c
ing flags, w
h
t
ory set nor
m
S
FP MSA d
e
r
e serial inte
r
i
toring inter
f
n
ed serial ID
f
ully backw
a
c
e Agreeme
n
: “Digital D
i
o
perating an
n
ostics Tra
n
u
gh a 2-wire
a
l (SCL, Mo
d
t
ransceiver
i
t
ive edge cl
o
SFP+ ER/E
W
o
n - February
2
ntal Specif
i
7
1D3BTL tr
a
m
perature.
m
eter
m
perature
e
o
r
y
Compli
a
e
rs are Clas
s
r
e certified
b
E
N (IEC) 6
0
Copies of
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Finisar FTLX1671D3BTL Datasheet

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FTLX1671D3BTL
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Network transceiver modules
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