Texas Instruments TMS320C5517 Digital Signal Processor (Rev. B) User guide

Texas Instruments
Brand
Texas Instruments
Model
TMS320C5517 Digital Signal Processor (Rev. B)
Type
User guide
TMS320C5517 Digital Signal Processor
Technical Reference Manual
Literature Number: SPRUH16B
April 2014–Revised October 2015
Contents
Preface....................................................................................................................................... 50
Revision History.......................................................................................................................... 52
1 System Control .................................................................................................................. 53
1.1 Introduction.................................................................................................................. 54
1.1.1 Block Diagram ..................................................................................................... 54
1.1.2 CPU Core .......................................................................................................... 54
1.1.3 FFT Hardware Accelerator....................................................................................... 55
1.1.4 Power Management............................................................................................... 56
1.1.5 Peripherals ......................................................................................................... 56
1.2 System Memory ............................................................................................................ 57
1.2.1 Program/Data Memory Map ..................................................................................... 57
1.2.2 I/O Memory Map................................................................................................... 61
1.3 Device Clocking ............................................................................................................ 61
1.3.1 Overview............................................................................................................ 61
1.3.2 Clock Domains..................................................................................................... 64
1.4 System Clock Generator .................................................................................................. 64
1.4.1 Overview............................................................................................................ 64
1.4.2 Functional Description............................................................................................ 65
1.4.3 Configuration....................................................................................................... 67
1.4.4 Clock Generator Registers....................................................................................... 72
1.5 Power Management........................................................................................................ 79
1.5.1 Overview............................................................................................................ 79
1.5.2 Power Domains.................................................................................................... 79
1.5.3 Clock Management ............................................................................................... 80
1.5.4 Static Power Management ...................................................................................... 95
1.5.5 Power Configurations ........................................................................................... 101
1.6 Interrupts................................................................................................................... 105
1.6.1 IFR and IER Registers .......................................................................................... 105
1.6.2 Interrupt Timing .................................................................................................. 107
1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h]............................................... 108
1.6.4 GPIO Interrupt Enable and Aggregation Flag Registers.................................................... 109
1.6.5 DMA Interrupt Enable and Aggregation Flag Registers .................................................... 109
1.6.6 McSPI Interrupt Aggregation Flag Register .................................................................. 109
1.6.7 McSPI Interrupt Aggregation Enable Register............................................................... 111
1.7 System Configuration and Control...................................................................................... 112
1.7.1 Overview.......................................................................................................... 112
1.7.2 Device Identification............................................................................................. 112
1.7.3 Device Configuration ............................................................................................ 118
1.7.4 DMA Controller Configuration.................................................................................. 137
1.7.5 Peripheral Reset ................................................................................................. 141
1.7.6 EMIF and USB Byte Access ................................................................................... 143
1.7.7 EMIF Clock Divider Register (ECDR) [1C26h]............................................................... 145
1.7.8 McSPI Functional Clock Divider Register (MSPIFCDR) [1C3Ch]......................................... 146
1.7.9 UHPI Configuration Register (UHPICR) [1C4Eh]............................................................ 147
1.7.10 BootMode Register (BMR) [1C34h] .......................................................................... 148
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1.8 System Module Registers ............................................................................................... 149
2 FFT Implementation .......................................................................................................... 151
2.1 Introduction ................................................................................................................ 152
2.2 Basics of DFT and FFT .................................................................................................. 152
2.2.1 Radix-2 Decimation in Time Equations ....................................................................... 152
2.2.2 Radix-2 DIT Butterfly ............................................................................................ 153
2.2.3 Computational Complexity...................................................................................... 154
2.2.4 FFT Graphs....................................................................................................... 155
2.3 DSP Overview Including the FFT Accelerator ........................................................................ 156
2.4 FFT Hardware Accelerator Description................................................................................ 157
2.4.1 Tightly-Coupled Hardware Accelerator ....................................................................... 157
2.4.2 Hardware Butterfly, Double-Stage and Single-Stage Mode................................................ 157
2.4.3 Pipeline and Latency ............................................................................................ 157
2.4.4 Software Control ................................................................................................. 158
2.4.5 Twiddle Factors .................................................................................................. 158
2.4.6 Scaling ............................................................................................................ 158
2.5 HWAFFT Software Interface ............................................................................................ 159
2.5.1 Data Types ....................................................................................................... 159
2.5.2 HWAFFT Functions.............................................................................................. 159
2.5.3 Bit Reverse Function ............................................................................................ 161
2.5.4 Function Descriptions and ROM Locations................................................................... 164
2.5.5 Project Configuration for Calling Functions from ROM ..................................................... 164
2.6 Simple Example to Illustrate the Use of the FFT Accelerator....................................................... 165
2.6.1 1024-Point FFT, Scaling Disabled............................................................................. 165
2.6.2 1024-Point IFFT, Scaling Disabled............................................................................ 166
2.6.3 Graphing FFT Results in CCS4................................................................................ 166
2.7 FFT Benchmarks.......................................................................................................... 167
2.8 Computation of Large (Greater Than 1024-Point) FFTs............................................................. 169
2.8.1 Procedure for Computing Large FFTs ........................................................................ 169
2.8.2 Twiddle Factor Computation ................................................................................... 169
2.8.3 Bit-Reverse Separates Even and Odd Indexes.............................................................. 169
2.8.4 2048-point FFT Source Code .................................................................................. 169
2.9 Appendix A Methods for Aligning the Bit-Reverse Destination Vector............................................. 171
2.9.1 Statically Allocate Buffer at Beginning of Suitable RAM Block ............................................ 171
2.9.2 Use the ALIGN Descriptor to Force log
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(4 * N) Zeros in the Least Significant Bits..................... 172
2.9.3 Use the DATA_ALIGN Pragma................................................................................ 172
3 Direct Memory Access (DMA) Controller.............................................................................. 173
3.1 Introduction ................................................................................................................ 174
3.1.1 Purpose of the DMA Controller ................................................................................ 174
3.1.2 Key Features of the DMA Controller .......................................................................... 174
3.1.3 Block Diagram of the DMA Controller......................................................................... 175
3.2 DMA Controller Architecture............................................................................................. 176
3.2.1 Clock Control..................................................................................................... 176
3.2.2 Memory Map ..................................................................................................... 177
3.2.3 DMA Channels................................................................................................... 177
3.2.4 Channel Source and Destination Start Addresses .......................................................... 179
3.2.5 Updating Addresses in a Channel............................................................................. 181
3.2.6 Data Burst Capability............................................................................................ 182
3.2.7 Synchronizing Channel Activity to DSP Peripheral Events................................................. 182
3.2.8 Channel Auto-Initialization Capability ......................................................................... 183
3.2.9 Ping-Pong DMA Mode .......................................................................................... 183
3.2.10 Monitoring Channel Activity ................................................................................... 184
3.2.11 Latency in DMA Transfers..................................................................................... 185
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3.2.12 Reset Considerations .......................................................................................... 185
3.2.13 Initialization ...................................................................................................... 186
3.2.14 Interrupt Support................................................................................................ 187
3.2.15 Power Management............................................................................................ 187
3.2.16 Emulation Considerations ..................................................................................... 187
3.3 DMA Transfer Examples................................................................................................. 187
3.3.1 Block Move Example............................................................................................ 187
3.3.2 Peripheral Servicing Example.................................................................................. 188
3.3.3 Ping-Pong DMA Example....................................................................................... 190
3.4 Registers................................................................................................................... 192
3.4.1 Source Start Address Registers (DMACHmSSAL and DMACHmSSAU)................................ 195
3.4.2 Destination Start Address Registers (DMACHmDSAL and DMACHmDSAU)........................... 196
3.4.3 Transfer Control Registers (DMACHmTCRL and DMACHmTCRU)...................................... 197
4 External Memory Interface (EMIF)....................................................................................... 200
4.1 Introduction ................................................................................................................ 201
4.1.1 Purpose of the External Memory Interface................................................................... 201
4.1.2 Features........................................................................................................... 201
4.1.3 Functional Block Diagram ...................................................................................... 203
4.2 Architecture................................................................................................................ 203
4.2.1 Clock Control..................................................................................................... 203
4.2.2 EMIF Requests................................................................................................... 204
4.2.3 Memory Map ..................................................................................................... 205
4.2.4 Signal Descriptions .............................................................................................. 205
4.2.5 Pin Multiplexing .................................................................................................. 206
4.2.6 SDRAM Controller and Interface .............................................................................. 206
4.2.7 Asynchronous Controller and Interface....................................................................... 219
4.2.8 BYTEMODE Bits of The EMIF System Control Register................................................... 238
4.2.9 Data Bus Parking ................................................................................................ 239
4.2.10 Priority and Arbitration ......................................................................................... 239
4.2.11 System Considerations ........................................................................................ 240
4.2.12 Reset Considerations .......................................................................................... 240
4.2.13 Initialization ..................................................................................................... 241
4.2.14 Interrupt Support................................................................................................ 241
4.2.15 DMA Event Support ............................................................................................ 242
4.2.16 Power Management............................................................................................ 242
4.2.17 Emulation Considerations ..................................................................................... 243
4.2.18 CPU Instruction Pipeline Considerations.................................................................... 243
4.3 Interfacing the EMIF to Mobile SDRAM ............................................................................... 244
4.3.1 Hardware Interface .............................................................................................. 244
4.3.2 SW Configuration................................................................................................ 245
4.4 EMIF Registers............................................................................................................ 248
4.4.1 REV Register (offset = 1000h) [reset = 205h] ............................................................... 250
4.4.2 STATUS Register (offset = 1001h) [reset = C000h] ........................................................ 251
4.4.3 AWCCR1 Register (offset = 1004h) [reset = 40h]........................................................... 252
4.4.4 AWCCR2 Register (offset = 1005h) [reset = F0E4h] ....................................................... 253
4.4.5 SDCR1 Register (offset = 1008h) [reset = 620h]............................................................ 255
4.4.6 SDCR2 Register (offset = 1009h) [reset = 0h]............................................................... 257
4.4.7 SDRCR Register (offset = 100Ch) [reset = 7Dh]............................................................ 259
4.4.8 ACS2CR1 Register (offset = 1010h) [reset = 7FFCh] ...................................................... 260
4.4.9 ACS2CR2 Register (offset = 1011h) [reset = 3FFFh]....................................................... 261
4.4.10 ACS3CR1 Register (offset = 1014h) [reset = 7FFDh] ..................................................... 262
4.4.11 ACS3CR2 Register (offset = 1015h) [reset = 3FFFh]...................................................... 263
4.4.12 ACS4CR1 Register (offset = 1018h) [reset = 7FFCh] ..................................................... 264
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4.4.13 ACS4CR2 Register (offset = 1019h) [reset = 3FFFh]...................................................... 265
4.4.14 ACS5CR1 Register (offset = 101Ch) [reset = 7FFDh]..................................................... 266
4.4.15 ACS5CR2 Register (offset = 101Dh) [reset = 3FFFh] ..................................................... 267
4.4.16 SDTIMR1 Register (offset = 1020h) [reset = 5820h]....................................................... 268
4.4.17 SDTIMR2 Register (offset = 1021h) [reset = 4221h]....................................................... 269
4.4.18 SDSRETR Register (offset = 103Ch) [reset = 5h].......................................................... 270
4.4.19 EIRR Register (offset = 1040h) [reset = 0h] ................................................................ 271
4.4.20 EIMR Register (offset = 1044h) [reset = 0h] ................................................................ 272
4.4.21 EIMSR Register (offset = 1048h) [reset = 0h] .............................................................. 273
4.4.22 EIMCR Register (offset = 104Ch) [reset = 0h].............................................................. 274
4.4.23 NANDFCR Register ............................................................................................ 275
4.4.24 NANDFSR1 Register (offset = 1064h) [reset = 0h] ........................................................ 277
4.4.25 NANDFSR2 Register (offset = 1065h) [reset = 0h] ........................................................ 278
4.4.26 PAGEMODCTRL1 Register (offset = 1068h) [reset = FCFEh]........................................... 279
4.4.27 PAGEMODCTRL2 Register (offset = 1069h) [reset = FCFCh]........................................... 280
4.4.28 NCS2ECC1 Register (offset = 1070h) [reset = 0h]......................................................... 281
4.4.29 NCS2ECC2 Register (offset = 1071h) [reset = 0h]......................................................... 283
4.4.30 NCS3ECC1 Register (offset = 1074h) [reset = 0h]......................................................... 285
4.4.31 NCS3ECC2 Register (offset = 1075h) [reset = 0h]......................................................... 287
4.4.32 NCS4ECC1 Register (offset = 1078h) [reset = 0h]......................................................... 289
4.4.33 NCS4ECC2 Register (offset = 1079h) [reset = 0h]......................................................... 291
4.4.34 NCS5ECC1 Register (offset = 107Ch) [reset = 0h] ........................................................ 293
4.4.35 NCS5ECC2 Register (offset = 107Dh) [reset = 0h] ........................................................ 295
4.4.36 NAND4BITECCLOAD Register (offset = 10BCh) [reset = 0h]............................................ 297
4.4.37 NAND4BITECC1 Register (offset = 10C0h) [reset = 0h].................................................. 298
4.4.38 NAND4BITECC2 Register (offset = 10C1h) [reset = 0h].................................................. 299
4.4.39 NAND4BITECC3 Register (offset = 10C4h) [reset = 0h].................................................. 300
4.4.40 NAND4BITECC4 Register (offset = 10C5h) [reset = 0h].................................................. 301
4.4.41 NAND4BITECC5 Register (offset = 10C8h) [reset = 0h].................................................. 302
4.4.42 NAND4BITECC6 Register (offset = 10C9h) [reset = 0h].................................................. 303
4.4.43 NAND4BITECC7 Register (offset = 10CCh) [reset = 0h].................................................. 304
4.4.44 NAND4BITECC8 Register (offset = 10CDh) [reset = 0h].................................................. 305
4.4.45 NANDERRADD1 Register (offset = 10D0h) [reset = 0h].................................................. 306
4.4.46 NANDERRADD2 Register (offset = 10D1h) [reset = 0h].................................................. 307
4.4.47 NANDERRADD3 Register (offset = 10D4h) [reset = 0h].................................................. 308
4.4.48 NANDERRADD4 Register (offset = 10D5h) [reset = 0h].................................................. 309
4.4.49 NANDERRVAL1 Register (offset = 10D8h) [reset = 0h]................................................... 310
4.4.50 NANDERRVAL2 Register (offset = 10D9h) [reset = 0h]................................................... 311
4.4.51 NANDERRVAL3 Register (offset = 10DCh) [reset = 0h] .................................................. 312
4.4.52 NANDERRVAL4 Register (offset = 10DDh) [reset = 0h] .................................................. 313
5 General-Purpose Input/Output (GPIO) ................................................................................. 314
5.1 Introduction ................................................................................................................ 315
5.1.1 Purpose of the Peripheral....................................................................................... 315
5.1.2 Features........................................................................................................... 315
5.1.3 Industry Standard(s) Compliance Statement................................................................. 315
5.2 Peripheral Architecture................................................................................................... 315
5.2.1 Clock Control..................................................................................................... 315
5.2.2 Signal Descriptions .............................................................................................. 315
5.2.3 GPIO Register Structure........................................................................................ 315
5.2.4 Using a GPIO Signal as an Output............................................................................ 316
5.2.5 Using a GPIO Signal as an Input.............................................................................. 316
5.2.6 Reset Considerations ........................................................................................... 316
5.2.7 Interrupt Support................................................................................................. 317
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5.3 GPIO Registers ........................................................................................................... 317
5.3.1 IODIR1 Register (offset = 1C06h) [reset = 0h]............................................................... 319
5.3.2 IODIR2 Register (offset = 1C07h) [reset = 0h]............................................................... 320
5.3.3 IOINDATA1 Register (offset = 1C08h) [reset = 0h] ......................................................... 321
5.3.4 IOINDATA2 Register (offset = 1C09h) [reset = 0h] ......................................................... 322
5.3.5 IODATAOUT1 Register (offset = 1C0Ah) [reset = 0h]...................................................... 323
5.3.6 IODATAOUT2 Register (offset = 1C0Bh) [reset = 0h]...................................................... 324
5.3.7 IOINTEDG1 Register (offset = 1C0Ch) [reset = 0h]......................................................... 325
5.3.8 IOINTEDG2 Register (offset = 1C0Dh) [reset = 0h]......................................................... 326
5.3.9 IOINTEN1 Register (offset = 1C0Eh) [reset = 0h]........................................................... 327
5.3.10 IOINTEN2 Register (offset = 1C0Fh) [reset = 0h].......................................................... 328
5.3.11 IOINTFLG1 Register (offset = 1C10h) [reset = 0h]......................................................... 329
5.3.12 IOINTFLG2 Register (offset = 1C11h) [reset = 0h]......................................................... 330
6 Inter-Integrated Circuit (I2C) Peripheral ............................................................................... 331
6.1 Introduction ................................................................................................................ 332
6.1.1 Purpose of the Peripheral....................................................................................... 332
6.1.2 Features........................................................................................................... 332
6.1.3 Functional Block Diagram ...................................................................................... 333
6.1.4 Industry Standard(s) Compliance Statement................................................................. 333
6.2 Peripheral Architecture................................................................................................... 334
6.2.1 Bus Structure..................................................................................................... 334
6.2.2 Clock Generation ................................................................................................ 335
6.2.3 Clock Synchronization........................................................................................... 336
6.2.4 Signal Descriptions .............................................................................................. 336
6.2.5 START and STOP Conditions ................................................................................. 337
6.2.6 Serial Data Formats ............................................................................................. 338
6.2.7 Operating Modes................................................................................................. 339
6.2.8 NACK Bit Generation............................................................................................ 340
6.2.9 NACK Response................................................................................................. 341
6.2.10 Arbitration........................................................................................................ 341
6.2.11 Reset Considerations .......................................................................................... 342
6.2.12 Initialization ...................................................................................................... 342
6.2.13 Interrupt Support................................................................................................ 344
6.2.14 DMA Events Generated by the I2C Peripheral ............................................................. 345
6.2.15 Power Management............................................................................................ 345
6.2.16 Emulation Considerations ..................................................................................... 346
6.3 I2C Registers.............................................................................................................. 346
6.3.1 ICOAR Register (offset = 1A00h) [reset = 0h] ............................................................... 347
6.3.2 ICIMR Register (offset = 1A04h) [reset = 0h]................................................................ 348
6.3.3 ICSTR Register (offset = 1A08h) [reset = 410h]............................................................. 349
6.3.4 ICCLKL Register (offset = 1A0Ch) [reset = 0h].............................................................. 353
6.3.5 ICCLKH Register (offset = 1A10h) [reset = 0h].............................................................. 354
6.3.6 ICCNT Register (offset = 1A14h) [reset = 0h] ............................................................... 355
6.3.7 ICDRR Register (offset = 1A18h) [reset = 0h] ............................................................... 356
6.3.8 ICSAR Register (offset = 1A1Ch) [reset = 3FFh]............................................................ 357
6.3.9 ICDXR Register (offset = 1A20h) [reset = 0h] ............................................................... 358
6.3.10 ICMDR Register (offset = 1A24h) [reset = 0h].............................................................. 359
6.3.11 ICIVR Register (offset = 1A28h) [reset = 0h] ............................................................... 362
6.3.12 ICEMDR Register (offset = 1A2Ch) [reset = 1h]............................................................ 363
6.3.13 ICPSC Register (offset = 1A30h) [reset = 0h] .............................................................. 364
6.3.14 ICPID1 Register (offset = 1A34h) [reset = 106h]........................................................... 365
6.3.15 ICPID2 Register (offset = 1A38h) [reset = 5h].............................................................. 366
7 Inter-IC Sound (I2S) Bus.................................................................................................... 367
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7.1 Introduction ............................................................................................................... 368
7.1.1 Purpose of the Peripheral....................................................................................... 368
7.1.2 Features........................................................................................................... 368
7.1.3 Functional Block Diagram ...................................................................................... 368
7.1.4 Industry Standard(s) Compliance.............................................................................. 369
7.2 Architecture................................................................................................................ 370
7.2.1 Clock Control..................................................................................................... 370
7.2.2 I2S Clock Generator............................................................................................. 370
7.2.3 Signal and Pin Descriptions .................................................................................... 371
7.2.4 Frame Clock Timing Requirement in Slave Mode........................................................... 372
7.2.5 Protocol Description............................................................................................. 374
7.2.6 I2S Data Transfer and Control Behavior...................................................................... 376
7.2.7 I2S Data Transfer Latency...................................................................................... 377
7.2.8 Data Packing and Sign Extension Options................................................................... 377
7.2.9 Reset Considerations ........................................................................................... 382
7.2.10 Interrupt Support................................................................................................ 382
7.2.11 DMA Event Support ............................................................................................ 383
7.2.12 Power Management............................................................................................ 383
7.2.13 Emulation Considerations ..................................................................................... 383
7.2.14 After Frame Sync ............................................................................................... 384
7.2.15 Steps for I2S Configuration and I2S Interrupt Service Routine (ISR) ................................... 384
7.3 I2S0 Registers............................................................................................................. 385
7.3.1 I2S0SCTRL Register (offset = 2800h) [reset = 0h].......................................................... 386
7.3.2 I2S0SRATE Register (offset = 2804h) [reset = 0h] ......................................................... 388
7.3.3 I2S0TXLT1 Register (offset = 2808h) [reset = 0h] .......................................................... 389
7.3.4 I2S0TXLT2 Register (offset = 2809h) [reset = 0h] .......................................................... 390
7.3.5 I2S0TXRT1 Register (offset = 280Ch) [reset = 0h] ......................................................... 391
7.3.6 I2S0TXRT2 Register (offset = 280Dh) [reset = 0h] ......................................................... 392
7.3.7 I2S0INTFL Register (offset = 2810h) [reset = 0h]........................................................... 393
7.3.8 I2S0INTMASK Register (offset = 2814h) [reset = 0h] ...................................................... 394
7.3.9 I2S0RXLT1 Register (offset = 2828h) [reset = 0h].......................................................... 395
7.3.10 I2S0RXLT2 Register (offset = 2829h) [reset = 0h]......................................................... 396
7.3.11 I2S0RXRT1 Register (offset = 282Ch) [reset = 0h] ........................................................ 397
7.3.12 I2S0RXRT2 Register (offset = 282Dh) [reset = 0h] ........................................................ 398
7.4 I2S2 Registers............................................................................................................. 399
7.4.1 I2S2SCTRL Register (offset = 2A00h) [reset = 0h] ......................................................... 400
7.4.2 I2S2SRATE Register (offset = 2A04h) [reset = 0h] ......................................................... 402
7.4.3 I2S2TXLT1 Register (offset = 2A08h) [reset = 0h].......................................................... 403
7.4.4 I2S2TXLT2 Register (offset = 2A09h) [reset = 0h].......................................................... 404
7.4.5 I2S2TXRT1 Register (offset = 2A0Ch) [reset = 0h] ......................................................... 405
7.4.6 I2S2TXRT2 Register (offset = 2A0Dh) [reset = 0h] ......................................................... 406
7.4.7 I2S2INTFL Register (offset = 2A10h) [reset = 0h]........................................................... 407
7.4.8 I2S2INTMASK Register (offset = 2A14h) [reset = 0h] ...................................................... 408
7.4.9 I2S2RXLT1 Register (offset = 2A28h) [reset = 0h].......................................................... 409
7.4.10 I2S2RXLT2 Register (offset = 2A29h) [reset = 0h]......................................................... 410
7.4.11 I2S2RXRT1 Register (offset = 2A2Ch) [reset = 0h]........................................................ 411
7.4.12 I2S2RXRT2 Register (offset = 2A2Dh) [reset = 0h]........................................................ 412
7.5 I2S3 Registers............................................................................................................. 413
7.5.1 I2S3SCTRL Register (offset = 2B00h) [reset = 0h] ......................................................... 414
7.5.2 I2S3SRATE Register (offset = 2B04h) [reset = 0h] ......................................................... 416
7.5.3 I2S3TXLT1 Register (offset = 2B08h) [reset = 0h].......................................................... 417
7.5.4 I2S3TXLT2 Register (offset = 2B09h) [reset = 0h].......................................................... 418
7.5.5 I2S3TXRT1 Register (offset = 2B0Ch) [reset = 0h] ......................................................... 419
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7.5.6 I2S3TXRT2 Register (offset = 2B0Dh) [reset = 0h] ......................................................... 420
7.5.7 I2S3INTFL Register (offset = 2B10h) [reset = 0h]........................................................... 421
7.5.8 I2S3INTMASK Register (offset = 2B14h) [reset = 0h] ...................................................... 422
7.5.9 I2S3RXLT1 Register (offset = 2B28h) [reset = 0h].......................................................... 423
7.5.10 I2S3RXLT2 Register (offset = 2B29h) [reset = 0h]......................................................... 424
7.5.11 I2S3RXRT1 Register (offset = 2B2Ch) [reset = 0h]........................................................ 425
7.5.12 I2S3RXRT2 Register (offset = 2B2Dh) [reset = 0h]........................................................ 426
8 Multichannel Buffered Serial Port (McBSP) Interface............................................................. 427
8.1 Introduction ................................................................................................................ 428
8.1.1 Purpose of the Peripheral....................................................................................... 428
8.1.2 Features........................................................................................................... 428
8.1.3 Functional Block Diagram ...................................................................................... 428
8.1.4 Industry Standard Compliance Statement.................................................................... 429
8.2 Architecture ............................................................................................................... 430
8.2.1 Clock Control..................................................................................................... 430
8.2.2 Signal Descriptions .............................................................................................. 430
8.2.3 Pin Multiplexing .................................................................................................. 430
8.2.4 Endianness Considerations .................................................................................... 430
8.2.5 Clock, Frames, and Data ....................................................................................... 431
8.2.6 McBSP Standard Operation.................................................................................... 445
8.2.7 μ-Law/A-Law Companding Hardware Operation ............................................................ 457
8.2.8 Multichannel Selection Modes ................................................................................. 459
8.2.9 SPI Operation Using the Clock Stop Mode................................................................... 467
8.2.10 Resetting the Serial Port: RRST, XRST, GRST, and RESET ............................................ 467
8.2.11 McBSP Initialization Procedure............................................................................... 468
8.2.12 Interrupt Support................................................................................................ 472
8.2.13 DMA Event Support ............................................................................................ 473
8.2.14 Power Management............................................................................................ 474
8.2.15 IDLE Logic Module ............................................................................................. 474
8.2.16 IDLE Control Signals........................................................................................... 474
8.2.17 Emulation Considerations ..................................................................................... 475
8.3 MCBSP Registers ........................................................................................................ 476
8.3.1 DRRL Register (offset = 4000h) [reset = 0h]................................................................. 477
8.3.2 DRRU Register (offset = 4001h) [reset = 0h] ................................................................ 478
8.3.3 DXRL Register (offset = 4004h) [reset = 0h]................................................................. 479
8.3.4 DXRU Register (offset = 4005h) [reset = 0h] ................................................................ 480
8.3.5 SPCRL Register (offset = 4008h) [reset = 0h]............................................................... 481
8.3.6 SPCRU Register (offset = 4009h) [reset = 0h]............................................................... 483
8.3.7 RCRL Register (offset = 400Ch) [reset = 0h] ................................................................ 484
8.3.8 RCRU Register (offset = 400Dh) [reset = 0h]................................................................ 485
8.3.9 XCRL Register (offset = 4010h) [reset = 0h]................................................................. 486
8.3.10 XCRU Register (offset = 4011h) [reset = 0h] ............................................................... 487
8.3.11 SRGRL Register (offset = 4014h) [reset = 1h].............................................................. 488
8.3.12 SRGRU Register (offset = 4015h) [reset = 2000h]......................................................... 489
8.3.13 MCRL Register (offset = 4018h) [reset = 0h] ............................................................... 490
8.3.14 MCRU Register (offset = 4019h) [reset = 0h]............................................................... 491
8.3.15 RCERA Register (offset = 401Ch) [reset = 0h]............................................................. 493
8.3.16 RCERB Register (offset = 401Dh) [reset = 0h]............................................................. 494
8.3.17 XCERA Register (offset = 4020h) [reset = 0h].............................................................. 495
8.3.18 XCERB Register (offset = 4021h) [reset = 0h].............................................................. 496
8.3.19 PCRL Register (offset = 4024h) [reset = 0h]................................................................ 497
8.3.20 PCRU Register (offset = 4025h) [reset = 0h] ............................................................... 499
8.3.21 RCERC Register (offset = 4028h) [reset = 0h] ............................................................. 500
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8.3.22 RCERD Register (offset = 4029h) [reset = 0h] ............................................................. 501
8.3.23 XCERC Register (offset = 402Ch) [reset = 0h]............................................................. 502
8.3.24 XCERD Register (offset = 402Dh) [reset = 0h]............................................................. 503
8.3.25 RCERE Register (offset = 4030h) [reset = 0h] ............................................................. 504
8.3.26 RCERF Register (offset = 4031h) [reset = 0h].............................................................. 505
8.3.27 XCERE Register (offset = 4034h) [reset = 0h].............................................................. 506
8.3.28 XCERF Register (offset = 4035h) [reset = 0h].............................................................. 507
8.3.29 RCERG Register (offset = 4038h) [reset = 0h] ............................................................. 508
8.3.30 RCERH Register (offset = 4039h) [reset = 0h] ............................................................. 509
8.3.31 XCERG Register (offset = 403Ch) [reset = 0h]............................................................. 510
8.3.32 XCERH Register (offset = 403Dh) [reset = 0h]............................................................. 511
9 Multichannel Serial Port Interface (McSPI) ........................................................................... 512
9.1 Introduction ................................................................................................................ 513
9.2 McSPI Environment ...................................................................................................... 514
9.2.1 McSPI Interface in Master Mode............................................................................... 514
9.2.2 McSPI Interface in Slave Mode................................................................................ 514
9.3 McSPI Functional Interface.............................................................................................. 516
9.3.1 Basic McSPI Pins for Master Mode ........................................................................... 516
9.3.2 Basic McSPI Pins for Slave Mode............................................................................. 516
9.3.3 Multichannel SPI Protocol and Data Format................................................................. 517
9.4 McSPI Functional Description........................................................................................... 521
9.4.1 Master Mode ..................................................................................................... 521
9.4.2 Slave Mode....................................................................................................... 526
9.4.3 FIFO Buffer Management....................................................................................... 529
9.4.4 Interrupts.......................................................................................................... 532
9.4.5 DMA Requests................................................................................................... 535
9.4.6 Power Saving Management.................................................................................... 535
9.5 McSPI Basic Programming Model...................................................................................... 537
9.5.1 Initialization of Modules ......................................................................................... 537
9.5.2 Transfer Procedures without FIFO ............................................................................ 537
9.5.3 Transfer Procedures with FIFO................................................................................ 550
9.6 McSPI Registers .......................................................................................................... 557
9.6.1 REVISIONL Register (offset = 3500h) [reset = 2Bh]........................................................ 559
9.6.2 SYSCONFIGL Register (offset = 3510h) [reset = 15h] ..................................................... 560
9.6.3 SYSSTATUSL Register (offset = 3514h) [reset = 0h] ...................................................... 561
9.6.4 IRQSTATUSL Register (offset = 3518h) [reset = 0h]....................................................... 562
9.6.5 IRQSTATUSU Register (offset = 3519h) [reset = 0h]....................................................... 564
9.6.6 IRQENABLEL Register (offset = 351Ch) [reset = 0h]....................................................... 565
9.6.7 IRQENABLEU Register (offset = 351Dh) [reset = 0h] ...................................................... 567
9.6.8 WAKEUPENABLEL Register (offset = 3520h) [reset = 0h] ................................................ 568
9.6.9 MODULCTRLL Register (offset = 3528h) [reset = 4h]...................................................... 569
9.6.10 CH0CONFL Register (offset = 352Ch) [reset = 0h]........................................................ 570
9.6.11 CH0CONFU Register (offset = 352Dh) [reset = 6h]........................................................ 573
9.6.12 CH0STATL Register (offset = 3530h) [reset = 0h] ......................................................... 575
9.6.13 CH0CTRLL Register (offset = 3534h) [reset = 0h]......................................................... 576
9.6.14 CH0TXL Register (offset = 3538h) [reset = 0h]............................................................. 577
9.6.15 CH0TXU Register (offset = 3539h) [reset = 0h] ............................................................ 578
9.6.16 CH0RXL Register (offset = 353Ch) [reset = 0h]............................................................ 579
9.6.17 CH0RXU Register (offset = 353Dh) [reset = 0h] ........................................................... 580
9.6.18 CH1CONFL Register (offset = 3540h) [reset = 0h] ........................................................ 581
9.6.19 CH1CONFU Register (offset = 3541h) [reset = 6h]........................................................ 584
9.6.20 CH1STATL Register (offset = 3544h) [reset = 0h] ......................................................... 586
9.6.21 CH1CTRLL Register (offset = 3548h) [reset = 0h]......................................................... 587
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9.6.22 CH1TXL Register (offset = 354Ch) [reset = 0h] ............................................................ 588
9.6.23 CH1TXU Register (offset = 354Dh) [reset = 0h]............................................................ 589
9.6.24 CH1RXL Register (offset = 3550h) [reset = 0h] ............................................................ 590
9.6.25 CH1RXU Register (offset = 3551h) [reset = 0h]............................................................ 591
9.6.26 CH2CONFL Register (offset = 3554h) [reset = 0h] ........................................................ 592
9.6.27 CH2CONFU Register (offset = 3555h) [reset = 6h]........................................................ 595
9.6.28 CH2STATL Register (offset = 3558h) [reset = 0h] ......................................................... 597
9.6.29 CH2CTRLL Register (offset = 355Ch) [reset = 0h]......................................................... 598
9.6.30 CH2TXL Register (offset = 3560h) [reset = 0h]............................................................. 599
9.6.31 CH2TXU Register (offset = 3561h) [reset = 0h] ............................................................ 600
9.6.32 CH2RXL Register (offset = 3564h) [reset = 0h] ............................................................ 601
9.6.33 CH2RXU Register (offset = 3565h) [reset = 0h]............................................................ 602
9.6.34 XFERLEVELL Register (offset = 357Ch) [reset = 0h] ..................................................... 603
9.6.35 XFERLEVELU Register (offset = 357Dh) [reset = 0h]..................................................... 604
9.6.36 DAFTXL Register (offset = 3580h) [reset = 0h]............................................................. 605
9.6.37 DAFTXU Register (offset = 3581h) [reset = 0h] ............................................................ 606
9.6.38 DAFRXL Register (offset = 35A0h) [reset = 0h]............................................................ 607
9.6.39 DAFRXU Register (offset = 35A1h) [reset = 0h]............................................................ 608
10 Multimedia Card (MMC)/Secure Digital (SD) Card Controller .................................................. 609
10.1 Introduction ................................................................................................................ 610
10.1.1 Purpose of the Peripheral ..................................................................................... 610
10.1.2 Features.......................................................................................................... 610
10.1.3 Functional Block Diagram ..................................................................................... 610
10.1.4 Supported Use Case Statement.............................................................................. 610
10.1.5 Industry Standard(s) Compliance Statement................................................................ 611
10.2 Peripheral Architecture................................................................................................... 611
10.2.1 Clock Control.................................................................................................... 613
10.2.2 Signal Descriptions............................................................................................. 613
10.2.3 Pin Multiplexing ................................................................................................. 614
10.2.4 Protocol Descriptions........................................................................................... 614
10.2.5 Data Flow in the Input/Output FIFO.......................................................................... 615
10.2.6 Data Flow in the Data Registers (MMCDRR and MMCDXR)............................................. 617
10.2.7 FIFO Operation During Card Read Operation.............................................................. 618
10.2.8 FIFO Operation During Card Write Operation .............................................................. 619
10.2.9 Reset Considerations .......................................................................................... 621
10.2.10 Programming and Using the MMCSD Controller ......................................................... 622
10.2.11 Interrupt Support .............................................................................................. 626
10.2.12 DMA Event Support........................................................................................... 626
10.2.13 Emulation Considerations.................................................................................... 626
10.3 Procedures for Common Operations................................................................................... 627
10.3.1 Card Identification Operation.................................................................................. 627
10.3.2 MMC/SD Mode Single-Block Write Operation Using CPU................................................ 628
10.3.3 MMC/SD Mode Single-Block Write Operation Using DMA................................................ 629
10.3.4 MMC/SD Mode Single-Block Read Operation Using CPU................................................ 630
10.3.5 MMC/SD Mode Single-Block Read Operation Using DMA ............................................... 631
10.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU .............................................. 632
10.3.7 MMC/SD Mode Multiple-Block Write Operation Using DMA.............................................. 633
10.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU.............................................. 634
10.3.9 MMC/SD Mode Multiple-Block Read Operation Using DMA.............................................. 635
10.3.10 SD High Speed Mode ........................................................................................ 636
10.3.11 SDIO Card Function .......................................................................................... 636
10.4 MMC-SD0 CONTROLLER Registers .................................................................................. 637
10.4.1 MMCCTL Register (offset = 3A00h) [reset = 0h] ........................................................... 638
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10.4.2 MMCCLK Register (offset = 3A04h) [reset = FFh] ......................................................... 639
10.4.3 MMCST0 Register (offset = 3A08h) [reset = 200h] ........................................................ 640
10.4.4 MMCST1 Register (offset = 3A0Ch) [reset = 2h]........................................................... 642
10.4.5 MMCIM Register (offset = 3A10h) [reset = 0h] ............................................................. 643
10.4.6 MMCTOR Register (offset = 3A14h) [reset = 0h]........................................................... 645
10.4.7 MMCTOD Register (offset = 3A18h) [reset = 0h]........................................................... 646
10.4.8 MMCBLEN Register (offset = 3A1Ch) [reset = 200h]...................................................... 647
10.4.9 MMCNBLK Register (offset = 3A20h) [reset = 0h] ......................................................... 648
10.4.10 MMCNBLC Register (offset = 3A24h) [reset = FFFFh] .................................................. 649
10.4.11 MMCDRR1 Register (offset = 3A28h) [reset = 0h] ....................................................... 650
10.4.12 MMCDRR2 Register (offset = 3A29h) [reset = 0h] ....................................................... 651
10.4.13 MMCDXR1 Register (offset = 3A2Ch) [reset = 0h]....................................................... 652
10.4.14 MMCDXR2 Register (offset = 3A2Dh) [reset = 0h]....................................................... 653
10.4.15 MMCCMD1 Register (offset = 3A30h) [reset = 0h]....................................................... 654
10.4.16 MMCCMD2 Register (offset = 3A31h) [reset = 0h]....................................................... 656
10.4.17 MMCARG1 Register (offset = 3A34h) [reset = 0h] ....................................................... 657
10.4.18 MMCARG2 Register (offset = 3A35h) [reset = 0h] ....................................................... 658
10.4.19 MMCRSP0 Register (offset = 3A38h) [reset = 0h]........................................................ 659
10.4.20 MMCRSP1 Register (offset = 3A39h) [reset = 0h]........................................................ 660
10.4.21 MMCRSP2 Register (offset = 3A3Ch) [reset = 0h] ....................................................... 661
10.4.22 MMCRSP3 Register (offset = 3A3Dh) [reset = 0h] ....................................................... 662
10.4.23 MMCRSP4 Register (offset = 3A40h) [reset = 0h]........................................................ 663
10.4.24 MMCRSP5 Register (offset = 3A41h) [reset = 0h]........................................................ 664
10.4.25 MMCRSP6 Register (offset = 3A44h) [reset = 0h]........................................................ 665
10.4.26 MMCRSP7 Register (offset = 3A45h) [reset = 0h]........................................................ 666
10.4.27 MMCDRSP Register (offset = 3A48h) [reset = 0h] ....................................................... 667
10.4.28 MMCCIDX Register (offset = 3A50h) [reset = 0h] ........................................................ 668
10.4.29 SDIOCTL Register ............................................................................................ 669
10.4.30 SDIOST0 Register (offset = 3A68h) [reset = 3h].......................................................... 670
10.4.31 SDIOIEN Register (offset = 3A6Ch) [reset = 0h].......................................................... 671
10.4.32 SDIOIST Register (offset = 3A70h) [reset = 0h] .......................................................... 672
10.4.33 MMCFIFOCTL Register (offset = 3A74h) [reset = 0h] ................................................... 673
10.5 MMC-SD1 CONTROLLER Registers .................................................................................. 673
10.5.1 MMCCTL Register (offset = 3B00h) [reset = 0h] ........................................................... 675
10.5.2 MMCCLK Register (offset = 3B04h) [reset = FFh] ......................................................... 676
10.5.3 MMCST0 Register (offset = 3B08h) [reset = 200h] ........................................................ 677
10.5.4 MMCST1 Register (offset = 3B0Ch) [reset = 2h]........................................................... 679
10.5.5 MMCIM Register (offset = 3B10h) [reset = 0h] ............................................................. 680
10.5.6 MMCTOR Register (offset = 3B14h) [reset = 0h]........................................................... 682
10.5.7 MMCTOD Register (offset = 3B18h) [reset = 0h]........................................................... 683
10.5.8 MMCBLEN Register (offset = 3B1Ch) [reset = 200h]...................................................... 684
10.5.9 MMCNBLK Register (offset = 3B20h) [reset = 0h] ......................................................... 685
10.5.10 MMCNBLC Register (offset = 3B24h) [reset = FFFFh] .................................................. 686
10.5.11 MMCDRR1 Register (offset = 3B28h) [reset = 0h] ....................................................... 687
10.5.12 MMCDRR2 Register (offset = 3B29h) [reset = 0h] ....................................................... 688
10.5.13 MMCDXR1 Register (offset = 3B2Ch) [reset = 0h]....................................................... 689
10.5.14 MMCDXR2 Register (offset = 3B2Dh) [reset = 0h]....................................................... 690
10.5.15 MMCCMD1 Register (offset = 3B30h) [reset = 0h]....................................................... 691
10.5.16 MMCCMD2 Register (offset = 3B31h) [reset = 0h]....................................................... 693
10.5.17 MMCARG1 Register (offset = 3B34h) [reset = 0h] ....................................................... 694
10.5.18 MMCARG2 Register (offset = 3B35h) [reset = 0h] ....................................................... 695
10.5.19 MMCRSP0 Register (offset = 3B38h) [reset = 0h]........................................................ 696
10.5.20 MMCRSP1 Register (offset = 3B39h) [reset = 0h]........................................................ 697
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10.5.21 MMCRSP2 Register (offset = 3B3Ch) [reset = 0h] ....................................................... 698
10.5.22 MMCRSP3 Register (offset = 3B3Dh) [reset = 0h] ....................................................... 699
10.5.23 MMCRSP4 Register (offset = 3B40h) [reset = 0h]........................................................ 700
10.5.24 MMCRSP5 Register (offset = 3B41h) [reset = 0h]........................................................ 701
10.5.25 MMCRSP6 Register (offset = 3B44h) [reset = 0h]........................................................ 702
10.5.26 MMCRSP7 Register (offset = 3B45h) [reset = 0h]........................................................ 703
10.5.27 MMCDRSP Register (offset = 3B48h) [reset = 0h] ....................................................... 704
10.5.28 MMCCIDX Register (offset = 3B50h) [reset = 0h] ........................................................ 705
10.5.29 SDIOCTL Register ............................................................................................ 706
10.5.30 SDIOST0 Register (offset = 3B68h) [reset = 3h].......................................................... 707
10.5.31 SDIOIEN Register (offset = 3B6Ch) [reset = 0h].......................................................... 708
10.5.32 SDIOIST Register (offset = 3B70h) [reset = 0h] .......................................................... 709
10.5.33 MMCFIFOCTL Register (offset = 3B74h) [reset = 0h] ................................................... 710
11 Real-Time Clock (RTC) ..................................................................................................... 711
11.1 Introduction ................................................................................................................ 712
11.1.1 Purpose of the Peripheral ..................................................................................... 712
11.1.2 Features......................................................................................................... 712
11.1.3 Functional Block Diagram ..................................................................................... 713
11.2 Peripheral Architecture................................................................................................... 713
11.2.1 Clock Control.................................................................................................... 713
11.2.2 Signal Descriptions............................................................................................. 713
11.2.3 Configuring the RTC Registers ............................................................................... 714
11.2.4 Using the Real-Time Clock Time and Calendar Registers................................................ 714
11.2.5 Using the Real-Time Clock Time and Calendar Alarms................................................... 716
11.2.6 Real-Time Clock Interrupt Requests ......................................................................... 717
11.2.7 Reset Considerations .......................................................................................... 721
11.3 Registers................................................................................................................... 722
11.3.1 Overview......................................................................................................... 722
11.3.2 RTC Registers .................................................................................................. 722
12 Successive Approximation (SAR) Analog-to-Digital Converter (ADC)...................................... 751
12.1 Introduction ................................................................................................................ 752
12.1.1 Purpose of the 10-bit SAR..................................................................................... 752
12.1.2 Features.......................................................................................................... 752
12.1.3 Supported Use Case Statement.............................................................................. 752
12.1.4 Industry Standard(s) Compliance Statement................................................................ 752
12.1.5 Functional Block Diagram ..................................................................................... 753
12.2 SAR Architecture.......................................................................................................... 754
12.2.1 SAR Clock Control.............................................................................................. 754
12.2.2 Memory Map .................................................................................................... 754
12.2.3 Signal Descriptions............................................................................................. 754
12.2.4 Battery Measurement .......................................................................................... 754
12.2.5 Internal Voltage Measurement................................................................................ 755
12.2.6 Volume Control................................................................................................. 755
12.2.7 Touch Screen Digitizing........................................................................................ 756
12.2.8 Touch Screen : Pen Press Interrupts ........................................................................ 757
12.2.9 General-Purpose Output....................................................................................... 758
12.2.10 Reset Considerations......................................................................................... 759
12.2.11 A/D Conversion................................................................................................ 759
12.2.12 Interrupt Support .............................................................................................. 759
12.2.13 Emulation Considerations.................................................................................... 759
12.2.14 Conversion Example.......................................................................................... 759
12.3 SAR Registers............................................................................................................. 761
12.3.1 SARCTRL Register............................................................................................. 762
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12.3.2 SARDATA Register............................................................................................. 763
12.3.3 SARCLKCTRL Register........................................................................................ 764
12.3.4 SARPINCTRL Register ........................................................................................ 765
12.3.5 SARGPOCTRL Register....................................................................................... 767
13 Serial Peripheral Interface (SPI).......................................................................................... 768
13.1 Introduction ................................................................................................................ 769
13.1.1 Purpose of the Peripheral ..................................................................................... 769
13.1.2 Features.......................................................................................................... 769
13.1.3 Functional Block Diagram ..................................................................................... 769
13.1.4 Supported Use Case Statement.............................................................................. 770
13.1.5 Industry Standard(s) Compliance Statement................................................................ 770
13.2 Serial Peripheral Interface Architecture................................................................................ 771
13.2.1 Clock Control.................................................................................................... 771
13.2.2 Signal Descriptions............................................................................................. 772
13.2.3 Units of Data: Characters and Frames ...................................................................... 772
13.2.4 Chip Select Control............................................................................................. 772
13.2.5 Clock Polarity and Phase...................................................................................... 772
13.2.6 Data Delay....................................................................................................... 774
13.2.7 Data Input and Output ......................................................................................... 775
13.2.8 Loopback Mode................................................................................................. 775
13.2.9 Monitoring SPI Activity ......................................................................................... 775
13.2.10 Slave Access .................................................................................................. 776
13.2.11 Reset Considerations......................................................................................... 778
13.2.12 Initialization..................................................................................................... 778
13.2.13 Interrupt Support .............................................................................................. 779
13.2.14 DMA Event Support........................................................................................... 779
13.2.15 Power Management .......................................................................................... 779
13.2.16 Emulation Considerations.................................................................................... 779
13.3 Interfacing the SPI to an SPI EEPROM ............................................................................... 779
13.3.1 Operational Description........................................................................................ 779
13.3.2 Hardware Interface ............................................................................................. 780
13.3.3 SW Configuration............................................................................................... 780
13.4 SPI Registers.............................................................................................................. 783
13.4.1 SPICDR Register (offset = 3000h) [reset = 0h]............................................................. 785
13.4.2 SPICCR Register (offset = 3001h) [reset = 0h]............................................................. 786
13.4.3 SPIDCR1 Register (offset = 3002h) [reset = 0h] ........................................................... 787
13.4.4 SPIDCR2 Register (offset = 3003h) [reset = 0h] ........................................................... 789
13.4.5 SPICMD1 Register (offset = 3004h) [reset = 0h]........................................................... 791
13.4.6 SPICMD2 Register (offset = 3005h) [reset = 0h]........................................................... 792
13.4.7 SPISTAT1 Register (offset = 3006h) [reset = 0h] .......................................................... 793
13.4.8 SPISTAT2 Register (offset = 3007h) [reset = 0h] .......................................................... 794
13.4.9 SPIDAT1 Register (offset = 3008h) [reset = 0h]............................................................ 795
13.4.10 SPIDAT2 Register (offset = 3009h) [reset = 0h] .......................................................... 796
14 32-Bit Timer/Watchdog Timer............................................................................................. 797
14.1 Introduction ................................................................................................................ 798
14.1.1 Purpose of the Timers ......................................................................................... 798
14.1.2 Features.......................................................................................................... 798
14.1.3 Functional Timer Block Diagram.............................................................................. 799
14.2 General-Purpose Timer.................................................................................................. 799
14.2.1 General-Purpose Timer Clock Control....................................................................... 799
14.2.2 Using the 32-bit General Purpose Timer .................................................................... 799
14.3 Watchdog Timer .......................................................................................................... 801
14.3.1 Watchdog Timer Function ..................................................................................... 801
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14.3.2 Watchdog Timer Operation.................................................................................... 801
14.4 Reset Considerations .................................................................................................... 802
14.5 Interrupt Support.......................................................................................................... 802
14.6 Registers................................................................................................................... 803
14.6.1 TIMER 0 CONTROLLER Registers.......................................................................... 803
14.6.2 TIMER 1 CONTROLLER Registers.......................................................................... 810
14.6.3 TIMER 2 CONTROLLER Registers.......................................................................... 817
14.6.4 TISR Registers.................................................................................................. 824
14.6.5 TIAFR Registers ................................................................................................ 826
14.6.6 WATCHDOG TIMER Registers............................................................................... 828
15 Universal Asynchronous Receiver/Transmitter (UART) ......................................................... 837
15.1 Introduction ................................................................................................................ 838
15.1.1 Purpose of the Peripheral ..................................................................................... 838
15.1.2 Features.......................................................................................................... 838
15.1.3 Functional Block Diagram ..................................................................................... 839
15.1.4 Industry Standard(s) Compliance Statement................................................................ 839
15.2 Peripheral Architecture................................................................................................... 841
15.2.1 Clock Generation and Control ................................................................................ 841
15.2.2 Signal Descriptions............................................................................................. 843
15.2.3 Pin Multiplexing ................................................................................................. 843
15.2.4 Protocol Description............................................................................................ 843
15.2.5 Operation ........................................................................................................ 844
15.2.6 Exception Processing .......................................................................................... 848
15.2.7 Reset Considerations .......................................................................................... 848
15.2.8 Initialization ...................................................................................................... 849
15.2.9 Interrupt Support................................................................................................ 849
15.2.10 DMA Event Support........................................................................................... 850
15.2.11 Power Management .......................................................................................... 851
15.2.12 Emulation Considerations.................................................................................... 851
15.3 UART Registers........................................................................................................... 852
15.3.1 UART Registers................................................................................................. 852
16 Host Port Interface (UHPI).................................................................................................. 868
16.1 Introduction ................................................................................................................ 869
16.1.1 Purpose of the Peripheral ..................................................................................... 869
16.1.2 Features.......................................................................................................... 869
16.1.3 Functional Block Diagram ..................................................................................... 870
16.1.4 Industry Standard(s) Compliance Statement................................................................ 871
16.1.5 Terminology Used in This Document ........................................................................ 871
16.2 Architecture................................................................................................................ 872
16.2.1 Memory Map .................................................................................................... 872
16.2.2 Signal Descriptions............................................................................................. 872
16.2.3 Pin Multiplexing ................................................................................................. 873
16.2.4 Protocol Description............................................................................................ 873
16.2.5 Operation ........................................................................................................ 873
16.2.6 Reset Considerations .......................................................................................... 889
16.2.7 Initialization ...................................................................................................... 889
16.2.8 Interrupt Support................................................................................................ 890
16.2.9 Emulation Considerations ..................................................................................... 892
16.3 UHPIA Register Settings................................................................................................. 892
16.4 Chip-Level Configuration for the UHPI Mode ......................................................................... 892
16.5 UHPI Configuration Register at Top Level ............................................................................ 892
16.6 UHPI Registers............................................................................................................ 893
16.6.1 PIDL Register (word address = 2E00h) [reset = 10Ah].................................................... 895
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16.6.2 PIDU Register (word address = 2E01h) [reset = 4421h].................................................. 896
16.6.3 PWREMU_MGMT Register (word address = 2E04h) [reset = 0h]....................................... 897
16.6.4 GPINT_CTRLL Register (word address = 2E08h) [reset = 0h]........................................... 898
16.6.5 GPINT_CTRLU Register (word address = 2E09h) [reset = 0h] .......................................... 899
16.6.6 GPIO_EN Register (word address = 2E0Ch) [reset = 0h]................................................. 900
16.6.7 GPIO_DIR1 Register (word address = 2E10h) [reset = 0h]............................................... 901
16.6.8 GPIO_DAT1 Register (word address = 2E14h) [reset = 0h].............................................. 902
16.6.9 GPIO_DIR2 Register (word address = 2E18h) [reset = 0h]............................................... 903
16.6.10 GPIO_DAT2 Register (word address = 2E1Ch) [reset = 0h]............................................ 905
16.6.11 UHPICL Register (word address = 2E30h) [reset = C0h]................................................ 907
16.6.12 UHPIAWL Register (word address = 2E34h) [reset = 0h] ............................................... 909
16.6.13 UHPIAWU Register (word address = 2E35h) [reset = 0h]............................................... 910
16.6.14 UHPIARL Register (word address = 2E38h) [reset = 0h]................................................ 911
16.6.15 UHPIARU Register (word address = 2E39h) [reset = 0h] ............................................... 912
16.6.16 XUHPIAWL Register (word address = 2E3Ch) [reset = 0h]............................................. 913
16.6.17 XUHPIAWU Register (word address = 2E3Dh) [reset = 0h]............................................. 914
16.6.18 XUHPIARL Register (word address = 2E40h) [reset = 0h].............................................. 915
16.6.19 XUHPIARU Register (word address = 2E41h) [reset = 0h].............................................. 916
17 Universal Serial Bus (USB) Controller ................................................................................. 917
17.1 Introduction ................................................................................................................ 918
17.1.1 Purpose of the Peripheral ..................................................................................... 918
17.1.2 Features.......................................................................................................... 918
17.1.3 Functional Block Diagram ..................................................................................... 919
17.1.4 Industry Standard(s) Compliance Statement................................................................ 919
17.2 Architecture................................................................................................................ 919
17.2.1 Clock Control.................................................................................................... 919
17.2.2 Signal Descriptions............................................................................................. 920
17.2.3 Memory Map .................................................................................................... 920
17.2.4 USB_DP/USB_DM Polarity Inversion........................................................................ 921
17.2.5 Indexed and Non-Indexed Registers......................................................................... 922
17.2.6 USB PHY Initialization ......................................................................................... 922
17.2.7 Dynamic FIFO Sizing........................................................................................... 924
17.2.8 USB Controller Peripheral Mode Operation................................................................. 924
17.2.9 Communications Port Programming Interface (CPPI) 4.1 DMA Overview for TMS320C5515....... 944
17.2.10 BYTEMODE Bits of the USB System Control Register .................................................. 968
17.2.11 Reset Considerations......................................................................................... 969
17.2.12 Interrupt Support .............................................................................................. 969
17.2.13 DMA Event Support........................................................................................... 969
17.2.14 Power Management .......................................................................................... 969
17.3 Registers................................................................................................................... 971
17.3.1 USB Controller Register Summary........................................................................... 971
17.3.2 Revision Identification Registers (REVID1 and REVID2) ................................................. 979
17.3.3 Control Register (CTRLR)..................................................................................... 980
17.3.4 Emulation Register (EMUR)................................................................................... 981
17.3.5 Mode Registers (MODE1 and MODE2) ..................................................................... 982
17.3.6 Auto Request Register (AUTOREQ)......................................................................... 984
17.3.7 Teardown Registers (TEARDOWN1 and TEARDOWN2)................................................. 985
17.3.8 USB Interrupt Source Registers (INTSRCR1 and INTSRCR2)........................................... 986
17.3.9 USB Interrupt Source Set Registers (INTSETR1 and INTSETR2)....................................... 987
17.3.10 USB Interrupt Source Clear Registers (INTCLRR1 and INTCLRR2) .................................. 988
17.3.11 USB Interrupt Mask Registers (INTMSKR1 and INTMSKR2)........................................... 989
17.3.12 USB Interrupt Mask Set Registers (INTMSKSETR1 and INTMSKSETR2) ........................... 990
17.3.13 USB Interrupt Mask Clear Registers (INTMSKCLRR1 and INTMSKCLRR2)......................... 991
15
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17.3.14 USB Interrupt Source Masked Registers (INTMASKEDR1 and INTMASKEDR2) ................... 992
17.3.15 USB End of Interrupt Register (EOIR)...................................................................... 993
17.3.16 USB Interrupt Vector Registers (INTVECTR1 and INTVECTR2)....................................... 993
17.3.17 Generic RNDIS EP1 Size Registers (GREP1SZR1 and GREP1SZR2) .............................. 994
17.3.18 Generic RNDIS EP2 Size Registers (GREP2SZR1 and GREP2SZR2) .............................. 995
17.3.19 Generic RNDIS EP3 Size Registers (GREP3SZR1 and GREP3SZR2) .............................. 996
17.3.20 Generic RNDIS EP4 Size Registers (GREP4SZR1 and GREP4SZR2) .............................. 997
17.3.21 Function Address Register (FADDR)....................................................................... 998
17.3.22 Power Management Register (POWER)................................................................... 998
17.3.23 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX).......................... 999
17.3.24 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) .............................................. 999
17.3.25 Interrupt Enable Register for INTRTX (INTRTXE) ...................................................... 1000
17.3.26 Interrupt Enable Register for INTRRX (INTRRXE)...................................................... 1000
17.3.27 Interrupt Register for Common USB Interrupts (INTRUSB)............................................ 1001
17.3.28 Interrupt Enable Register for INTRUSB (INTRUSBE) .................................................. 1002
17.3.29 Frame Number Register (FRAME) ........................................................................ 1002
17.3.30 Index Register for Selecting the Endpoint Status and Control Registers (INDEX).................. 1003
17.3.31 Register to Enable the USB 2.0 Test Modes (TESTMODE)........................................... 1003
17.3.32 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)........................... 1004
17.3.33 Control Status Register for Peripheral Endpoint 0 (PERI_CSR0)..................................... 1005
17.3.34 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR).......................... 1006
17.3.35 Maximum Packet Size for Peripheral Receive Endpoint (RXMAXP) ................................. 1007
17.3.36 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) .......................... 1008
17.3.37 Count 0 Register (COUNT0) ............................................................................... 1009
17.3.38 Receive Count Register (RXCOUNT)..................................................................... 1009
17.3.39 Configuration Data Register (CONFIGDATA) ........................................................... 1010
17.3.40 Transmit and Receive FIFO Registers for Endpoint 0 (FIFO0R1 and FIFO0R2)................... 1011
17.3.41 Transmit and Receive FIFO Registers for Endpoint 1 (FIFO1R1 and FIFO1R2)................... 1012
17.3.42 Transmit and Receive FIFO Registers for Endpoint 2 (FIFO2R1 and FIFO2R2)................... 1013
17.3.43 Transmit and Receive FIFO Registers for Endpoint 3 (FIFO3R1 and FIFO3R2)................... 1014
17.3.44 Transmit and Receive FIFO Registers for Endpoint 4 (FIFO4R1 and FIFO4R2)................... 1015
17.3.45 Device Control Register (DEVCTL) ....................................................................... 1016
17.3.46 Transmit Endpoint FIFO Size (TXFIFOSZ)............................................................... 1017
17.3.47 Receive Endpoint FIFO Size (RXFIFOSZ)............................................................... 1017
17.3.48 Transmit Endpoint FIFO Address (TXFIFOADDR)...................................................... 1018
17.3.49 Hardware Version Register (HWVERS) .................................................................. 1018
17.3.50 Receive Endpoint FIFO Address (RXFIFOADDR) ..................................................... 1019
17.3.51 CDMA Revision Identification Registers (DMAREVID1 and DMAREVID2).......................... 1019
17.3.52 CDMA Teardown Free Descriptor Queue Control Register (TDFDQ)................................ 1020
17.3.53 CDMA Emulation Control Register (DMAEMU) ......................................................... 1020
17.3.54 CDMA Transmit Channel n Global Configuration Registers (TXGCR1[n] and TXGCR2[n])....... 1021
17.3.55 CDMA Receive Channel n Global Configuration Registers (RXGCR1[n] and RXGCR2[n])....... 1022
17.3.56 CDMA Receive Channel n Host Packet Configuration Registers A (RXHPCR1A[n] and
RXHPCR2A[n]) ................................................................................................. 1024
17.3.57 CDMA Receive Channel n Host Packet Configuration Registers B (RXHPCR1B[n] and
RXHPCR2B[n]) ................................................................................................. 1025
17.3.58 CDMA Scheduler Control Register (DMA_SCHED_CTRL1 and DMA_SCHED_CTRL2) ......... 1026
17.3.59 CDMA Scheduler Table Word n Registers (ENTRYLSW[n]-ENTRYMSW[n])....................... 1027
17.3.60 Queue Manager Revision Identification Registers (QMGRREVID1 and QMGRREVID2) ......... 1028
17.3.61 Queue Manager Queue Diversion Registers (DIVERSION1 and DIVERSION2) ................... 1029
17.3.62 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0)................... 1030
17.3.63 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1)................... 1030
17.3.64 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2)................... 1031
17.3.65 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3)................... 1031
16
Contents SPRUH16B–April 2014–Revised October 2015
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17.3.66 Queue Manager Free Descriptor/Buffer Starvation Count Register 4 (FDBSC4)................... 1032
17.3.67 Queue Manager Free Descriptor/Buffer Starvation Count Register 5 (FDBSC5)................... 1032
17.3.68 Queue Manager Free Descriptor/Buffer Starvation Count Register 6 (FDBSC6)................... 1033
17.3.69 Queue Manager Free Descriptor/Buffer Starvation Count Register 7 (FDBSC7)................... 1033
17.3.70 Queue Manager Linking RAM Region 0 Base Address Registers (LRAM0BASE1 and
LRAM0BASE2) ................................................................................................. 1034
17.3.71 Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) .............................. 1035
17.3.72 Queue Manager Linking RAM Region 1 Base Address Registers (LRAM1BASE1 and
LRAM1BASE2) ................................................................................................. 1036
17.3.73 Queue Manager Queue Pending Register 0 (PEND0) ................................................. 1037
17.3.74 Queue Manager Queue Pending Register 1 (PEND1) ................................................. 1037
17.3.75 Queue Manager Queue Pending Register 2 (PEND2) ................................................. 1038
17.3.76 Queue Manager Queue Pending Register 3 (PEND3) ................................................. 1038
17.3.77 Queue Manager Queue Pending Register 4 (PEND4) ................................................. 1039
17.3.78 Queue Manager Queue Pending Register 5 (PEND5) ................................................. 1039
17.3.79 Queue Manager Memory Region R Base Address Registers (QMEMRBASE1[R] and
QMEMRBASE2[R]) ............................................................................................ 1040
17.3.80 Queue Manager Memory Region R Control Registers (QMEMRCTRL1[R] and
QMEMRCTRL2[R])............................................................................................. 1041
17.3.81 Queue Manager Queue N Control Register D (CTRL1D[N] and CTRL2D[N]) ...................... 1042
17.3.82 Queue Manager Queue N Status Register A (QSTATA[N]) ........................................... 1043
17.3.83 Queue Manager Queue N Status Registers B (QSTAT1B[N] and QSTAT2B[N]) .................. 1043
17.3.84 Queue Manager Queue N Status Register C (QSTATC[N])........................................... 1044
17
SPRUH16B–April 2014–Revised October 2015 Contents
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List of Figures
1-1. Functional Block Diagram................................................................................................. 54
1-2. DSP Memory Map ......................................................................................................... 58
1-3. DSP Clocking Diagram ................................................................................................... 63
1-4. Clock Generator............................................................................................................ 65
1-5. PLL Output Frequency Configuration.................................................................................... 65
1-6. CLKOUT Configuration Register (CLKOUTCR) [1C24h] ............................................................. 66
1-7. PLL Multiplier Register (PMR) [1C20h].................................................................................. 73
1-8. PLL Input Control Register (PICR) [1C21h] ............................................................................ 74
1-9. PLL Control Register (PCR) [1C22h].................................................................................... 75
1-10. PLL Ouput Divider Register (PODCR) [1C23h] ........................................................................ 75
1-11. Clock Configuration Register 1 (CCR1) [1C1Eh] ...................................................................... 77
1-12. Clock Configuration Register 2 (CCR2) [1C1Fh]....................................................................... 78
1-13. Idle Configuration Register (ICR) [0001h]............................................................................... 82
1-14. Idle Status Register (ISTR) [0002h]...................................................................................... 83
1-15. Peripheral Clock Gating Configuration Register 1 (PCGCR1) [1C02h]............................................. 85
1-16. Peripheral Clock Gating Configuration Register 2 (PCGCR2) [1C03h]............................................. 87
1-17. Peripheral Clock Stop Request/Acknowledge Register 1 (CLKSTOP1) [1C3Ah] ................................. 88
1-18. Peripheral Clock Stop Request/Acknowledge Register 2 (CLKSTOP2) [1C3Bh] ................................. 91
1-19. USB System Control Register (USBSCR) [1C32h].................................................................... 93
1-20. RTC Power Management Register (RTCPMGT) [1930h]............................................................. 95
1-21. RTC Interrupt Flag Register (RTCINTFL) [1920h]..................................................................... 96
1-22. RTC System Control Register (RSCR) [1C27h]........................................................................ 97
1-23. RTC Gate-Keeper Register LSW (RGKR_LSW) [196Ch] ............................................................ 98
1-24. RTC Gate-Keeper Register MSW (RGKR_MSW) [196Dh]........................................................... 98
1-25. RAM Sleep Mode Control Register 1 (RAMSLPMDCNTLR1) [1C28h] ............................................. 99
1-26. RAM Sleep Mode Control Register 2 (RAMSLPMDCNTLR2) [1C2Ah]............................................. 99
1-27. RAM Sleep Mode Control Register 3 (RAMSLPMDCNTLR3) [1C2Bh] ........................................... 100
1-28. RAM Sleep Mode Control Register 4 (RAMSLPMDCNTLR4) [1C2Ch] ........................................... 100
1-29. RAM Sleep Mode Control Register 5 (RAMSLPMDCNTLR5) [1C2Dh] ........................................... 100
1-30. IFR0 and IER0 Bit Locations............................................................................................ 106
1-31. IFR1 and IER1 Bit Locations............................................................................................ 107
1-32. Timer Interrupt Selection Register (TISR) [1C3Eh] .................................................................. 108
1-33. McSPI Interrupt Aggregation Flag Register (MSIAFR) [1C15h] .................................................... 109
1-34. McSPI Interrupt Aggregation Enable Register (MSIAER) [1C3Dh] ................................................ 111
1-35. Die ID Register 0 (DIEIDR0) [1C40h].................................................................................. 113
1-36. Die ID Register 1 (DIEIDR1) [1C41h].................................................................................. 113
1-37. Die ID Register 2 (DIEIDR2) [1C42h].................................................................................. 113
1-38. Die ID Register 3 (DIEIDR3) [1C43h].................................................................................. 114
1-39. Die ID Register 4 (DIEIDR4) [1C44h].................................................................................. 114
1-40. Die ID Register 5 (DIEIDR5) [1C45h].................................................................................. 115
1-41. Die ID Register 6 (DIEIDR6) [1C46h].................................................................................. 115
1-42. Die ID Register 7 (DIEIDR7) [1C47h].................................................................................. 115
1-43. JTAG ID Code LSW Register (JTAGIDLSW) [1C58h]............................................................... 116
1-44. JTAG ID Code MSW Register (JTAGIDMSW) [1C59h] ............................................................. 117
1-45. External Bus Selection Register (EBSR) [1C00h].................................................................... 118
1-46. RTC Power Management Register (RTCPMGT) [1930h] ........................................................... 124
1-47. LDO Control Register (LDOCNTL) [7004h] ........................................................................... 125
18
List of Figures SPRUH16B–April 2014–Revised October 2015
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1-48. Output Slew Rate Control Register (OSRCR) [1C16h].............................................................. 126
1-49. Pullup and Pulldown Inhibit Register 1 (PUDINHIBR1) [1C17h] ................................................... 127
1-50. Pullup and Pulldown Inhibit Register 2 (PUDINHIBR2) [1C18h] ................................................... 128
1-51. Pullup and Pulldown Inhibit Register 3 (PUDINHIBR3) [1C19h] ................................................... 129
1-52. Pullup and Pulldown Inhibit Register 4 (PUDINHIBR4) [1C4Ch]................................................... 131
1-53. Pullup and Pulldown Inhibit Register 5 (PUDINHIBR5) [1C4Dh]................................................... 132
1-54. Pullup and Pulldown Inhibit Register 6 (PUDINHIBR6) [1C4Fh] ................................................... 133
1-55. Pullup and Pulldown Inhibit Register 7 (PUDINHIBR7) [1C50h] ................................................... 135
1-56. DMA Interrupt Flag Register (DMAIFR) [1C30h] ..................................................................... 138
1-57. DMA Interrupt Enable Register (DMAIER) [1C31h].................................................................. 138
1-58. DMAn Channel Event Source Register 1 (DMAnCESR1) [1C1Ah, 1C1Ch, 1C36h, and 1C38h].............. 140
1-59. DMAn Channel Event Source Register 2 (DMAnCESR2) [1C1Bh, 1C1Dh, 1C37h, and 1C39h].............. 140
1-60. Peripheral Software Reset Counter Register (PSRCR) [1C04h]................................................... 141
1-61. Peripheral Reset Control Register (PRCR) [1C05h] ................................................................. 141
1-62. EMIF System Control Register (ESCR) [1C33h] ..................................................................... 144
1-63. EMIF Clock Divider Register (ECDR) [1C26h]........................................................................ 145
1-64. McSPI Functional Clock Divider Register (MSPIFCDR) [1C3Ch].................................................. 146
1-65. UHPI Configuration Register (UHPICR) [1C4Eh]..................................................................... 147
1-66. BootMode Register (BMR) [1C34h] .................................................................................... 148
2-1. DIT Radix 2 Butterfly ..................................................................................................... 153
2-2. DIT Radix 2 8-point FFT................................................................................................. 154
2-3. Graphical FFT Computation............................................................................................. 155
2-4. Block Diagram............................................................................................................. 156
2-5. Bit Reversed Input Buffer................................................................................................ 162
2-6. Graphing the Real Part of the FFT Result in CCS4.................................................................. 166
2-7. Graphing the Imaginary Part of the FFT Result in CCS4 ........................................................... 167
3-1. Conceptual Block Diagram of the DMA Controller ................................................................... 175
3-2. Clocking Diagram for the DMA Controller............................................................................. 176
3-3. Two-Part DMA Transfer.................................................................................................. 177
3-4. Registers for Controlling the Context of a Channel .................................................................. 179
3-5. Ping-Pong Mode for DMA Data Transfer.............................................................................. 183
3-6. Block Move Example..................................................................................................... 188
3-7. Block Move Example DMA Configuration ............................................................................. 188
3-8. Servicing Incoming I2C Data Example................................................................................. 189
3-9. Servicing Incoming I2C Data Example DMA Configuration......................................................... 189
3-10. Servicing Incoming UART Data Example ............................................................................. 190
3-11. Servicing Incoming UART Data Example DMA Configuration...................................................... 190
3-12. Servicing Incoming I2S Data Example in Ping-Pong DMA Mode.................................................. 191
3-13. Servicing Incoming I2S Data Example DMA Configuration......................................................... 191
3-14. Source Start Address Register - Lower Part (DMACHmSSAL) .................................................... 195
3-15. Source Start Address Register - Upper Part (DMACHmSSAU).................................................... 195
3-16. Destination Start Address Register - Lower Part (DMACHmDSAL) ............................................... 196
3-17. Destination Start Address Register - Upper Part (DMACHmDSAU)............................................... 196
3-18. Transfer Control Register Lower (DMACHmTCRL).................................................................. 197
3-19. Transfer Control Register Upper (DMACHmTCRU) ................................................................. 197
4-1. EMIF Functional Block Diagram ........................................................................................ 203
4-2. Clocking Diagram for the EMIF ......................................................................................... 204
4-3. Timing Waveform for SDRAM PRE Command....................................................................... 208
4-4. EMIF to mSDRAM Connection.......................................................................................... 209
19
SPRUH16B–April 2014–Revised October 2015 List of Figures
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4-5. Timing Waveform for Basic SDRAM Read Operation ............................................................... 215
4-6. Timing Waveform for Basic SDRAM Write Operation ............................................................... 216
4-7. EMIF Asynchronous Interface........................................................................................... 220
4-8. Connecting Data and Address Bus to Asynchronous Memory Devices........................................... 221
4-9. Common Asynchronous Interface ...................................................................................... 221
4-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode.............................................. 225
4-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode.............................................. 227
4-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode...................................... 229
4-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ...................................... 230
4-14. EMIF to NAND Flash Interface.......................................................................................... 232
4-15. ECC Value for 8-Bit NAND Flash....................................................................................... 235
4-16. Hardware Interface to Mobile SDRAM Device........................................................................ 245
4-17. SDTIMR1 Contents....................................................................................................... 245
4-18. SDTIMR2 Contents....................................................................................................... 245
4-19. SDRETR Contents........................................................................................................ 246
4-20. SDRCR Contents......................................................................................................... 246
4-21. SDCR1 Contents.......................................................................................................... 247
4-22. SDCR2 Contents.......................................................................................................... 247
4-23. REV Register.............................................................................................................. 250
4-24. STATUS Register......................................................................................................... 251
4-25. AWCCR1 Register........................................................................................................ 252
4-26. AWCCR2 Register........................................................................................................ 253
4-27. SDCR1 Register .......................................................................................................... 255
4-28. SDCR2 Register .......................................................................................................... 257
4-29. SDRCR Register.......................................................................................................... 259
4-30. ACS2CR1 Register....................................................................................................... 260
4-31. ACS2CR2 Register....................................................................................................... 261
4-32. ACS3CR1 Register....................................................................................................... 262
4-33. ACS3CR2 Register....................................................................................................... 263
4-34. ACS4CR1 Register....................................................................................................... 264
4-35. ACS4CR2 Register....................................................................................................... 265
4-36. ACS5CR1 Register....................................................................................................... 266
4-37. ACS5CR2 Register....................................................................................................... 267
4-38. SDTIMR1 Register........................................................................................................ 268
4-39. SDTIMR2 Register........................................................................................................ 269
4-40. SDSRETR Register....................................................................................................... 270
4-41. EIRR Register............................................................................................................. 271
4-42. EIMR Register............................................................................................................. 272
4-43. EIMSR Register........................................................................................................... 273
4-44. EIMCR Register........................................................................................................... 274
4-45. NANDFCR Register ...................................................................................................... 275
4-46. NANDFSR1 Register..................................................................................................... 277
4-47. NANDFSR2 Register..................................................................................................... 278
4-48. PAGEMODCTRL1 Register............................................................................................. 279
4-49. PAGEMODCTRL2 Register............................................................................................. 280
4-50. NCS2ECC1 Register..................................................................................................... 281
4-51. NCS2ECC2 Register..................................................................................................... 283
4-52. NCS3ECC1 Register..................................................................................................... 285
4-53. NCS3ECC2 Register..................................................................................................... 287
20
List of Figures SPRUH16B–April 2014–Revised October 2015
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Texas Instruments TMS320C5517 Digital Signal Processor (Rev. B) User guide

Texas Instruments
Brand
Texas Instruments
Model
TMS320C5517 Digital Signal Processor (Rev. B)
Type
User guide
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