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DSP56321T
NXP DSP56321T Reference guide
Type
Reference guide
Brand
NXP
Size
945.68 KB
Pages
96
Language
English
View document
NXP DSP56321T Reference guide
Type
Reference guide
Brand
NXP
Size
9.70 MB
Category
Software
Pages
360
Language
English
Table of contents
Manual Organization
29
Manual Conventions
29
Features
29
DSP56300 Core Functional Blocks
29
Data ALU
29
Data ALU Registers
29
Multiplier-Accumulator (MAC)
29
Address Generation Unit (AGU)
29
Program Control Unit (PCU)
29
Clock Generator Circuit
29
JTAG TAP and OnCE Module
29
On-Chip Memory
29
Off-Chip Memory Expansion
29
Internal Buses
29
Block Diagram
29
DMA Controller
29
Peripherals
29
GPIO Functionality
29
Timer Module
29
EFCOP
29
Power
30
Ground
30
Clock
30
External Memory Expansion Port (Port A)
30
External Address Bus
30
External Data Bus
30
External Bus Control
30
Interrupt and Mode Control
30
Enhanced Synchronous Serial Interface
30
Enhanced Synchronous Serial Interface
30
Timers
30
JTAG and OnCE Interface
30
Program Memory Space
112
Internal Program Memory
112
Memory Switch Modes—Program Memory
112
Program Bootstrap ROM
112
X Data Memory Space
112
Internal X Data Memory
112
Memory Switch Modes—X Data Memory
112
Internal X I/O Space
112
Y Data Memory Space
112
Internal Y Data Memory
112
Memory Switch Modes—Y Data Memory
112
Internal Y I/O Space
112
External Y I/O Space
112
Summary of Memory Switch Mode Configurations
112
Dynamic Memory Configuration Switching
112
Sixteen-Bit Compatibility Mode Configuration
112
Memory Maps
112
Operating Modes
113
Bootstrap Program
113
Central Processor Unit (CPU) Registers
113
Status Register (SR)
113
Operating Mode Register (OMR)
113
Configuring Interrupts
113
Interrupt Priority Registers (IPRC and IPRP)
113
Interrupt Table Memory Map
113
Processing Interrupt Source Priorities Within an IPL
113
Bus Interface Unit (BIU) Registers
113
Bus Control Register
113
Address Attribute Registers (AAR[0–3])
113
DMA Control Registers 5–0 (DCR[5–0])
113
Device Identification Register (IDR)
113
JTAG Identification (ID) Register
113
JTAG Boundary Scan Register (BSR)
113
Overview
114
Clock Generation Scheme
114
Clock Acronym List
114
CLKGEN External Pins
114
DPLL Description
114
Clock Generator Output Stage
114
EXTAL as Clock Source
114
DPLL as Clock Source
114
Global Clock Generator
114
CLKGEN Programming Model
114
DPLL Clock Control (PCTL) Register
136
DPLL Static Control Register (DSCR)
136
Peripheral Initialization Steps
137
Mapping the Control Registers
137
Reading Status Registers
137
Data Transfer Methods
137
Polling
137
Interrupts
137
Advantages and Disadvantages
137
General-Purpose Input/Output (GPIO)
137
Port B Signals and Registers
137
Port C Signals and Registers
137
Port D Signals and Registers
137
Port E Signals and Registers
137
Triple Timer Signals and Registers
137
Features
138
DSP Core Interface
138
Host Processor Interface
138
Host Port Signals
138
Overview
138
Operation
138
Software Polling
138
Core Interrupts and Host Commands
138
Core DMA Access
138
Host Requests
138
Endian Modes
138
Boot-up Using the HI08 Host Port
138
DSP Core Programming Model
138
Host Control Register (HCR)
138
Host Status Register (HSR)
138
Host Data Direction Register (HDDR)
138
Host Data Register (HDR)
138
Host Base Address Register (HBAR)
138
Host Port Control Register (HPCR)
138
Host Transmit (HTX) Register
138
Host Receive (HRX) Register
138
DSP-Side Registers After Reset
138
Host Programmer Model
138
Interface Control Register (ICR)
138
Command Vector Register (CVR)
138
Interface Status Register (ISR)
138
Interrupt Vector Register (IVR)
138
Receive Data Registers (RXH:RXM:RXL)
138
Transmit Data Registers (TXH:TXM:TXL)
138
Host-Side Registers After Reset
167
Programming Model Quick Reference
167
ESSI Data and Control Signals
168
Serial Transmit Data Signal (STD)
168
Serial Receive Data Signal (SRD)
168
Serial Clock (SCK)
168
Serial Control Signal (SC0)
168
Serial Control Signal (SC1)
168
Serial Control Signal (SC2)
168
Operation
168
ESSI After Reset
168
Initialization
168
Exceptions
168
Operating Modes: Normal, Network, and On-Demand
168
Normal/Network/On-Demand Mode Selection
168
Synchronous/Asynchronous Operating Modes
168
Frame Sync Selection
168
Frame Sync Signal Format
168
Frame Sync Length for Multiple Devices
168
Word Length Frame Sync and Data Word Timing
168
Frame Sync Polarity
168
Byte Format (LSB/MSB) for the Transmitter
168
Flags
168
ESSI Programming Model
168
ESSI Control Register A (CRA)
168
ESSI Control Register B (CRB)
168
ESSI Status Register (SSISR)
168
ESSI Receive Shift Register
168
ESSI Receive Data Register (RX)
168
ESSI Transmit Shift Registers
168
ESSI Transmit Data Registers (TX[2–0])
168
ESSI Time Slot Register (TSR)
168
Transmit Slot Mask Registers (TSMA, TSMB)
168
Receive Slot Mask Registers (RSMA, RSMB)
168
GPIO Signals and Registers
168
Port Control Registers (PCRC and PCRD)
168
Port Direction Registers (PRRC and PRRD)
168
Port Data Registers (PDRC and PDRD)
168
Operating Modes
169
Synchronous Mode
169
Asynchronous Mode
169
Multi-Drop Mode
169
Transmitting Data and Address Characters
169
Wired-OR Mode
169
Idle Line Wakeup
169
View document
NXP DSP56321T Reference guide
Type
Reference guide
Brand
NXP
Size
945.59 KB
Pages
96
Language
English
View document